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//=============================================================================
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//
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// mod_regs_bsc.h
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//
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// BSC (bus state controller) Module register definitions
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//
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//=============================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later
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// version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
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// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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//
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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//=============================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): jskov
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// Contributors:jskov
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// Date: 2002-01-16
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//
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//####DESCRIPTIONEND####
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//
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//=============================================================================
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//--------------------------------------------------------------------------
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// Register definitions
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#define CYGARC_REG_BCR1 0xffffffe0
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#define CYGARC_REG_BCR2 0xffffffe4
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#define CYGARC_REG_WCR1 0xffffffe8
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#define CYGARC_REG_WCR2 0xffffffc0
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#define CYGARC_REG_WCR3 0xffffffc4
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#define CYGARC_REG_MCR 0xffffffec
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#define CYGARC_REG_RTCSR 0xfffffff0
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#define CYGARC_REG_RTCNT 0xfffffff4
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#define CYGARC_REG_RTCOR 0xfffffff8
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#define CYGARC_REG_BSC_WRITE_MAGIC 0xa55a0000
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#define CYGARC_REG_BCR1_A3LW1 0x00004000
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#define CYGARC_REG_BCR1_A3LW0 0x00002000
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#define CYGARC_REG_BCR1_A2ENDIAN 0x00001000 // 0 = big, 1 = little
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#define CYGARC_REG_BCR1_BSTROM 0x00000800
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#define CYGARC_REG_BCR1_AHLW1 0x00000200
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#define CYGARC_REG_BCR1_AHLW0 0x00000100
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#define CYGARC_REG_BCR1_A1LW1 0x00000080
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#define CYGARC_REG_BCR1_A1LW0 0x00000040
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#define CYGARC_REG_BCR1_A0LW1 0x00000020
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#define CYGARC_REG_BCR1_A0LW0 0x00000010
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#define CYGARC_REG_BCR1_A4ENDIAN 0x00000008 // 0 = big, 1 = little
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#define CYGARC_REG_BCR1_DRAM2 0x00000004
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#define CYGARC_REG_BCR1_DRAM1 0x00000002
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#define CYGARC_REG_BCR1_DRAM0 0x00000001
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// Bus widths for areas
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#define CYGARC_REG_BCR2_A4_8 0x00000100
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#define CYGARC_REG_BCR2_A4_16 0x00000200
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#define CYGARC_REG_BCR2_A4_32 0x00000300
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#define CYGARC_REG_BCR2_A3_8 0x00000040
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#define CYGARC_REG_BCR2_A3_16 0x00000080
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#define CYGARC_REG_BCR2_A3_32 0x000000c0
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#define CYGARC_REG_BCR2_A2_8 0x00000010
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#define CYGARC_REG_BCR2_A2_16 0x00000020
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#define CYGARC_REG_BCR2_A2_32 0x00000030
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#define CYGARC_REG_BCR2_A1_8 0x00000004
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#define CYGARC_REG_BCR2_A1_16 0x00000008
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#define CYGARC_REG_BCR2_A1_32 0x0000000c
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// Intercycle wait states
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#define CYGARC_REG_WCR1_A3WI_MASK 0x0000c000 // Intercycle Idle Specification
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#define CYGARC_REG_WCR1_A3WI_SHIFT 14
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#define CYGARC_REG_WCR1_A2WI_MASK 0x00003000
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#define CYGARC_REG_WCR1_A2WI_SHIFT 12
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#define CYGARC_REG_WCR1_A1WI_MASK 0x00000c00
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#define CYGARC_REG_WCR1_A1WI_SHIFT 10
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#define CYGARC_REG_WCR1_A0WI_MASK 0x00000300
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#define CYGARC_REG_WCR1_A0WI_SHIFT 8
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#define CYGARC_REG_WCR1_A3W_MASK 0x000000c0 // waits
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#define CYGARC_REG_WCR1_A3W_SHIFT 6
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#define CYGARC_REG_WCR1_A2W_MASK 0x00000030
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#define CYGARC_REG_WCR1_A2W_SHIFT 4
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#define CYGARC_REG_WCR1_A1W_MASK 0x0000000c
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#define CYGARC_REG_WCR1_A1W_SHIFT 2
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#define CYGARC_REG_WCR1_A0W_MASK 0x00000003
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#define CYGARC_REG_WCR1_A0W_SHIFT 0
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#define CYGARC_REG_WCR1_WI_0 0
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#define CYGARC_REG_WCR1_WI_1 1
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#define CYGARC_REG_WCR1_WI_2 2
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#define CYGARC_REG_WCR1_WI_4 3
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#define CYGARC_REG_WCR1_W_0 0
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#define CYGARC_REG_WCR1_W_1 1
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#define CYGARC_REG_WCR1_W_2 2
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#define CYGARC_REG_WCR1_W_LONG 3
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// Wait states
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#define CYGARC_REG_WCR2_A4WD_MASK 0x0000c000 // External waits for A4
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#define CYGARC_REG_WCR2_A4WD_SHIFT 14
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#define CYGARC_REG_WCR2_A4WM 0x00001000 // external wait mask
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#define CYGARC_REG_WCR2_A3WM 0x00000800 // external wait mask
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#define CYGARC_REG_WCR2_A2WM 0x00000400 // external wait mask
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#define CYGARC_REG_WCR2_A1WM 0x00000200 // external wait mask
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#define CYGARC_REG_WCR2_A0WM 0x00000100 // external wait mask
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#define CYGARC_REG_WCR2_A4WI_MASK 0x0000000c // Intercycle Wait states
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#define CYGARC_REG_WCR2_A4WI_SHIFT 2
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#define CYGARC_REG_WCR2_A4W_MASK 0x00000003 // Wait states
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#define CYGARC_REG_WCR2_A4W_SHIFT 0
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#define CYGARC_REG_WCR2_A4WD_0WS 0
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#define CYGARC_REG_WCR2_A4WD_1WS 1
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#define CYGARC_REG_WCR2_A4WD_4WS 2
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//--------------------------------------------------------------------------
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// Additional type definitions
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#if (CYGARC_SH_MOD_BCN > 1)
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#define CYGARC_REG_BCR3 0xfffffffc
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#endif
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//-----------------------------------------------------------------------------
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// Calculate constants needed to drive the proper SDRAM refresh rate. Argument
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// is delay between required refresh events in microseconds (us). Should be
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// available off the SDRAM spec sheet.
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// These should be a part of a fully CDLicized memory controller setup.
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#define CYGARC_RTCSR_PRESCALE(_r_) \
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(((CYGHWR_HAL_SH_BOARD_SPEED*(_r_)/(4*1000000))<256) ? 4 : \
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((CYGHWR_HAL_SH_BOARD_SPEED*(_r_)/(16*1000000))<256) ? 16 : \
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((CYGHWR_HAL_SH_BOARD_SPEED*(_r_)/(64*1000000))<256) ? 64 : \
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((CYGHWR_HAL_SH_BOARD_SPEED*(_r_)/(256*1000000))<256) ? 256 : \
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((CYGHWR_HAL_SH_BOARD_SPEED*(_r_)/(1024*1000000))<256) ? 1024 : \
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((CYGHWR_HAL_SH_BOARD_SPEED*(_r_)/(2048*1000000))<256) ? 2048 : 4096)
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// These two macros provide the static values we need to stuff into the
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// registers.
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#define CYGARC_RTCSR_CKSx(_r_) \
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(( 4 == CYGARC_RTCSR_PRESCALE(_r_)) ? 0x08 : \
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( 16 == CYGARC_RTCSR_PRESCALE(_r_)) ? 0x10 : \
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( 64 == CYGARC_RTCSR_PRESCALE(_r_)) ? 0x18 : \
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( 256 == CYGARC_RTCSR_PRESCALE(_r_)) ? 0x20 : \
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(1024 == CYGARC_RTCSR_PRESCALE(_r_)) ? 0x28 : \
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(2048 == CYGARC_RTCSR_PRESCALE(_r_)) ? 0x30 : 0x38 )
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#define CYGARC_RTCSR_N(_r_) \
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(CYGHWR_HAL_SH_BOARD_SPEED*(_r_)/(CYGARC_RTCSR_PRESCALE(_r_)*1000000))
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