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#ifndef CYGONCE_VAR_INTR_H
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#define CYGONCE_VAR_INTR_H
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//==========================================================================
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//
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// var_intr.h
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//
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// HAL variant interrupt and clock support
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//
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//==========================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later
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// version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
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// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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//
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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//==========================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): jskov
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// Contributors: jskov,
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// Date: 1999-04-24
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// Purpose: Define Interrupt support
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// Description: The macros defined here provide the HAL APIs for handling
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// interrupts and the clock.
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//
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// Usage:
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// #include <cyg/hal/hal_intr.h>
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// ...
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//
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//
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//####DESCRIPTIONEND####
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//
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//==========================================================================
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#include <pkgconf/hal.h>
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#include CYGBLD_HAL_CPU_MODULES_H // INTC module selection
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//--------------------------------------------------------------------------
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// Optional platform overrides and fallbacks
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#include <cyg/hal/plf_intr.h>
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#ifndef CYGPRI_HAL_INTERRUPT_ACKNOWLEDGE_PLF
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# define CYGPRI_HAL_INTERRUPT_ACKNOWLEDGE_PLF(vec)
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#endif
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#ifndef CYGPRI_HAL_INTERRUPT_CONFIGURE_PLF
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# define CYGPRI_HAL_INTERRUPT_CONFIGURE_PLF(vec, level, up)
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#endif
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//----------------------------------------------------------------------------
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// Additional vectors provided by INTC V1
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#if (CYGARC_SH_MOD_INTC == 1)
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#ifndef CYGPRI_HAL_INTERRUPT_UPDATE_LEVEL_PLF
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# define CYGPRI_HAL_INTERRUPT_UPDATE_LEVEL_PLF(vec, level) \
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case CYGNUM_HAL_INTERRUPT_NMI: \
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/* fall through */ \
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case CYGNUM_HAL_INTERRUPT_LVL4 ... CYGNUM_HAL_INTERRUPT_LVL_MAX: \
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/* Cannot change levels */ \
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break;
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#endif
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#define CYGNUM_HAL_INTERRUPT_LVL8 9
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#define CYGNUM_HAL_INTERRUPT_LVL9 10
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#define CYGNUM_HAL_INTERRUPT_LVL10 11
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#define CYGNUM_HAL_INTERRUPT_LVL11 12
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#define CYGNUM_HAL_INTERRUPT_LVL12 13
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#define CYGNUM_HAL_INTERRUPT_LVL13 14
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#define CYGNUM_HAL_INTERRUPT_LVL14 15
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#define CYGNUM_HAL_INTERRUPT_DMAC0_TE 16
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#define CYGNUM_HAL_INTERRUPT_DMAC1_TE 17
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#define CYGNUM_HAL_INTERRUPT_WDT_ITI 18
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#define CYGNUM_HAL_INTERRUPT_REF_CMI 19
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#define CYGNUM_HAL_INTERRUPT_EDMAC_EINT 20
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#define CYGNUM_HAL_INTERRUPT_FRT_ICI 21
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#define CYGNUM_HAL_INTERRUPT_FRT_OCI 22
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#define CYGNUM_HAL_INTERRUPT_FRT_OVI 23
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#define CYGNUM_HAL_INTERRUPT_TPU0_TGI0A 24
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#define CYGNUM_HAL_INTERRUPT_TPU0_TGI0B 25
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#define CYGNUM_HAL_INTERRUPT_TPU0_TGI0C 26
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#define CYGNUM_HAL_INTERRUPT_TPU0_TGI0D 27
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#define CYGNUM_HAL_INTERRUPT_TPU0_TGI0V 28
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#define CYGNUM_HAL_INTERRUPT_TPU1_TGI1A 29
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#define CYGNUM_HAL_INTERRUPT_TPU1_TGI1B 30
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#define CYGNUM_HAL_INTERRUPT_TPU1_TGI1V 31
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#define CYGNUM_HAL_INTERRUPT_TPU1_TGI1U 32
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#define CYGNUM_HAL_INTERRUPT_TPU2_TGI2A 33
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#define CYGNUM_HAL_INTERRUPT_TPU2_TGI2B 34
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#define CYGNUM_HAL_INTERRUPT_TPU2_TGI2V 35
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#define CYGNUM_HAL_INTERRUPT_TPU2_TGI2U 36
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#define CYGNUM_HAL_INTERRUPT_SCIF1_ERI1 37
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#define CYGNUM_HAL_INTERRUPT_SCIF1_RXI1 38
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#define CYGNUM_HAL_INTERRUPT_SCIF1_BRI1 39
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#define CYGNUM_HAL_INTERRUPT_SCIF1_TXI1 40
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#define CYGNUM_HAL_INTERRUPT_SCIF2_ERI2 41
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#define CYGNUM_HAL_INTERRUPT_SCIF2_RXI2 42
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#define CYGNUM_HAL_INTERRUPT_SCIF2_BRI2 43
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#define CYGNUM_HAL_INTERRUPT_SCIF2_TXI2 44
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#define CYGNUM_HAL_INTERRUPT_SIO0_RERI0 45
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#define CYGNUM_HAL_INTERRUPT_SIO0_TERI0 46
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#define CYGNUM_HAL_INTERRUPT_SIO0_RDFI0 47
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#define CYGNUM_HAL_INTERRUPT_SIO0_TDEI0 48
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#define CYGNUM_HAL_INTERRUPT_SIO1_RERI1 49
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#define CYGNUM_HAL_INTERRUPT_SIO1_TERI1 50
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#define CYGNUM_HAL_INTERRUPT_SIO1_RDFI1 51
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#define CYGNUM_HAL_INTERRUPT_SIO1_TDEI1 52
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#define CYGNUM_HAL_INTERRUPT_SIO2_RERI2 53
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#define CYGNUM_HAL_INTERRUPT_SIO2_TERI2 54
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#define CYGNUM_HAL_INTERRUPT_SIO2_RDFI2 55
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#define CYGNUM_HAL_INTERRUPT_SIO2_TDEI2 56
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#define CYGNUM_HAL_INTERRUPT_LVL_MAX CYGNUM_HAL_INTERRUPT_LVL14
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#undef CYGNUM_HAL_ISR_MAX
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#ifdef CYGNUM_HAL_ISR_PLF_MAX
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# define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_ISR_PLF_MAX
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#else
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# define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_INTERRUPT_SIO2_TDEI2
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#endif
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// The vector used by the Real time clock
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#ifndef CYGNUM_HAL_INTERRUPT_RTC
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# define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_FRT_OCI
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#endif
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#elif (CYGARC_SH_MOD_INTC == 2)
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#ifndef CYGPRI_HAL_INTERRUPT_UPDATE_LEVEL_PLF
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# define CYGPRI_HAL_INTERRUPT_UPDATE_LEVEL_PLF(vec, level) \
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case CYGNUM_HAL_INTERRUPT_NMI: \
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/* Cannot change levels */ \
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break;
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#endif
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#define CYGNUM_HAL_INTERRUPT_DMAC0_DEI0 9
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#define CYGNUM_HAL_INTERRUPT_DMAC1_DEI1 10
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#define CYGNUM_HAL_INTERRUPT_DMAC2_DEI2 11
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#define CYGNUM_HAL_INTERRUPT_DMAC3_DEI3 12
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#define CYGNUM_HAL_INTERRUPT_MTU0_TGI0A 13
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#define CYGNUM_HAL_INTERRUPT_MTU0_TGI0B 14
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#define CYGNUM_HAL_INTERRUPT_MTU0_TGI0C 15
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#define CYGNUM_HAL_INTERRUPT_MTU0_TGI0D 16
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#define CYGNUM_HAL_INTERRUPT_MTU0_TGI0V 17
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#define CYGNUM_HAL_INTERRUPT_MTU1_TGI1A 18
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#define CYGNUM_HAL_INTERRUPT_MTU1_TGI1B 19
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#define CYGNUM_HAL_INTERRUPT_MTU1_TGI1V 20
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#define CYGNUM_HAL_INTERRUPT_MTU1_TGI1U 21
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#define CYGNUM_HAL_INTERRUPT_MTU2_TGI2A 22
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#define CYGNUM_HAL_INTERRUPT_MTU2_TGI2B 23
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#define CYGNUM_HAL_INTERRUPT_MTU2_TGI2V 24
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#define CYGNUM_HAL_INTERRUPT_MTU2_TGI2U 25
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#define CYGNUM_HAL_INTERRUPT_MTU3_TGI3A 26
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#define CYGNUM_HAL_INTERRUPT_MTU3_TGI3B 27
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#define CYGNUM_HAL_INTERRUPT_MTU3_TGI3C 28
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#define CYGNUM_HAL_INTERRUPT_MTU3_TGI3D 29
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#define CYGNUM_HAL_INTERRUPT_MTU3_TGI3V 30
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#define CYGNUM_HAL_INTERRUPT_MTU4_TGI4A 31
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#define CYGNUM_HAL_INTERRUPT_MTU4_TGI4B 32
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#define CYGNUM_HAL_INTERRUPT_MTU4_TGI4C 33
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#define CYGNUM_HAL_INTERRUPT_MTU4_TGI4D 34
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#define CYGNUM_HAL_INTERRUPT_MTU4_TGI4V 35
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#define CYGNUM_HAL_INTERRUPT_SCI0_ERI0 36
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#define CYGNUM_HAL_INTERRUPT_SCI0_RXI0 37
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#define CYGNUM_HAL_INTERRUPT_SCI0_TXI0 38
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#define CYGNUM_HAL_INTERRUPT_SCI0_TEI0 39
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#define CYGNUM_HAL_INTERRUPT_SCI1_ERI1 40
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#define CYGNUM_HAL_INTERRUPT_SCI1_RXI1 41
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#define CYGNUM_HAL_INTERRUPT_SCI1_TXI1 42
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#define CYGNUM_HAL_INTERRUPT_SCI1_TEI1 43
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#define CYGNUM_HAL_INTERRUPT_AD_ADI0 44
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#define CYGNUM_HAL_INTERRUPT_AD_ADI1 45
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#define CYGNUM_HAL_INTERRUPT_DTC_SWDTCE 46
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#define CYGNUM_HAL_INTERRUPT_CMT0_CMI0 47
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#define CYGNUM_HAL_INTERRUPT_CMT1_CMI1 48
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#define CYGNUM_HAL_INTERRUPT_WDT_ITI 49
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#define CYGNUM_HAL_INTERRUPT_BSC_CMI 50
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#define CYGNUM_HAL_INTERRUPT_IO_OEI 51
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#define CYGNUM_HAL_INTERRUPT_VAR_RESERVED 52 // just to catch bad assignments
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#undef CYGNUM_HAL_ISR_MAX
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#ifdef CYGNUM_HAL_ISR_PLF_MAX
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# define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_ISR_PLF_MAX
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#else
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# define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_INTERRUPT_VAR_RESERVED
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#endif
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// eCos vector this entry decodes to , actual HW interrupt vector
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#define CYGHWR_HAL_SH_SH2_CUSTOM_INTERRUPT_LAYOUT \
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exception_vector_int CYGNUM_HAL_INTERRUPT_LVL0 , 1 ; \
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exception_vector_int CYGNUM_HAL_INTERRUPT_LVL1 , 2 ; \
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exception_vector_int CYGNUM_HAL_INTERRUPT_LVL2 , 3 ; \
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exception_vector_int CYGNUM_HAL_INTERRUPT_LVL3 , 4 ; \
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exception_vector_int CYGNUM_HAL_INTERRUPT_LVL4 , 5 ; \
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exception_vector_int CYGNUM_HAL_INTERRUPT_LVL5 , 6 ; \
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exception_vector_int CYGNUM_HAL_INTERRUPT_LVL6 , 7 ; \
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exception_vector_int CYGNUM_HAL_INTERRUPT_LVL7 , 8 ; \
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\
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exception_vector_int CYGNUM_HAL_INTERRUPT_DMAC0_DEI0 , 9 ; \
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exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 10 ; \
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exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 11 ; \
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exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 12 ; \
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exception_vector_int CYGNUM_HAL_INTERRUPT_DMAC1_DEI1 , 13 ; \
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exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 14 ; \
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exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 15 ; \
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exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 16 ; \
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exception_vector_int CYGNUM_HAL_INTERRUPT_DMAC2_DEI2 , 17 ; \
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exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 18 ; \
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exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 19 ; \
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exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 20 ; \
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exception_vector_int CYGNUM_HAL_INTERRUPT_DMAC3_DEI3 , 21 ; \
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exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 22 ; \
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exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 23 ; \
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exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 24 ; \
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exception_vector_int CYGNUM_HAL_INTERRUPT_MTU0_TGI0A , 25 ; \
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exception_vector_int CYGNUM_HAL_INTERRUPT_MTU0_TGI0B , 26 ; \
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exception_vector_int CYGNUM_HAL_INTERRUPT_MTU0_TGI0C , 27 ; \
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exception_vector_int CYGNUM_HAL_INTERRUPT_MTU0_TGI0D , 28 ; \
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exception_vector_int CYGNUM_HAL_INTERRUPT_MTU0_TGI0V , 29 ; \
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exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 30 ; \
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exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 31 ; \
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exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 32 ; \
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exception_vector_int CYGNUM_HAL_INTERRUPT_MTU1_TGI1A , 33 ; \
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exception_vector_int CYGNUM_HAL_INTERRUPT_MTU1_TGI1B , 34 ; \
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exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 35 ; \
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exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 36 ; \
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exception_vector_int CYGNUM_HAL_INTERRUPT_MTU1_TGI1V , 37 ; \
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exception_vector_int CYGNUM_HAL_INTERRUPT_MTU1_TGI1U , 38 ; \
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exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 39 ; \
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exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 40 ; \
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exception_vector_int CYGNUM_HAL_INTERRUPT_MTU2_TGI2A , 41 ; \
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exception_vector_int CYGNUM_HAL_INTERRUPT_MTU2_TGI2B , 42 ; \
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exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 43 ; \
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exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 44 ; \
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exception_vector_int CYGNUM_HAL_INTERRUPT_MTU2_TGI2V , 45 ; \
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exception_vector_int CYGNUM_HAL_INTERRUPT_MTU2_TGI2U , 46 ; \
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exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 47 ; \
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exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 48 ; \
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exception_vector_int CYGNUM_HAL_INTERRUPT_MTU3_TGI3A , 49 ; \
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exception_vector_int CYGNUM_HAL_INTERRUPT_MTU3_TGI3B , 50 ; \
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exception_vector_int CYGNUM_HAL_INTERRUPT_MTU3_TGI3C , 51 ; \
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exception_vector_int CYGNUM_HAL_INTERRUPT_MTU3_TGI3D , 52 ; \
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exception_vector_int CYGNUM_HAL_INTERRUPT_MTU3_TGI3V , 53 ; \
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exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 54 ; \
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exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 55 ; \
|
273 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 56 ; \
|
274 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_MTU4_TGI4A , 57 ; \
|
275 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_MTU4_TGI4B , 58 ; \
|
276 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_MTU4_TGI4C , 59 ; \
|
277 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_MTU4_TGI4D , 60 ; \
|
278 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_MTU4_TGI4V , 61 ; \
|
279 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 62 ; \
|
280 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 63 ; \
|
281 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 64 ; \
|
282 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_SCI0_ERI0 , 65 ; \
|
283 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_SCI0_RXI0 , 66 ; \
|
284 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_SCI0_TXI0 , 67 ; \
|
285 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_SCI0_TEI0 , 68 ; \
|
286 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_SCI1_ERI1 , 69 ; \
|
287 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_SCI1_RXI1 , 70 ; \
|
288 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_SCI1_TXI1 , 71 ; \
|
289 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_SCI1_TEI1 , 72 ; \
|
290 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_AD_ADI0 , 73 ; \
|
291 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_AD_ADI1 , 74 ; \
|
292 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 75 ; \
|
293 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 76 ; \
|
294 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_DTC_SWDTCE , 77 ; \
|
295 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 78 ; \
|
296 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 79 ; \
|
297 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 80 ; \
|
298 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_CMT0_CMI0 , 81 ; \
|
299 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 82 ; \
|
300 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 83 ; \
|
301 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 84 ; \
|
302 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_CMT1_CMI1 , 85 ; \
|
303 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 86 ; \
|
304 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 87 ; \
|
305 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 88 ; \
|
306 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_WDT_ITI , 89 ; \
|
307 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_BSC_CMI , 90 ; \
|
308 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 91 ; \
|
309 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 92 ; \
|
310 |
|
|
exception_vector_int CYGNUM_HAL_INTERRUPT_BSC_CMI , 93 ; \
|
311 |
|
|
.set vecno, CYGNUM_HAL_INTERRUPT_VAR_RESERVED ; \
|
312 |
|
|
.rept (256-CYGNUM_HAL_INTERRUPT_VAR_RESERVED) ; \
|
313 |
|
|
exception_vector_int vecno ; \
|
314 |
|
|
.set vecno, vecno+1 ; \
|
315 |
|
|
.endr
|
316 |
|
|
|
317 |
|
|
// The vector used by the Real time clock
|
318 |
|
|
#ifndef CYGNUM_HAL_INTERRUPT_RTC
|
319 |
|
|
# define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_CMT0_CMI0
|
320 |
|
|
#endif
|
321 |
|
|
|
322 |
|
|
#else
|
323 |
|
|
|
324 |
|
|
# error "No vectors defined for this INTC type"
|
325 |
|
|
|
326 |
|
|
#endif
|
327 |
|
|
|
328 |
|
|
//----------------------------------------------------------------------------
|
329 |
|
|
// Platform may provide extensions to the interrupt configuration functions
|
330 |
|
|
// via these macros. The first macro is put inside the functions's
|
331 |
|
|
// switch statements, the last two called as functions.
|
332 |
|
|
#ifndef CYGPRI_HAL_INTERRUPT_UPDATE_LEVEL_PLF
|
333 |
|
|
# define CYGPRI_HAL_INTERRUPT_UPDATE_LEVEL_PLF(vec, level)
|
334 |
|
|
# define CYGPRI_HAL_INTERRUPT_ACKNOWLEDGE_PLF(vec)
|
335 |
|
|
# define CYGPRI_HAL_INTERRUPT_CONFIGURE_PLF(vec)
|
336 |
|
|
#endif
|
337 |
|
|
|
338 |
|
|
#ifndef __ASSEMBLER__
|
339 |
|
|
//--------------------------------------------------------------------------
|
340 |
|
|
// Clock control, using Free-running Timer to match on compare register A
|
341 |
|
|
|
342 |
|
|
#include <cyg/hal/sh_regs.h> // register definitions
|
343 |
|
|
#include <cyg/hal/hal_io.h> // io macros
|
344 |
|
|
#include <cyg/infra/cyg_ass.h> // CYG_FAIL
|
345 |
|
|
|
346 |
|
|
#if defined(CYGARC_SH_MOD_FRT)
|
347 |
|
|
#define HAL_CLOCK_VAR_INITIALIZE( _period_ ) \
|
348 |
|
|
CYG_MACRO_START \
|
349 |
|
|
register cyg_uint8 _tier_; \
|
350 |
|
|
\
|
351 |
|
|
/* Disable interrupts while programming the timer */ \
|
352 |
|
|
HAL_READ_UINT8(CYGARC_REG_TIER, _tier_); \
|
353 |
|
|
HAL_WRITE_UINT8(CYGARC_REG_TIER, 0); \
|
354 |
|
|
\
|
355 |
|
|
/* Clear counter register */ \
|
356 |
|
|
HAL_WRITE_UINT8(CYGARC_REG_FRC, 0); \
|
357 |
|
|
/* Set compare A register */ \
|
358 |
|
|
HAL_WRITE_UINT8(CYGARC_REG_TOCR, CYGARC_REG_TOCR_OLVLA); \
|
359 |
|
|
HAL_WRITE_UINT16(CYGARC_REG_OCR, _period_); \
|
360 |
|
|
\
|
361 |
|
|
/* Enable match A counter clear */ \
|
362 |
|
|
HAL_WRITE_UINT8(CYGARC_REG_FTCSR, CYGARC_REG_FTCSR_CCLRA); \
|
363 |
|
|
/* Set interrupt prescaling */ \
|
364 |
|
|
HAL_WRITE_UINT8(CYGARC_REG_TCR, \
|
365 |
|
|
((8==CYGHWR_HAL_SH_FRT_PRESCALE) ? \
|
366 |
|
|
CYGARC_REG_TCR_CLK_8 : \
|
367 |
|
|
(32==CYGHWR_HAL_SH_FRT_PRESCALE) ? \
|
368 |
|
|
CYGARC_REG_TCR_CLK_32: \
|
369 |
|
|
(128==CYGHWR_HAL_SH_FRT_PRESCALE) ? \
|
370 |
|
|
CYGARC_REG_TCR_CLK_128:CYGARC_REG_TCR_CLK_EXT)); \
|
371 |
|
|
\
|
372 |
|
|
\
|
373 |
|
|
CYG_MACRO_END
|
374 |
|
|
|
375 |
|
|
// HAL_CLOCK_VAR_INITIALIZE is called from hal_variant_init since the
|
376 |
|
|
// FRT is also used by the hal_delay_us code.
|
377 |
|
|
#define HAL_CLOCK_INITIALIZE( _period_ ) \
|
378 |
|
|
CYG_MACRO_START \
|
379 |
|
|
register cyg_uint8 _tier_; \
|
380 |
|
|
\
|
381 |
|
|
CYG_ASSERT((cyg_uint16)(_period_) < (cyg_uint16)0xfffe, \
|
382 |
|
|
"period too large for 16bit FRT"); \
|
383 |
|
|
\
|
384 |
|
|
/* Disable interrupts while programming the timer */ \
|
385 |
|
|
HAL_READ_UINT8(CYGARC_REG_TIER, _tier_); \
|
386 |
|
|
HAL_WRITE_UINT8(CYGARC_REG_TIER, 0); \
|
387 |
|
|
\
|
388 |
|
|
/* Set compare A register */ \
|
389 |
|
|
HAL_WRITE_UINT8(CYGARC_REG_TOCR, CYGARC_REG_TOCR_OLVLA); \
|
390 |
|
|
HAL_WRITE_UINT16(CYGARC_REG_OCR, _period_); \
|
391 |
|
|
\
|
392 |
|
|
/* Enable interrupt */ \
|
393 |
|
|
_tier_ |= CYGARC_REG_TIER_OCIAE; \
|
394 |
|
|
HAL_WRITE_UINT8(CYGARC_REG_TIER, _tier_); \
|
395 |
|
|
\
|
396 |
|
|
CYG_MACRO_END
|
397 |
|
|
|
398 |
|
|
#define HAL_CLOCK_RESET( _vector_, _period_ ) \
|
399 |
|
|
CYG_MACRO_START \
|
400 |
|
|
register cyg_uint8 _ftcsr_; \
|
401 |
|
|
\
|
402 |
|
|
/* Clear match flag */ \
|
403 |
|
|
HAL_READ_UINT8(CYGARC_REG_FTCSR, _ftcsr_); \
|
404 |
|
|
_ftcsr_ &= ~CYGARC_REG_FTCSR_OCFA; \
|
405 |
|
|
HAL_WRITE_UINT8(CYGARC_REG_FTCSR, _ftcsr_); \
|
406 |
|
|
\
|
407 |
|
|
CYG_MACRO_END
|
408 |
|
|
|
409 |
|
|
#define HAL_CLOCK_READ( _pvalue_ ) \
|
410 |
|
|
CYG_MACRO_START \
|
411 |
|
|
register cyg_uint16 _frc_; \
|
412 |
|
|
\
|
413 |
|
|
HAL_READ_UINT16(CYGARC_REG_FRC, _frc_); \
|
414 |
|
|
\
|
415 |
|
|
*(_pvalue_) = _frc_; \
|
416 |
|
|
CYG_MACRO_END
|
417 |
|
|
|
418 |
|
|
#elif defined(CYGARC_SH_MOD_CMT)
|
419 |
|
|
|
420 |
|
|
/* Compare Match Timer 0 is used for the eCos kernel RTC */
|
421 |
|
|
#define HAL_CLOCK_VAR_INITIALIZE( _period_ ) \
|
422 |
|
|
CYG_MACRO_START \
|
423 |
|
|
register cyg_uint16 _tmp_; \
|
424 |
|
|
\
|
425 |
|
|
/* Disable timer while programming it */ \
|
426 |
|
|
HAL_READ_UINT16(CYGARC_REG_CMSTR, _tmp_); \
|
427 |
|
|
HAL_WRITE_UINT16(CYGARC_REG_CMSTR, _tmp_ & ~CYGARC_REG_CMSTR_STR0); \
|
428 |
|
|
\
|
429 |
|
|
/* Clear counter register */ \
|
430 |
|
|
HAL_WRITE_UINT16(CYGARC_REG_CMCNT0, 0); \
|
431 |
|
|
/* Set compare 0 register */ \
|
432 |
|
|
HAL_WRITE_UINT16(CYGARC_REG_CMCOR0, _period_); \
|
433 |
|
|
\
|
434 |
|
|
/* Set prescaling and disable interrupts */ \
|
435 |
|
|
HAL_WRITE_UINT16(CYGARC_REG_CMCSR0, \
|
436 |
|
|
((8==CYGHWR_HAL_SH_CMT_PRESCALE) ? \
|
437 |
|
|
CYGARC_REG_CMCSR_CLK_8 : \
|
438 |
|
|
(32==CYGHWR_HAL_SH_CMT_PRESCALE) ? \
|
439 |
|
|
CYGARC_REG_CMCSR_CLK_32: \
|
440 |
|
|
(128==CYGHWR_HAL_SH_CMT_PRESCALE) ? \
|
441 |
|
|
CYGARC_REG_CMCSR_CLK_128:CYGARC_REG_CMCSR_CLK_512)); \
|
442 |
|
|
\
|
443 |
|
|
/* Start timer */ \
|
444 |
|
|
HAL_WRITE_UINT16(CYGARC_REG_CMSTR, _tmp_ | CYGARC_REG_CMSTR_STR0); \
|
445 |
|
|
\
|
446 |
|
|
CYG_MACRO_END
|
447 |
|
|
|
448 |
|
|
// HAL_CLOCK_VAR_INITIALIZE is called from hal_variant_init since the
|
449 |
|
|
// CMT0 is also used by the hal_delay_us code.
|
450 |
|
|
#define HAL_CLOCK_INITIALIZE( _period_ ) \
|
451 |
|
|
CYG_MACRO_START \
|
452 |
|
|
register cyg_uint16 _tmp_; \
|
453 |
|
|
\
|
454 |
|
|
CYG_ASSERT((cyg_uint16)(_period_) < (cyg_uint16)0xfffe, \
|
455 |
|
|
"period too large for 16bit CMT"); \
|
456 |
|
|
\
|
457 |
|
|
/* Disable timer while programming it */ \
|
458 |
|
|
HAL_READ_UINT16(CYGARC_REG_CMSTR, _tmp_); \
|
459 |
|
|
HAL_WRITE_UINT16(CYGARC_REG_CMSTR, _tmp_ & ~CYGARC_REG_CMSTR_STR0); \
|
460 |
|
|
\
|
461 |
|
|
/* Clear counter register */ \
|
462 |
|
|
HAL_WRITE_UINT16(CYGARC_REG_CMCNT0, 0); \
|
463 |
|
|
/* Set compare 0 register */ \
|
464 |
|
|
HAL_WRITE_UINT16(CYGARC_REG_CMCOR0, _period_); \
|
465 |
|
|
\
|
466 |
|
|
/* Set prescaling and enable interrupts */ \
|
467 |
|
|
HAL_WRITE_UINT16(CYGARC_REG_CMCSR0, CYGARC_REG_CMCSR_CMIE | \
|
468 |
|
|
((8==CYGHWR_HAL_SH_CMT_PRESCALE) ? \
|
469 |
|
|
CYGARC_REG_CMCSR_CLK_8 : \
|
470 |
|
|
(32==CYGHWR_HAL_SH_CMT_PRESCALE) ? \
|
471 |
|
|
CYGARC_REG_CMCSR_CLK_32: \
|
472 |
|
|
(128==CYGHWR_HAL_SH_CMT_PRESCALE) ? \
|
473 |
|
|
CYGARC_REG_CMCSR_CLK_128:CYGARC_REG_CMCSR_CLK_512)); \
|
474 |
|
|
\
|
475 |
|
|
/* Start timer */ \
|
476 |
|
|
HAL_WRITE_UINT16(CYGARC_REG_CMSTR, _tmp_ | CYGARC_REG_CMSTR_STR0); \
|
477 |
|
|
\
|
478 |
|
|
CYG_MACRO_END
|
479 |
|
|
|
480 |
|
|
#define HAL_CLOCK_RESET( _vector_, _period_ ) \
|
481 |
|
|
CYG_MACRO_START \
|
482 |
|
|
register cyg_uint16 _tmp_; \
|
483 |
|
|
\
|
484 |
|
|
/* Clear match flag */ \
|
485 |
|
|
HAL_READ_UINT16(CYGARC_REG_CMCSR0, _tmp_); \
|
486 |
|
|
_tmp_ &= ~CYGARC_REG_CMCSR_CMF; \
|
487 |
|
|
HAL_WRITE_UINT16(CYGARC_REG_CMCSR0, _tmp_); \
|
488 |
|
|
\
|
489 |
|
|
CYG_MACRO_END
|
490 |
|
|
|
491 |
|
|
#define HAL_CLOCK_READ( _pvalue_ ) \
|
492 |
|
|
CYG_MACRO_START \
|
493 |
|
|
register cyg_uint16 _tmp_; \
|
494 |
|
|
\
|
495 |
|
|
HAL_READ_UINT16(CYGARC_REG_CMCNT0, _tmp_); \
|
496 |
|
|
\
|
497 |
|
|
*(_pvalue_) = _tmp_; \
|
498 |
|
|
CYG_MACRO_END
|
499 |
|
|
|
500 |
|
|
|
501 |
|
|
|
502 |
|
|
#else
|
503 |
|
|
# error "No RTC handling defined"
|
504 |
|
|
#endif
|
505 |
|
|
|
506 |
|
|
|
507 |
|
|
|
508 |
|
|
#ifdef CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY
|
509 |
|
|
#define HAL_CLOCK_LATENCY( _pvalue_ ) HAL_CLOCK_READ(_pvalue_)
|
510 |
|
|
#endif
|
511 |
|
|
|
512 |
|
|
|
513 |
|
|
//----------------------------------------------------------------------------
|
514 |
|
|
// Reset.
|
515 |
|
|
#ifndef HAL_PLATFORM_RESET
|
516 |
|
|
#define HAL_PLATFORM_RESET() \
|
517 |
|
|
CYG_MACRO_START \
|
518 |
|
|
HAL_WRITE_UINT16(CYGARC_REG_RSTCSR_W, CYGARC_REG_RSTCSR_W_RSTx_MAGIC|CYGARC_REG_RSTCSR_RSTE); \
|
519 |
|
|
HAL_WRITE_UINT16(CYGARC_REG_WTCNT_W, CYGARC_REG_WTCNT_W_MAGIC|0xfe); \
|
520 |
|
|
HAL_WRITE_UINT16(CYGARC_REG_WTCSR_W, CYGARC_REG_WTCSR_W_MAGIC|CYGARC_REG_WTCSR_TME|CYGARC_REG_WTCSR_WTIT); \
|
521 |
|
|
/* wait for it */ \
|
522 |
|
|
for(;;) ; \
|
523 |
|
|
CYG_MACRO_END
|
524 |
|
|
#else
|
525 |
|
|
#define HAL_PLATFORM_RESET()
|
526 |
|
|
#endif
|
527 |
|
|
|
528 |
|
|
#endif // __ASSEMBLER__
|
529 |
|
|
|
530 |
|
|
//--------------------------------------------------------------------------
|
531 |
|
|
#endif // ifndef CYGONCE_VAR_INTR_H
|
532 |
|
|
// End of var_intr.h
|