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# ====================================================================
#
#      hal_sh_sh3.cdl
#
#      SH3 variant HAL package configuration data
#
# ====================================================================
## ####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later
## version.
##
## eCos is distributed in the hope that it will be useful, but WITHOUT
## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License
## along with eCos; if not, write to the Free Software Foundation, Inc.,
## 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
##
## As a special exception, if other files instantiate templates or use
## macros or inline functions from this file, or you compile this file
## and link it with other works to produce a work based on this file,
## this file does not by itself cause the resulting work to be covered by
## the GNU General Public License. However the source code for this file
## must still be made available in accordance with section (3) of the GNU
## General Public License v2.
##
## This exception does not invalidate any other reasons why a work based
## on this file might be covered by the GNU General Public License.
## -------------------------------------------
## ####ECOSGPLCOPYRIGHTEND####
# ====================================================================
######DESCRIPTIONBEGIN####
#
# Author(s):      jskov
# Original data:  jskov
# Contributors:
# Date:           2000-10-30
#
#####DESCRIPTIONEND####
#
# ====================================================================
 
cdl_package CYGPKG_HAL_SH_SH3 {
    display       "SH3 variant"
    parent        CYGPKG_HAL_SH
    hardware
    include_dir   cyg/hal
    define_header hal_sh_sh3.h
    description   "
        The SH3 (SuperH 3) variant HAL package provides generic
        support for SH3 variant CPUs."
 
    define_proc {
        puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H   "
        puts $::cdl_header "#define CYGBLD_HAL_VAR_EXCEPTION_MODEL_H   "
        puts $::cdl_header "#define CYGBLD_HAL_VAR_EXCEPTION_MODEL_INC "
        puts $::cdl_header "#define CYGBLD_HAL_VAR_INTR_MODEL_H   "
    }
 
    compile       sh3_sci.c sh3_scif.c var_misc.c variant.S
 
    # The "-o file" is a workaround for CR100958 - without it the
    # output file would end up in the source directory under CygWin.
    # n.b. grep does not behave itself under win32
    make -priority 1 {
        /include/cyg/hal/sh3_offsets.inc : /src/var_mk_defs.c
        $(CC) $(ACTUAL_CFLAGS) $(INCLUDE_PATH) -Wp,-MD,sh3_offsets.tmp -o var_mk_defs.tmp -S $<
        fgrep .equ var_mk_defs.tmp | sed s/#// > $@
        @echo $@ ": \\" > $(notdir $@).deps
        @tail -n +2 sh3_offsets.tmp >> $(notdir $@).deps
        @echo >> $(notdir $@).deps
        @rm sh3_offsets.tmp var_mk_defs.tmp
    }
 
    # CPU variant supported
    cdl_option CYGPKG_HAL_SH_7707A {
        display       "SH 7707A microprocessor"
        parent        CYGPKG_HAL_SH_CPU
        implements    CYGINT_HAL_SH_VARIANT
        implements    CYGINT_HAL_SH_CPG_T2
        default_value 0
        no_define
        define        -file=system.h CYGPKG_HAL_SH_7707A
        description "
            The SH3 7707A microprocessor. This is an embedded part that in
            addition to the SH3 processor core has built in peripherals
            such as memory controllers, serial ports, LCD controller and
            timers/counters."
        define_proc {
            puts $cdl_system_header "#define CYGBLD_HAL_CPU_MODULES_H "
        }
    }
 
    cdl_option CYGPKG_HAL_SH_7708 {
        display       "SH 7708 microprocessor"
        parent        CYGPKG_HAL_SH_CPU
        implements    CYGINT_HAL_SH_VARIANT
        implements    CYGINT_HAL_SH_CPG_T1
        default_value 0
        no_define
        define        -file=system.h CYGPKG_HAL_SH_7708
        description "
            The SH3 7708 microprocessor. This is an embedded part that in
            addition to the SH3 processor core has built in peripherals
            such as memory controllers, serial ports and
            timers/counters."
        define_proc {
            puts $cdl_system_header "#define CYGBLD_HAL_CPU_MODULES_H "
        }
    }
 
    cdl_option CYGPKG_HAL_SH_7709A {
        display       "SH 7709A microprocessor"
        parent        CYGPKG_HAL_SH_CPU
        implements    CYGINT_HAL_SH_VARIANT
        implements    CYGINT_HAL_SH_CPG_T3
        implements    CYGINT_HAL_SH_DMA_CHANNELS
        implements    CYGINT_HAL_SH_DMA_CHANNELS
        implements    CYGINT_HAL_SH_DMA_CHANNELS
        implements    CYGINT_HAL_SH_DMA_CHANNELS
        default_value 1
        no_define
        define        -file=system.h CYGPKG_HAL_SH_7709A
        description "
            The SH3 7709A microprocessor. This is an embedded part that in
            addition to the SH3 processor core has built in peripherals
            such as memory controllers, DMA controllers, A/D and D/A
            converters, serial ports and timers/counters."
        define_proc {
            puts $cdl_system_header "#define CYGBLD_HAL_CPU_MODULES_H "
        }
    }
 
    cdl_option CYGPKG_HAL_SH_7709R {
        display       "SH 7709R microprocessor"
        parent        CYGPKG_HAL_SH_CPU
        implements    CYGINT_HAL_SH_VARIANT
        implements    CYGINT_HAL_SH_CPG_T3
        default_value 0
        no_define
        define        -file=system.h CYGPKG_HAL_SH_7709R
        description "
            The SH3 7709R microprocessor. This is an embedded part that in
            addition to the SH3 processor core has built in peripherals
            such as memory controllers, DMA controllers, A/D and D/A
            converters, serial ports and timers/counters."
        define_proc {
            puts $cdl_system_header "#define CYGBLD_HAL_CPU_MODULES_H "
        }
    }
 
    cdl_option CYGPKG_HAL_SH_7709S {
        display       "SH 7709S microprocessor"
        parent        CYGPKG_HAL_SH_CPU
        implements    CYGINT_HAL_SH_VARIANT
        implements    CYGINT_HAL_SH_CPG_T3
        implements    CYGINT_HAL_SH_DMA_CHANNELS
        implements    CYGINT_HAL_SH_DMA_CHANNELS
        implements    CYGINT_HAL_SH_DMA_CHANNELS
        implements    CYGINT_HAL_SH_DMA_CHANNELS
        default_value 0
        no_define
        define        -file=system.h CYGPKG_HAL_SH_7709S
        description "
            The SH3 7709S microprocessor. This is an embedded part that in
            addition to the SH3 processor core has built in peripherals
            such as memory controllers, DMA controllers, A/D and D/A
            converters, serial ports and timers/counters."
        define_proc {
            puts $cdl_system_header "#define CYGBLD_HAL_CPU_MODULES_H "
        }
    }
 
    cdl_option CYGPKG_HAL_SH_7729 {
        display       "SH 7729 microprocessor"
        parent        CYGPKG_HAL_SH_CPU
        implements    CYGINT_HAL_SH_VARIANT
        implements    CYGINT_HAL_SH_CPG_T3
        default_value 0
        no_define
        define        -file=system.h CYGPKG_HAL_SH_7729
        description "
            The SH3 7729 microprocessor. This is an embedded part that in
            addition to the SH3 processor core has built in peripherals
            such as memory controllers, serial ports, and timers/counters,
            and a DSP engine."
        define_proc {
            puts $cdl_system_header "#define CYGBLD_HAL_CPU_MODULES_H "
        }
    }
 
    cdl_component CYGHWR_HAL_SH_CLOCK_SETTINGS {
        display          "SH on-chip generic clock controls"
        description      "
            The various clocks used by the system are controlled by
            these options, some of which are derived from platform
            settings."
        flavor        none
        no_define
 
        cdl_interface CYGINT_HAL_SH_CPG_T1 {
            display     "Clock pulse generator type 1"
        }
 
        cdl_interface CYGINT_HAL_SH_CPG_T2 {
            display     "Clock pulse generator type 2"
        }
 
        cdl_interface CYGINT_HAL_SH_CPG_T3 {
            display     "Clock pulse generator type 3"
        }
 
 
        cdl_option CYGHWR_HAL_SH_TMU_PRESCALE_0 {
            display       "TMU counter 0 prescaling"
            description   "
                The peripheral clock is driving the counter used for
                the real-time clock, prescaled by this factor."
            flavor        data
            legal_values  { 4 16 64 256 }
            default_value 4
        }
 
        cdl_option CYGHWR_HAL_SH_RTC_PRESCALE {
            display       "eCos RTC prescaling"
            flavor        data
            calculated    CYGHWR_HAL_SH_TMU_PRESCALE_0
        }
 
        cdl_option CYGHWR_HAL_SH_CLOCK_CKIO {
            display    "CKIO clock"
            no_define
            flavor     data
            # CKIO is either XTAL or PLL2 output
            calculated { CYGINT_HAL_SH_CPG_T1 ? (
                             (CYGHWR_HAL_SH_OOC_CLOCK_MODE == 7)
                             ? (CYGHWR_HAL_SH_OOC_XTAL)
                             : CYGHWR_HAL_SH_PLL2_OUTPUT
                         )
                         : CYGINT_HAL_SH_CPG_T2 ? (
                             (CYGHWR_HAL_SH_OOC_CLOCK_MODE == 2)
                             ? (CYGHWR_HAL_SH_OOC_XTAL)
                             : CYGHWR_HAL_SH_PLL2_OUTPUT
                         )
                         : CYGINT_HAL_SH_CPG_T3 ? (
                             (CYGHWR_HAL_SH_OOC_CLOCK_MODE == 7)
                             ? (CYGHWR_HAL_SH_OOC_XTAL)
                             : CYGHWR_HAL_SH_PLL2_OUTPUT
                         )
                         : 0 }
        }
 
        cdl_option CYGHWR_HAL_SH_PLL1_OUTPUT {
            display    "The clock output from PLL1"
            no_define
            flavor     data
            calculated { CYGHWR_HAL_SH_CLOCK_CKIO * CYGHWR_HAL_SH_OOC_PLL_1 }
        }
 
        cdl_option CYGHWR_HAL_SH_PLL2_OUTPUT {
            display    "The clock output from PLL2"
            no_define
            flavor     data
            calculated { CYGINT_HAL_SH_CPG_T1 ? (
                             (CYGHWR_HAL_SH_OOC_XTAL * CYGHWR_HAL_SH_OOC_PLL_2)
                         )
                         : CYGINT_HAL_SH_CPG_T2 ? (
                             (CYGHWR_HAL_SH_OOC_CLOCK_MODE == 5)
                             ? (CYGHWR_HAL_SH_OOC_XTAL / 2)
                             : (CYGHWR_HAL_SH_OOC_CLOCK_MODE == 6)
                             ? (14745600)
                             : (CYGHWR_HAL_SH_OOC_CLOCK_MODE == 7)
                             ? (11075600)
                             : (CYGHWR_HAL_SH_OOC_XTAL * CYGHWR_HAL_SH_OOC_PLL_2)
                         )
                         : CYGINT_HAL_SH_CPG_T3 ? (
                             (CYGHWR_HAL_SH_OOC_XTAL * CYGHWR_HAL_SH_OOC_PLL_2)
                         )
                         : 0 }
        }
 
 
        cdl_option CYGHWR_HAL_SH_DIVIDER1_INPUT {
            display    "The clock input to divider 1"
            no_define
            flavor     data
            # DIV1 input is either PLL2 output or PLL1 output
            calculated { (CYGHWR_HAL_SH_OOC_PLL_1 == 0)
                           ? CYGHWR_HAL_SH_PLL2_OUTPUT
                           : CYGHWR_HAL_SH_PLL1_OUTPUT }
        }
 
        cdl_option CYGHWR_HAL_SH_DIVIDER2_INPUT {
            display    "The clock input to divider 2"
            no_define
            flavor     data
            # DIV2 input is either PLL2 output or PLL1 output
            calculated { CYGINT_HAL_SH_CPG_T1 ? (
                             (CYGHWR_HAL_SH_OOC_CLOCK_MODE == 3 || CYGHWR_HAL_SH_OOC_CLOCK_MODE == 4)
                             ? CYGHWR_HAL_SH_PLL2_OUTPUT
                             : CYGHWR_HAL_SH_PLL1_OUTPUT
                         )
                         : CYGINT_HAL_SH_CPG_T2 ? (
                             (CYGHWR_HAL_SH_OOC_CLOCK_MODE <= 2)
                             ? CYGHWR_HAL_SH_PLL1_OUTPUT
                             : CYGHWR_HAL_SH_PLL2_OUTPUT
                         )
                         : CYGINT_HAL_SH_CPG_T3 ? (
                             (CYGHWR_HAL_SH_OOC_CLOCK_MODE == 3 || CYGHWR_HAL_SH_OOC_CLOCK_MODE == 4)
                             ? CYGHWR_HAL_SH_PLL2_OUTPUT
                             : CYGHWR_HAL_SH_PLL1_OUTPUT
                         )
                         : 0 }
        }
 
        cdl_option CYGHWR_HAL_SH_PROCESSOR_SPEED {
            display          "Processor clock speed (MHz)"
            flavor           data
            calculated       { CYGHWR_HAL_SH_DIVIDER1_INPUT / CYGHWR_HAL_SH_OOC_DIVIDER_1 }
            description      "
                The core (CPU, cache and MMU) speed is computed from
                the input clock speed and the divider 1 setting."
        }
 
        cdl_option CYGHWR_HAL_SH_BOARD_SPEED {
            display          "Platform bus clock speed (MHz)"
            flavor           data
            calculated       { CYGHWR_HAL_SH_CLOCK_CKIO }
            description      "
                The platform bus speed is CKIO."
        }
 
        cdl_option CYGHWR_HAL_SH_ONCHIP_PERIPHERAL_SPEED {
            display          "Processor on-chip peripheral clock speed (MHz)"
            flavor           data
            calculated       { CYGHWR_HAL_SH_DIVIDER2_INPUT / CYGHWR_HAL_SH_OOC_DIVIDER_2 }
            description      "
                The peripheral speed is computed from the input clock
                speed and the divider 2 settings."
        }
    }
 
    cdl_option CYGNUM_HAL_SH_SH3_SCI_BAUD_RATE {
        display          "SCI serial port default baud rate"
        flavor data
        legal_values     { 4800 9600 14400 19200 38400 57600 115200 }
        default_value    { CYGNUM_HAL_SH_SH3_SCI_BAUD_RATE_DEFAULT ? \
                           CYGNUM_HAL_SH_SH3_SCI_BAUD_RATE_DEFAULT : 38400 }
        description      "
           This controls the default baud rate used for communicating
           with GDB / displaying diagnostic output."
    }
 
    cdl_option CYGNUM_HAL_SH_SH3_SCIF_BAUD_RATE {
        display          "SCIF serial ports default baud rate"
        flavor data
        legal_values     { 4800 9600 14400 19200 38400 57600 115200 }
        default_value    { CYGNUM_HAL_SH_SH3_SCIF_BAUD_RATE_DEFAULT ? \
                           CYGNUM_HAL_SH_SH3_SCIF_BAUD_RATE_DEFAULT : 38400 }
        description      "
           This controls the default baud rate used for communicating
           with GDB / displaying diagnostic output."
    }
 
    cdl_component CYGPKG_HAL_SH_INTERRUPT {
        display          "Interrupt controls"
        flavor     none
        no_define
        description      "
            Initial interrupt settings can be specified using these option."
 
        cdl_option CYGHWR_HAL_SH_IRQ_HANDLE_SPURIOUS_INTERRUPTS {
            display          "Handle spurious interrupts"
            default_value    0
            description      "
               The SH3 may generate spurious interrupts with INTEVT = 0
               when changing the BL bit of the status register. Enabling
               this option will cause such interrupts to be identified
               very early in the interrupt handler and be ignored.  Given
               that the SH HAL uses the I-mask to control interrupts,
               these spurious interrupts should not occur, and so there
               should be no reason to include the special handling code."
        }
 
        cdl_option CYGHWR_HAL_SH_IRQ_USE_IRQLVL {
            display          "Use IRQ0-3 pins as IRL input"
            default_value    0
            description      "
                It is possible for the IRQ0-3 pins to be used as IRL
                inputs by enabling this option."
        }
 
        cdl_option CYGHWR_HAL_SH_IRQ_ENABLE_IRLS_INTERRUPTS {
            display          "Enable IRLS interrupt pins"
            default_value    0
            active_if        CYGHWR_HAL_SH_IRQ_USE_IRQLVL
            description      "
                IRLS interrupt pins must be specifically
                activated. When they are, they will cause the same
                type of interrupt as those caused by the IRL pins. If
                IRL and IRLS pins signal an interrupt at the same
                time, the highest level interrupt will be generated.
                Only available on some cores, and probably share pins
                with other interrupt sources (PINT) which cannot be
                used in this configuration."
        }
    }
 
    # Cache settings
    cdl_option CYGHWR_HAL_SH_CACHE_MODE_P0 {
        display       "Select cache mode set for P0/U0/P3 at startup"
        parent        CYGPKG_HAL_SH_CACHE
        default_value { "WRITE_BACK" }
        legal_values  { "WRITE_BACK" "WRITE_THROUGH" }
        flavor        data
        description "
            Controls what cache mode the cache should be put in at
            startup for areas P0, U0 and P3. Write-back mode improves
            performance by letting dirty data to be kept in the
            cache for a period of time, allowing mutiple writes to
            the same cache line to be written back to memory in
            one memory transaction. In Write-through mode, each
            individual write will cause a memory transaction."
    }
 
    cdl_option CYGHWR_HAL_SH_CACHE_MODE_P1 {
        display       "Select cache mode set for P1 at startup"
        parent        CYGPKG_HAL_SH_CACHE
        default_value { "WRITE_BACK" }
        legal_values  { "WRITE_BACK" "WRITE_THROUGH" }
        flavor        data
        description "
            Controls what cache mode the cache should be put in at
            startup for area P1. Write-back mode improves
            performance by letting dirty data to be kept in the
            cache for a period of time, allowing mutiple writes to
            the same cache line to be written back to memory in
            one memory transaction. In Write-through mode, each
            individual write will cause a memory transaction."
    }
}

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[/] [openrisc/] [trunk/] [rtos/] [ecos-3.0/] [packages/] [hal/] [sh/] [sh3/] [current/] [cdl/] [hal_sh_sh3.cdl] - Blame information for rev 838

Line No.	Rev	Author	Line
1	786	skrzyp	`# ====================================================================`
2			`#`
3			`# hal_sh_sh3.cdl`
4			`#`
5			`# SH3 variant HAL package configuration data`
6			`#`
7			`# ====================================================================`
8			`## ####ECOSGPLCOPYRIGHTBEGIN####`
9			`## -------------------------------------------`
10			`## This file is part of eCos, the Embedded Configurable Operating System.`
11			`## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.`
12			`##`
13			`## eCos is free software; you can redistribute it and/or modify it under`
14			`## the terms of the GNU General Public License as published by the Free`
15			`## Software Foundation; either version 2 or (at your option) any later`
16			`## version.`
17			`##`
18			`## eCos is distributed in the hope that it will be useful, but WITHOUT`
19			`## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or`
20			`## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License`
21			`## for more details.`
22			`##`
23			`## You should have received a copy of the GNU General Public License`
24			`## along with eCos; if not, write to the Free Software Foundation, Inc.,`
25			`## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.`
26			`##`
27			`## As a special exception, if other files instantiate templates or use`
28			`## macros or inline functions from this file, or you compile this file`
29			`## and link it with other works to produce a work based on this file,`
30			`## this file does not by itself cause the resulting work to be covered by`
31			`## the GNU General Public License. However the source code for this file`
32			`## must still be made available in accordance with section (3) of the GNU`
33			`## General Public License v2.`
34			`##`
35			`## This exception does not invalidate any other reasons why a work based`
36			`## on this file might be covered by the GNU General Public License.`
37			`## -------------------------------------------`
38			`## ####ECOSGPLCOPYRIGHTEND####`
39			`# ====================================================================`
40			`######DESCRIPTIONBEGIN####`
41			`#`
42			`# Author(s): jskov`
43			`# Original data: jskov`
44			`# Contributors:`
45			`# Date: 2000-10-30`
46			`#`
47			`#####DESCRIPTIONEND####`
48			`#`
49			`# ====================================================================`
50
51			`cdl_package CYGPKG_HAL_SH_SH3 {`
52			`display "SH3 variant"`
53			`parent CYGPKG_HAL_SH`
54			`hardware`
55			`include_dir cyg/hal`
56			`define_header hal_sh_sh3.h`
57			`description "`
58			`The SH3 (SuperH 3) variant HAL package provides generic`
59			`support for SH3 variant CPUs."`
60
61			`define_proc {`
62			`puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H "`
63			`puts $::cdl_header "#define CYGBLD_HAL_VAR_EXCEPTION_MODEL_H "`
64			`puts $::cdl_header "#define CYGBLD_HAL_VAR_EXCEPTION_MODEL_INC "`
65			`puts $::cdl_header "#define CYGBLD_HAL_VAR_INTR_MODEL_H "`
66			`}`
67
68			`compile sh3_sci.c sh3_scif.c var_misc.c variant.S`
69
70			`# The "-o file" is a workaround for CR100958 - without it the`
71			`# output file would end up in the source directory under CygWin.`
72			`# n.b. grep does not behave itself under win32`
73			`make -priority 1 {`
74			`/include/cyg/hal/sh3_offsets.inc : /src/var_mk_defs.c`
75			`$(CC) $(ACTUAL_CFLAGS) $(INCLUDE_PATH) -Wp,-MD,sh3_offsets.tmp -o var_mk_defs.tmp -S $<`
76			`fgrep .equ var_mk_defs.tmp \| sed s/#// > $@`
77			`@echo $@ ": \\" > $(notdir $@).deps`
78			`@tail -n +2 sh3_offsets.tmp >> $(notdir $@).deps`
79			`@echo >> $(notdir $@).deps`
80			`@rm sh3_offsets.tmp var_mk_defs.tmp`
81			`}`
82
83			`# CPU variant supported`
84			`cdl_option CYGPKG_HAL_SH_7707A {`
85			`display "SH 7707A microprocessor"`
86			`parent CYGPKG_HAL_SH_CPU`
87			`implements CYGINT_HAL_SH_VARIANT`
88			`implements CYGINT_HAL_SH_CPG_T2`
89			`default_value 0`
90			`no_define`
91			`define -file=system.h CYGPKG_HAL_SH_7707A`
92			`description "`
93			`The SH3 7707A microprocessor. This is an embedded part that in`
94			`addition to the SH3 processor core has built in peripherals`
95			`such as memory controllers, serial ports, LCD controller and`
96			`timers/counters."`
97			`define_proc {`
98			`puts $cdl_system_header "#define CYGBLD_HAL_CPU_MODULES_H "`
99			`}`
100			`}`
101
102			`cdl_option CYGPKG_HAL_SH_7708 {`
103			`display "SH 7708 microprocessor"`
104			`parent CYGPKG_HAL_SH_CPU`
105			`implements CYGINT_HAL_SH_VARIANT`
106			`implements CYGINT_HAL_SH_CPG_T1`
107			`default_value 0`
108			`no_define`
109			`define -file=system.h CYGPKG_HAL_SH_7708`
110			`description "`
111			`The SH3 7708 microprocessor. This is an embedded part that in`
112			`addition to the SH3 processor core has built in peripherals`
113			`such as memory controllers, serial ports and`
114			`timers/counters."`
115			`define_proc {`
116			`puts $cdl_system_header "#define CYGBLD_HAL_CPU_MODULES_H "`
117			`}`
118			`}`
119
120			`cdl_option CYGPKG_HAL_SH_7709A {`
121			`display "SH 7709A microprocessor"`
122			`parent CYGPKG_HAL_SH_CPU`
123			`implements CYGINT_HAL_SH_VARIANT`
124			`implements CYGINT_HAL_SH_CPG_T3`
125			`implements CYGINT_HAL_SH_DMA_CHANNELS`
126			`implements CYGINT_HAL_SH_DMA_CHANNELS`
127			`implements CYGINT_HAL_SH_DMA_CHANNELS`
128			`implements CYGINT_HAL_SH_DMA_CHANNELS`
129			`default_value 1`
130			`no_define`
131			`define -file=system.h CYGPKG_HAL_SH_7709A`
132			`description "`
133			`The SH3 7709A microprocessor. This is an embedded part that in`
134			`addition to the SH3 processor core has built in peripherals`
135			`such as memory controllers, DMA controllers, A/D and D/A`
136			`converters, serial ports and timers/counters."`
137			`define_proc {`
138			`puts $cdl_system_header "#define CYGBLD_HAL_CPU_MODULES_H "`
139			`}`
140			`}`
141
142			`cdl_option CYGPKG_HAL_SH_7709R {`
143			`display "SH 7709R microprocessor"`
144			`parent CYGPKG_HAL_SH_CPU`
145			`implements CYGINT_HAL_SH_VARIANT`
146			`implements CYGINT_HAL_SH_CPG_T3`
147			`default_value 0`
148			`no_define`
149			`define -file=system.h CYGPKG_HAL_SH_7709R`
150			`description "`
151			`The SH3 7709R microprocessor. This is an embedded part that in`
152			`addition to the SH3 processor core has built in peripherals`
153			`such as memory controllers, DMA controllers, A/D and D/A`
154			`converters, serial ports and timers/counters."`
155			`define_proc {`
156			`puts $cdl_system_header "#define CYGBLD_HAL_CPU_MODULES_H "`
157			`}`
158			`}`
159
160			`cdl_option CYGPKG_HAL_SH_7709S {`
161			`display "SH 7709S microprocessor"`
162			`parent CYGPKG_HAL_SH_CPU`
163			`implements CYGINT_HAL_SH_VARIANT`
164			`implements CYGINT_HAL_SH_CPG_T3`
165			`implements CYGINT_HAL_SH_DMA_CHANNELS`
166			`implements CYGINT_HAL_SH_DMA_CHANNELS`
167			`implements CYGINT_HAL_SH_DMA_CHANNELS`
168			`implements CYGINT_HAL_SH_DMA_CHANNELS`
169			`default_value 0`
170			`no_define`
171			`define -file=system.h CYGPKG_HAL_SH_7709S`
172			`description "`
173			`The SH3 7709S microprocessor. This is an embedded part that in`
174			`addition to the SH3 processor core has built in peripherals`
175			`such as memory controllers, DMA controllers, A/D and D/A`
176			`converters, serial ports and timers/counters."`
177			`define_proc {`
178			`puts $cdl_system_header "#define CYGBLD_HAL_CPU_MODULES_H "`
179			`}`
180			`}`
181
182			`cdl_option CYGPKG_HAL_SH_7729 {`
183			`display "SH 7729 microprocessor"`
184			`parent CYGPKG_HAL_SH_CPU`
185			`implements CYGINT_HAL_SH_VARIANT`
186			`implements CYGINT_HAL_SH_CPG_T3`
187			`default_value 0`
188			`no_define`
189			`define -file=system.h CYGPKG_HAL_SH_7729`
190			`description "`
191			`The SH3 7729 microprocessor. This is an embedded part that in`
192			`addition to the SH3 processor core has built in peripherals`
193			`such as memory controllers, serial ports, and timers/counters,`
194			`and a DSP engine."`
195			`define_proc {`
196			`puts $cdl_system_header "#define CYGBLD_HAL_CPU_MODULES_H "`
197			`}`
198			`}`
199
200			`cdl_component CYGHWR_HAL_SH_CLOCK_SETTINGS {`
201			`display "SH on-chip generic clock controls"`
202			`description "`
203			`The various clocks used by the system are controlled by`
204			`these options, some of which are derived from platform`
205			`settings."`
206			`flavor none`
207			`no_define`
208
209			`cdl_interface CYGINT_HAL_SH_CPG_T1 {`
210			`display "Clock pulse generator type 1"`
211			`}`
212
213			`cdl_interface CYGINT_HAL_SH_CPG_T2 {`
214			`display "Clock pulse generator type 2"`
215			`}`
216
217			`cdl_interface CYGINT_HAL_SH_CPG_T3 {`
218			`display "Clock pulse generator type 3"`
219			`}`
220
221
222			`cdl_option CYGHWR_HAL_SH_TMU_PRESCALE_0 {`
223			`display "TMU counter 0 prescaling"`
224			`description "`
225			`The peripheral clock is driving the counter used for`
226			`the real-time clock, prescaled by this factor."`
227			`flavor data`
228			`legal_values { 4 16 64 256 }`
229			`default_value 4`
230			`}`
231
232			`cdl_option CYGHWR_HAL_SH_RTC_PRESCALE {`
233			`display "eCos RTC prescaling"`
234			`flavor data`
235			`calculated CYGHWR_HAL_SH_TMU_PRESCALE_0`
236			`}`
237
238			`cdl_option CYGHWR_HAL_SH_CLOCK_CKIO {`
239			`display "CKIO clock"`
240			`no_define`
241			`flavor data`
242			`# CKIO is either XTAL or PLL2 output`
243			`calculated { CYGINT_HAL_SH_CPG_T1 ? (`
244			`(CYGHWR_HAL_SH_OOC_CLOCK_MODE == 7)`
245			`? (CYGHWR_HAL_SH_OOC_XTAL)`
246			`: CYGHWR_HAL_SH_PLL2_OUTPUT`
247			`)`
248			`: CYGINT_HAL_SH_CPG_T2 ? (`
249			`(CYGHWR_HAL_SH_OOC_CLOCK_MODE == 2)`
250			`? (CYGHWR_HAL_SH_OOC_XTAL)`
251			`: CYGHWR_HAL_SH_PLL2_OUTPUT`
252			`)`
253			`: CYGINT_HAL_SH_CPG_T3 ? (`
254			`(CYGHWR_HAL_SH_OOC_CLOCK_MODE == 7)`
255			`? (CYGHWR_HAL_SH_OOC_XTAL)`
256			`: CYGHWR_HAL_SH_PLL2_OUTPUT`
257			`)`
258			`: 0 }`
259			`}`
260
261			`cdl_option CYGHWR_HAL_SH_PLL1_OUTPUT {`
262			`display "The clock output from PLL1"`
263			`no_define`
264			`flavor data`
265			`calculated { CYGHWR_HAL_SH_CLOCK_CKIO * CYGHWR_HAL_SH_OOC_PLL_1 }`
266			`}`
267
268			`cdl_option CYGHWR_HAL_SH_PLL2_OUTPUT {`
269			`display "The clock output from PLL2"`
270			`no_define`
271			`flavor data`
272			`calculated { CYGINT_HAL_SH_CPG_T1 ? (`
273			`(CYGHWR_HAL_SH_OOC_XTAL * CYGHWR_HAL_SH_OOC_PLL_2)`
274			`)`
275			`: CYGINT_HAL_SH_CPG_T2 ? (`
276			`(CYGHWR_HAL_SH_OOC_CLOCK_MODE == 5)`
277			`? (CYGHWR_HAL_SH_OOC_XTAL / 2)`
278			`: (CYGHWR_HAL_SH_OOC_CLOCK_MODE == 6)`
279			`? (14745600)`
280			`: (CYGHWR_HAL_SH_OOC_CLOCK_MODE == 7)`
281			`? (11075600)`
282			`: (CYGHWR_HAL_SH_OOC_XTAL * CYGHWR_HAL_SH_OOC_PLL_2)`
283			`)`
284			`: CYGINT_HAL_SH_CPG_T3 ? (`
285			`(CYGHWR_HAL_SH_OOC_XTAL * CYGHWR_HAL_SH_OOC_PLL_2)`
286			`)`
287			`: 0 }`
288			`}`
289
290
291			`cdl_option CYGHWR_HAL_SH_DIVIDER1_INPUT {`
292			`display "The clock input to divider 1"`
293			`no_define`
294			`flavor data`
295			`# DIV1 input is either PLL2 output or PLL1 output`
296			`calculated { (CYGHWR_HAL_SH_OOC_PLL_1 == 0)`
297			`? CYGHWR_HAL_SH_PLL2_OUTPUT`
298			`: CYGHWR_HAL_SH_PLL1_OUTPUT }`
299			`}`
300
301			`cdl_option CYGHWR_HAL_SH_DIVIDER2_INPUT {`
302			`display "The clock input to divider 2"`
303			`no_define`
304			`flavor data`
305			`# DIV2 input is either PLL2 output or PLL1 output`
306			`calculated { CYGINT_HAL_SH_CPG_T1 ? (`
307			`(CYGHWR_HAL_SH_OOC_CLOCK_MODE == 3 \|\| CYGHWR_HAL_SH_OOC_CLOCK_MODE == 4)`
308			`? CYGHWR_HAL_SH_PLL2_OUTPUT`
309			`: CYGHWR_HAL_SH_PLL1_OUTPUT`
310			`)`
311			`: CYGINT_HAL_SH_CPG_T2 ? (`
312			`(CYGHWR_HAL_SH_OOC_CLOCK_MODE <= 2)`
313			`? CYGHWR_HAL_SH_PLL1_OUTPUT`
314			`: CYGHWR_HAL_SH_PLL2_OUTPUT`
315			`)`
316			`: CYGINT_HAL_SH_CPG_T3 ? (`
317			`(CYGHWR_HAL_SH_OOC_CLOCK_MODE == 3 \|\| CYGHWR_HAL_SH_OOC_CLOCK_MODE == 4)`
318			`? CYGHWR_HAL_SH_PLL2_OUTPUT`
319			`: CYGHWR_HAL_SH_PLL1_OUTPUT`
320			`)`
321			`: 0 }`
322			`}`
323
324			`cdl_option CYGHWR_HAL_SH_PROCESSOR_SPEED {`
325			`display "Processor clock speed (MHz)"`
326			`flavor data`
327			`calculated { CYGHWR_HAL_SH_DIVIDER1_INPUT / CYGHWR_HAL_SH_OOC_DIVIDER_1 }`
328			`description "`
329			`The core (CPU, cache and MMU) speed is computed from`
330			`the input clock speed and the divider 1 setting."`
331			`}`
332
333			`cdl_option CYGHWR_HAL_SH_BOARD_SPEED {`
334			`display "Platform bus clock speed (MHz)"`
335			`flavor data`
336			`calculated { CYGHWR_HAL_SH_CLOCK_CKIO }`
337			`description "`
338			`The platform bus speed is CKIO."`
339			`}`
340
341			`cdl_option CYGHWR_HAL_SH_ONCHIP_PERIPHERAL_SPEED {`
342			`display "Processor on-chip peripheral clock speed (MHz)"`
343			`flavor data`
344			`calculated { CYGHWR_HAL_SH_DIVIDER2_INPUT / CYGHWR_HAL_SH_OOC_DIVIDER_2 }`
345			`description "`
346			`The peripheral speed is computed from the input clock`
347			`speed and the divider 2 settings."`
348			`}`
349			`}`
350
351			`cdl_option CYGNUM_HAL_SH_SH3_SCI_BAUD_RATE {`
352			`display "SCI serial port default baud rate"`
353			`flavor data`
354			`legal_values { 4800 9600 14400 19200 38400 57600 115200 }`
355			`default_value { CYGNUM_HAL_SH_SH3_SCI_BAUD_RATE_DEFAULT ? \`
356			`CYGNUM_HAL_SH_SH3_SCI_BAUD_RATE_DEFAULT : 38400 }`
357			`description "`
358			`This controls the default baud rate used for communicating`
359			`with GDB / displaying diagnostic output."`
360			`}`
361
362			`cdl_option CYGNUM_HAL_SH_SH3_SCIF_BAUD_RATE {`
363			`display "SCIF serial ports default baud rate"`
364			`flavor data`
365			`legal_values { 4800 9600 14400 19200 38400 57600 115200 }`
366			`default_value { CYGNUM_HAL_SH_SH3_SCIF_BAUD_RATE_DEFAULT ? \`
367			`CYGNUM_HAL_SH_SH3_SCIF_BAUD_RATE_DEFAULT : 38400 }`
368			`description "`
369			`This controls the default baud rate used for communicating`
370			`with GDB / displaying diagnostic output."`
371			`}`
372
373			`cdl_component CYGPKG_HAL_SH_INTERRUPT {`
374			`display "Interrupt controls"`
375			`flavor none`
376			`no_define`
377			`description "`
378			`Initial interrupt settings can be specified using these option."`
379
380			`cdl_option CYGHWR_HAL_SH_IRQ_HANDLE_SPURIOUS_INTERRUPTS {`
381			`display "Handle spurious interrupts"`
382			`default_value 0`
383			`description "`
384			`The SH3 may generate spurious interrupts with INTEVT = 0`
385			`when changing the BL bit of the status register. Enabling`
386			`this option will cause such interrupts to be identified`
387			`very early in the interrupt handler and be ignored. Given`
388			`that the SH HAL uses the I-mask to control interrupts,`
389			`these spurious interrupts should not occur, and so there`
390			`should be no reason to include the special handling code."`
391			`}`
392
393			`cdl_option CYGHWR_HAL_SH_IRQ_USE_IRQLVL {`
394			`display "Use IRQ0-3 pins as IRL input"`
395			`default_value 0`
396			`description "`
397			`It is possible for the IRQ0-3 pins to be used as IRL`
398			`inputs by enabling this option."`
399			`}`
400
401			`cdl_option CYGHWR_HAL_SH_IRQ_ENABLE_IRLS_INTERRUPTS {`
402			`display "Enable IRLS interrupt pins"`
403			`default_value 0`
404			`active_if CYGHWR_HAL_SH_IRQ_USE_IRQLVL`
405			`description "`
406			`IRLS interrupt pins must be specifically`
407			`activated. When they are, they will cause the same`
408			`type of interrupt as those caused by the IRL pins. If`
409			`IRL and IRLS pins signal an interrupt at the same`
410			`time, the highest level interrupt will be generated.`
411			`Only available on some cores, and probably share pins`
412			`with other interrupt sources (PINT) which cannot be`
413			`used in this configuration."`
414			`}`
415			`}`
416
417			`# Cache settings`
418			`cdl_option CYGHWR_HAL_SH_CACHE_MODE_P0 {`
419			`display "Select cache mode set for P0/U0/P3 at startup"`
420			`parent CYGPKG_HAL_SH_CACHE`
421			`default_value { "WRITE_BACK" }`
422			`legal_values { "WRITE_BACK" "WRITE_THROUGH" }`
423			`flavor data`
424			`description "`
425			`Controls what cache mode the cache should be put in at`
426			`startup for areas P0, U0 and P3. Write-back mode improves`
427			`performance by letting dirty data to be kept in the`
428			`cache for a period of time, allowing mutiple writes to`
429			`the same cache line to be written back to memory in`
430			`one memory transaction. In Write-through mode, each`
431			`individual write will cause a memory transaction."`
432			`}`
433
434			`cdl_option CYGHWR_HAL_SH_CACHE_MODE_P1 {`
435			`display "Select cache mode set for P1 at startup"`
436			`parent CYGPKG_HAL_SH_CACHE`
437			`default_value { "WRITE_BACK" }`
438			`legal_values { "WRITE_BACK" "WRITE_THROUGH" }`
439			`flavor data`
440			`description "`
441			`Controls what cache mode the cache should be put in at`
442			`startup for area P1. Write-back mode improves`
443			`performance by letting dirty data to be kept in the`
444			`cache for a period of time, allowing mutiple writes to`
445			`the same cache line to be written back to memory in`
446			`one memory transaction. In Write-through mode, each`
447			`individual write will cause a memory transaction."`
448			`}`
449			`}`