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# ====================================================================
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#
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# hal_sh_sh3.cdl
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#
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# SH3 variant HAL package configuration data
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#
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# ====================================================================
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## ####ECOSGPLCOPYRIGHTBEGIN####
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## -------------------------------------------
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## This file is part of eCos, the Embedded Configurable Operating System.
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## Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
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##
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## eCos is free software; you can redistribute it and/or modify it under
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## the terms of the GNU General Public License as published by the Free
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## Software Foundation; either version 2 or (at your option) any later
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## version.
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##
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## eCos is distributed in the hope that it will be useful, but WITHOUT
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## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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## for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with eCos; if not, write to the Free Software Foundation, Inc.,
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## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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##
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## As a special exception, if other files instantiate templates or use
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## macros or inline functions from this file, or you compile this file
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## and link it with other works to produce a work based on this file,
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## this file does not by itself cause the resulting work to be covered by
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## the GNU General Public License. However the source code for this file
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## must still be made available in accordance with section (3) of the GNU
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## General Public License v2.
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##
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## This exception does not invalidate any other reasons why a work based
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## on this file might be covered by the GNU General Public License.
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## -------------------------------------------
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## ####ECOSGPLCOPYRIGHTEND####
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# ====================================================================
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######DESCRIPTIONBEGIN####
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#
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# Author(s): jskov
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# Original data: jskov
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# Contributors:
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# Date: 2000-10-30
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#
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#####DESCRIPTIONEND####
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#
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# ====================================================================
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cdl_package CYGPKG_HAL_SH_SH3 {
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display "SH3 variant"
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parent CYGPKG_HAL_SH
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hardware
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include_dir cyg/hal
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define_header hal_sh_sh3.h
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description "
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The SH3 (SuperH 3) variant HAL package provides generic
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support for SH3 variant CPUs."
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define_proc {
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puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H "
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puts $::cdl_header "#define CYGBLD_HAL_VAR_EXCEPTION_MODEL_H "
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puts $::cdl_header "#define CYGBLD_HAL_VAR_EXCEPTION_MODEL_INC "
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puts $::cdl_header "#define CYGBLD_HAL_VAR_INTR_MODEL_H "
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}
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compile sh3_sci.c sh3_scif.c var_misc.c variant.S
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# The "-o file" is a workaround for CR100958 - without it the
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# output file would end up in the source directory under CygWin.
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# n.b. grep does not behave itself under win32
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make -priority 1 {
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/include/cyg/hal/sh3_offsets.inc : /src/var_mk_defs.c
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$(CC) $(ACTUAL_CFLAGS) $(INCLUDE_PATH) -Wp,-MD,sh3_offsets.tmp -o var_mk_defs.tmp -S $<
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fgrep .equ var_mk_defs.tmp | sed s/#// > $@
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@echo $@ ": \\" > $(notdir $@).deps
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@tail -n +2 sh3_offsets.tmp >> $(notdir $@).deps
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@echo >> $(notdir $@).deps
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@rm sh3_offsets.tmp var_mk_defs.tmp
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}
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# CPU variant supported
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cdl_option CYGPKG_HAL_SH_7707A {
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display "SH 7707A microprocessor"
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parent CYGPKG_HAL_SH_CPU
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implements CYGINT_HAL_SH_VARIANT
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implements CYGINT_HAL_SH_CPG_T2
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default_value 0
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no_define
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define -file=system.h CYGPKG_HAL_SH_7707A
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description "
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The SH3 7707A microprocessor. This is an embedded part that in
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addition to the SH3 processor core has built in peripherals
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such as memory controllers, serial ports, LCD controller and
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timers/counters."
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define_proc {
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puts $cdl_system_header "#define CYGBLD_HAL_CPU_MODULES_H "
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}
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}
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cdl_option CYGPKG_HAL_SH_7708 {
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display "SH 7708 microprocessor"
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parent CYGPKG_HAL_SH_CPU
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implements CYGINT_HAL_SH_VARIANT
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implements CYGINT_HAL_SH_CPG_T1
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default_value 0
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no_define
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define -file=system.h CYGPKG_HAL_SH_7708
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description "
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The SH3 7708 microprocessor. This is an embedded part that in
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addition to the SH3 processor core has built in peripherals
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such as memory controllers, serial ports and
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timers/counters."
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define_proc {
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puts $cdl_system_header "#define CYGBLD_HAL_CPU_MODULES_H "
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}
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}
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cdl_option CYGPKG_HAL_SH_7709A {
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display "SH 7709A microprocessor"
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parent CYGPKG_HAL_SH_CPU
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implements CYGINT_HAL_SH_VARIANT
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implements CYGINT_HAL_SH_CPG_T3
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implements CYGINT_HAL_SH_DMA_CHANNELS
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implements CYGINT_HAL_SH_DMA_CHANNELS
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implements CYGINT_HAL_SH_DMA_CHANNELS
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implements CYGINT_HAL_SH_DMA_CHANNELS
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default_value 1
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no_define
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define -file=system.h CYGPKG_HAL_SH_7709A
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description "
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The SH3 7709A microprocessor. This is an embedded part that in
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addition to the SH3 processor core has built in peripherals
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such as memory controllers, DMA controllers, A/D and D/A
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converters, serial ports and timers/counters."
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define_proc {
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puts $cdl_system_header "#define CYGBLD_HAL_CPU_MODULES_H "
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}
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}
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cdl_option CYGPKG_HAL_SH_7709R {
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display "SH 7709R microprocessor"
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parent CYGPKG_HAL_SH_CPU
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implements CYGINT_HAL_SH_VARIANT
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implements CYGINT_HAL_SH_CPG_T3
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default_value 0
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no_define
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define -file=system.h CYGPKG_HAL_SH_7709R
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description "
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The SH3 7709R microprocessor. This is an embedded part that in
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addition to the SH3 processor core has built in peripherals
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such as memory controllers, DMA controllers, A/D and D/A
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converters, serial ports and timers/counters."
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define_proc {
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puts $cdl_system_header "#define CYGBLD_HAL_CPU_MODULES_H "
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}
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}
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cdl_option CYGPKG_HAL_SH_7709S {
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display "SH 7709S microprocessor"
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parent CYGPKG_HAL_SH_CPU
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implements CYGINT_HAL_SH_VARIANT
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implements CYGINT_HAL_SH_CPG_T3
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implements CYGINT_HAL_SH_DMA_CHANNELS
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implements CYGINT_HAL_SH_DMA_CHANNELS
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implements CYGINT_HAL_SH_DMA_CHANNELS
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implements CYGINT_HAL_SH_DMA_CHANNELS
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default_value 0
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no_define
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define -file=system.h CYGPKG_HAL_SH_7709S
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description "
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The SH3 7709S microprocessor. This is an embedded part that in
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addition to the SH3 processor core has built in peripherals
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such as memory controllers, DMA controllers, A/D and D/A
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converters, serial ports and timers/counters."
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define_proc {
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puts $cdl_system_header "#define CYGBLD_HAL_CPU_MODULES_H "
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}
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}
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cdl_option CYGPKG_HAL_SH_7729 {
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display "SH 7729 microprocessor"
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parent CYGPKG_HAL_SH_CPU
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implements CYGINT_HAL_SH_VARIANT
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implements CYGINT_HAL_SH_CPG_T3
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default_value 0
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no_define
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define -file=system.h CYGPKG_HAL_SH_7729
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description "
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The SH3 7729 microprocessor. This is an embedded part that in
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addition to the SH3 processor core has built in peripherals
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such as memory controllers, serial ports, and timers/counters,
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and a DSP engine."
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define_proc {
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puts $cdl_system_header "#define CYGBLD_HAL_CPU_MODULES_H "
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}
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}
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cdl_component CYGHWR_HAL_SH_CLOCK_SETTINGS {
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display "SH on-chip generic clock controls"
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description "
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The various clocks used by the system are controlled by
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these options, some of which are derived from platform
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settings."
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flavor none
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no_define
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cdl_interface CYGINT_HAL_SH_CPG_T1 {
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display "Clock pulse generator type 1"
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}
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cdl_interface CYGINT_HAL_SH_CPG_T2 {
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display "Clock pulse generator type 2"
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}
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cdl_interface CYGINT_HAL_SH_CPG_T3 {
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display "Clock pulse generator type 3"
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}
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cdl_option CYGHWR_HAL_SH_TMU_PRESCALE_0 {
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display "TMU counter 0 prescaling"
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description "
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The peripheral clock is driving the counter used for
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the real-time clock, prescaled by this factor."
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flavor data
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legal_values { 4 16 64 256 }
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default_value 4
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}
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cdl_option CYGHWR_HAL_SH_RTC_PRESCALE {
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display "eCos RTC prescaling"
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flavor data
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calculated CYGHWR_HAL_SH_TMU_PRESCALE_0
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}
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cdl_option CYGHWR_HAL_SH_CLOCK_CKIO {
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display "CKIO clock"
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no_define
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flavor data
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# CKIO is either XTAL or PLL2 output
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calculated { CYGINT_HAL_SH_CPG_T1 ? (
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(CYGHWR_HAL_SH_OOC_CLOCK_MODE == 7)
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? (CYGHWR_HAL_SH_OOC_XTAL)
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: CYGHWR_HAL_SH_PLL2_OUTPUT
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)
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: CYGINT_HAL_SH_CPG_T2 ? (
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(CYGHWR_HAL_SH_OOC_CLOCK_MODE == 2)
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? (CYGHWR_HAL_SH_OOC_XTAL)
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: CYGHWR_HAL_SH_PLL2_OUTPUT
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)
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: CYGINT_HAL_SH_CPG_T3 ? (
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(CYGHWR_HAL_SH_OOC_CLOCK_MODE == 7)
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? (CYGHWR_HAL_SH_OOC_XTAL)
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: CYGHWR_HAL_SH_PLL2_OUTPUT
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)
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: 0 }
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}
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cdl_option CYGHWR_HAL_SH_PLL1_OUTPUT {
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display "The clock output from PLL1"
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no_define
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flavor data
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calculated { CYGHWR_HAL_SH_CLOCK_CKIO * CYGHWR_HAL_SH_OOC_PLL_1 }
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}
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cdl_option CYGHWR_HAL_SH_PLL2_OUTPUT {
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display "The clock output from PLL2"
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no_define
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flavor data
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calculated { CYGINT_HAL_SH_CPG_T1 ? (
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(CYGHWR_HAL_SH_OOC_XTAL * CYGHWR_HAL_SH_OOC_PLL_2)
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)
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: CYGINT_HAL_SH_CPG_T2 ? (
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(CYGHWR_HAL_SH_OOC_CLOCK_MODE == 5)
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? (CYGHWR_HAL_SH_OOC_XTAL / 2)
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: (CYGHWR_HAL_SH_OOC_CLOCK_MODE == 6)
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? (14745600)
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: (CYGHWR_HAL_SH_OOC_CLOCK_MODE == 7)
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? (11075600)
|
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: (CYGHWR_HAL_SH_OOC_XTAL * CYGHWR_HAL_SH_OOC_PLL_2)
|
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)
|
284 |
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: CYGINT_HAL_SH_CPG_T3 ? (
|
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(CYGHWR_HAL_SH_OOC_XTAL * CYGHWR_HAL_SH_OOC_PLL_2)
|
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)
|
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: 0 }
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}
|
289 |
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|
290 |
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291 |
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cdl_option CYGHWR_HAL_SH_DIVIDER1_INPUT {
|
292 |
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display "The clock input to divider 1"
|
293 |
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no_define
|
294 |
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flavor data
|
295 |
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# DIV1 input is either PLL2 output or PLL1 output
|
296 |
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calculated { (CYGHWR_HAL_SH_OOC_PLL_1 == 0)
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? CYGHWR_HAL_SH_PLL2_OUTPUT
|
298 |
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: CYGHWR_HAL_SH_PLL1_OUTPUT }
|
299 |
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}
|
300 |
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|
301 |
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cdl_option CYGHWR_HAL_SH_DIVIDER2_INPUT {
|
302 |
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display "The clock input to divider 2"
|
303 |
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no_define
|
304 |
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flavor data
|
305 |
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# DIV2 input is either PLL2 output or PLL1 output
|
306 |
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calculated { CYGINT_HAL_SH_CPG_T1 ? (
|
307 |
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(CYGHWR_HAL_SH_OOC_CLOCK_MODE == 3 || CYGHWR_HAL_SH_OOC_CLOCK_MODE == 4)
|
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? CYGHWR_HAL_SH_PLL2_OUTPUT
|
309 |
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: CYGHWR_HAL_SH_PLL1_OUTPUT
|
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)
|
311 |
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: CYGINT_HAL_SH_CPG_T2 ? (
|
312 |
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(CYGHWR_HAL_SH_OOC_CLOCK_MODE <= 2)
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? CYGHWR_HAL_SH_PLL1_OUTPUT
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: CYGHWR_HAL_SH_PLL2_OUTPUT
|
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)
|
316 |
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: CYGINT_HAL_SH_CPG_T3 ? (
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317 |
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(CYGHWR_HAL_SH_OOC_CLOCK_MODE == 3 || CYGHWR_HAL_SH_OOC_CLOCK_MODE == 4)
|
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? CYGHWR_HAL_SH_PLL2_OUTPUT
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319 |
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: CYGHWR_HAL_SH_PLL1_OUTPUT
|
320 |
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)
|
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: 0 }
|
322 |
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}
|
323 |
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324 |
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cdl_option CYGHWR_HAL_SH_PROCESSOR_SPEED {
|
325 |
|
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display "Processor clock speed (MHz)"
|
326 |
|
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flavor data
|
327 |
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calculated { CYGHWR_HAL_SH_DIVIDER1_INPUT / CYGHWR_HAL_SH_OOC_DIVIDER_1 }
|
328 |
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description "
|
329 |
|
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The core (CPU, cache and MMU) speed is computed from
|
330 |
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the input clock speed and the divider 1 setting."
|
331 |
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}
|
332 |
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|
333 |
|
|
cdl_option CYGHWR_HAL_SH_BOARD_SPEED {
|
334 |
|
|
display "Platform bus clock speed (MHz)"
|
335 |
|
|
flavor data
|
336 |
|
|
calculated { CYGHWR_HAL_SH_CLOCK_CKIO }
|
337 |
|
|
description "
|
338 |
|
|
The platform bus speed is CKIO."
|
339 |
|
|
}
|
340 |
|
|
|
341 |
|
|
cdl_option CYGHWR_HAL_SH_ONCHIP_PERIPHERAL_SPEED {
|
342 |
|
|
display "Processor on-chip peripheral clock speed (MHz)"
|
343 |
|
|
flavor data
|
344 |
|
|
calculated { CYGHWR_HAL_SH_DIVIDER2_INPUT / CYGHWR_HAL_SH_OOC_DIVIDER_2 }
|
345 |
|
|
description "
|
346 |
|
|
The peripheral speed is computed from the input clock
|
347 |
|
|
speed and the divider 2 settings."
|
348 |
|
|
}
|
349 |
|
|
}
|
350 |
|
|
|
351 |
|
|
cdl_option CYGNUM_HAL_SH_SH3_SCI_BAUD_RATE {
|
352 |
|
|
display "SCI serial port default baud rate"
|
353 |
|
|
flavor data
|
354 |
|
|
legal_values { 4800 9600 14400 19200 38400 57600 115200 }
|
355 |
|
|
default_value { CYGNUM_HAL_SH_SH3_SCI_BAUD_RATE_DEFAULT ? \
|
356 |
|
|
CYGNUM_HAL_SH_SH3_SCI_BAUD_RATE_DEFAULT : 38400 }
|
357 |
|
|
description "
|
358 |
|
|
This controls the default baud rate used for communicating
|
359 |
|
|
with GDB / displaying diagnostic output."
|
360 |
|
|
}
|
361 |
|
|
|
362 |
|
|
cdl_option CYGNUM_HAL_SH_SH3_SCIF_BAUD_RATE {
|
363 |
|
|
display "SCIF serial ports default baud rate"
|
364 |
|
|
flavor data
|
365 |
|
|
legal_values { 4800 9600 14400 19200 38400 57600 115200 }
|
366 |
|
|
default_value { CYGNUM_HAL_SH_SH3_SCIF_BAUD_RATE_DEFAULT ? \
|
367 |
|
|
CYGNUM_HAL_SH_SH3_SCIF_BAUD_RATE_DEFAULT : 38400 }
|
368 |
|
|
description "
|
369 |
|
|
This controls the default baud rate used for communicating
|
370 |
|
|
with GDB / displaying diagnostic output."
|
371 |
|
|
}
|
372 |
|
|
|
373 |
|
|
cdl_component CYGPKG_HAL_SH_INTERRUPT {
|
374 |
|
|
display "Interrupt controls"
|
375 |
|
|
flavor none
|
376 |
|
|
no_define
|
377 |
|
|
description "
|
378 |
|
|
Initial interrupt settings can be specified using these option."
|
379 |
|
|
|
380 |
|
|
cdl_option CYGHWR_HAL_SH_IRQ_HANDLE_SPURIOUS_INTERRUPTS {
|
381 |
|
|
display "Handle spurious interrupts"
|
382 |
|
|
default_value 0
|
383 |
|
|
description "
|
384 |
|
|
The SH3 may generate spurious interrupts with INTEVT = 0
|
385 |
|
|
when changing the BL bit of the status register. Enabling
|
386 |
|
|
this option will cause such interrupts to be identified
|
387 |
|
|
very early in the interrupt handler and be ignored. Given
|
388 |
|
|
that the SH HAL uses the I-mask to control interrupts,
|
389 |
|
|
these spurious interrupts should not occur, and so there
|
390 |
|
|
should be no reason to include the special handling code."
|
391 |
|
|
}
|
392 |
|
|
|
393 |
|
|
cdl_option CYGHWR_HAL_SH_IRQ_USE_IRQLVL {
|
394 |
|
|
display "Use IRQ0-3 pins as IRL input"
|
395 |
|
|
default_value 0
|
396 |
|
|
description "
|
397 |
|
|
It is possible for the IRQ0-3 pins to be used as IRL
|
398 |
|
|
inputs by enabling this option."
|
399 |
|
|
}
|
400 |
|
|
|
401 |
|
|
cdl_option CYGHWR_HAL_SH_IRQ_ENABLE_IRLS_INTERRUPTS {
|
402 |
|
|
display "Enable IRLS interrupt pins"
|
403 |
|
|
default_value 0
|
404 |
|
|
active_if CYGHWR_HAL_SH_IRQ_USE_IRQLVL
|
405 |
|
|
description "
|
406 |
|
|
IRLS interrupt pins must be specifically
|
407 |
|
|
activated. When they are, they will cause the same
|
408 |
|
|
type of interrupt as those caused by the IRL pins. If
|
409 |
|
|
IRL and IRLS pins signal an interrupt at the same
|
410 |
|
|
time, the highest level interrupt will be generated.
|
411 |
|
|
Only available on some cores, and probably share pins
|
412 |
|
|
with other interrupt sources (PINT) which cannot be
|
413 |
|
|
used in this configuration."
|
414 |
|
|
}
|
415 |
|
|
}
|
416 |
|
|
|
417 |
|
|
# Cache settings
|
418 |
|
|
cdl_option CYGHWR_HAL_SH_CACHE_MODE_P0 {
|
419 |
|
|
display "Select cache mode set for P0/U0/P3 at startup"
|
420 |
|
|
parent CYGPKG_HAL_SH_CACHE
|
421 |
|
|
default_value { "WRITE_BACK" }
|
422 |
|
|
legal_values { "WRITE_BACK" "WRITE_THROUGH" }
|
423 |
|
|
flavor data
|
424 |
|
|
description "
|
425 |
|
|
Controls what cache mode the cache should be put in at
|
426 |
|
|
startup for areas P0, U0 and P3. Write-back mode improves
|
427 |
|
|
performance by letting dirty data to be kept in the
|
428 |
|
|
cache for a period of time, allowing mutiple writes to
|
429 |
|
|
the same cache line to be written back to memory in
|
430 |
|
|
one memory transaction. In Write-through mode, each
|
431 |
|
|
individual write will cause a memory transaction."
|
432 |
|
|
}
|
433 |
|
|
|
434 |
|
|
cdl_option CYGHWR_HAL_SH_CACHE_MODE_P1 {
|
435 |
|
|
display "Select cache mode set for P1 at startup"
|
436 |
|
|
parent CYGPKG_HAL_SH_CACHE
|
437 |
|
|
default_value { "WRITE_BACK" }
|
438 |
|
|
legal_values { "WRITE_BACK" "WRITE_THROUGH" }
|
439 |
|
|
flavor data
|
440 |
|
|
description "
|
441 |
|
|
Controls what cache mode the cache should be put in at
|
442 |
|
|
startup for area P1. Write-back mode improves
|
443 |
|
|
performance by letting dirty data to be kept in the
|
444 |
|
|
cache for a period of time, allowing mutiple writes to
|
445 |
|
|
the same cache line to be written back to memory in
|
446 |
|
|
one memory transaction. In Write-through mode, each
|
447 |
|
|
individual write will cause a memory transaction."
|
448 |
|
|
}
|
449 |
|
|
}
|