| 1 |
786 |
skrzyp |
//=============================================================================
|
| 2 |
|
|
//
|
| 3 |
|
|
// mod_regs_tmu.h
|
| 4 |
|
|
//
|
| 5 |
|
|
// TMU (timer unit) Module register definitions
|
| 6 |
|
|
//
|
| 7 |
|
|
//=============================================================================
|
| 8 |
|
|
// ####ECOSGPLCOPYRIGHTBEGIN####
|
| 9 |
|
|
// -------------------------------------------
|
| 10 |
|
|
// This file is part of eCos, the Embedded Configurable Operating System.
|
| 11 |
|
|
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
|
| 12 |
|
|
//
|
| 13 |
|
|
// eCos is free software; you can redistribute it and/or modify it under
|
| 14 |
|
|
// the terms of the GNU General Public License as published by the Free
|
| 15 |
|
|
// Software Foundation; either version 2 or (at your option) any later
|
| 16 |
|
|
// version.
|
| 17 |
|
|
//
|
| 18 |
|
|
// eCos is distributed in the hope that it will be useful, but WITHOUT
|
| 19 |
|
|
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
| 20 |
|
|
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
| 21 |
|
|
// for more details.
|
| 22 |
|
|
//
|
| 23 |
|
|
// You should have received a copy of the GNU General Public License
|
| 24 |
|
|
// along with eCos; if not, write to the Free Software Foundation, Inc.,
|
| 25 |
|
|
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
| 26 |
|
|
//
|
| 27 |
|
|
// As a special exception, if other files instantiate templates or use
|
| 28 |
|
|
// macros or inline functions from this file, or you compile this file
|
| 29 |
|
|
// and link it with other works to produce a work based on this file,
|
| 30 |
|
|
// this file does not by itself cause the resulting work to be covered by
|
| 31 |
|
|
// the GNU General Public License. However the source code for this file
|
| 32 |
|
|
// must still be made available in accordance with section (3) of the GNU
|
| 33 |
|
|
// General Public License v2.
|
| 34 |
|
|
//
|
| 35 |
|
|
// This exception does not invalidate any other reasons why a work based
|
| 36 |
|
|
// on this file might be covered by the GNU General Public License.
|
| 37 |
|
|
// -------------------------------------------
|
| 38 |
|
|
// ####ECOSGPLCOPYRIGHTEND####
|
| 39 |
|
|
//=============================================================================
|
| 40 |
|
|
//#####DESCRIPTIONBEGIN####
|
| 41 |
|
|
//
|
| 42 |
|
|
// Author(s): jskov
|
| 43 |
|
|
// Contributors:jskov
|
| 44 |
|
|
// Date: 2000-10-30
|
| 45 |
|
|
//
|
| 46 |
|
|
//####DESCRIPTIONEND####
|
| 47 |
|
|
//
|
| 48 |
|
|
//=============================================================================
|
| 49 |
|
|
|
| 50 |
|
|
//--------------------------------------------------------------------------
|
| 51 |
|
|
// TMU registers
|
| 52 |
|
|
#define CYGARC_REG_TOCR 0xfffffe90 // 8 bit
|
| 53 |
|
|
#define CYGARC_REG_TSTR 0xfffffe92 // 8 bit
|
| 54 |
|
|
#define CYGARC_REG_TCOR0 0xfffffe94 // 32 bit
|
| 55 |
|
|
#define CYGARC_REG_TCNT0 0xfffffe98 // 32 bit
|
| 56 |
|
|
#define CYGARC_REG_TCR0 0xfffffe9c // 16 bit
|
| 57 |
|
|
#define CYGARC_REG_TCOR1 0xfffffea0 // 32 bit
|
| 58 |
|
|
#define CYGARC_REG_TCNT1 0xfffffea4 // 32 bit
|
| 59 |
|
|
#define CYGARC_REG_TCR1 0xfffffea8 // 16 bit
|
| 60 |
|
|
#define CYGARC_REG_TCOR2 0xfffffeac // 32 bit
|
| 61 |
|
|
#define CYGARC_REG_TCNT2 0xfffffeb0 // 32 bit
|
| 62 |
|
|
#define CYGARC_REG_TCR2 0xfffffeb4 // 16 bit
|
| 63 |
|
|
#define CYGARC_REG_TCPR2 0xfffffeb8 // 32 bit
|
| 64 |
|
|
|
| 65 |
|
|
// TSTR
|
| 66 |
|
|
#define CYGARC_REG_TSTR_STR0 0x0001
|
| 67 |
|
|
#define CYGARC_REG_TSTR_STR1 0x0002
|
| 68 |
|
|
#define CYGARC_REG_TSTR_STR2 0x0004
|
| 69 |
|
|
|
| 70 |
|
|
// TCR0/1/2
|
| 71 |
|
|
#define CYGARC_REG_TCR_TPSC0 0x0001
|
| 72 |
|
|
#define CYGARC_REG_TCR_TPSC1 0x0002
|
| 73 |
|
|
#define CYGARC_REG_TCR_TPSC2 0x0004
|
| 74 |
|
|
#define CYGARC_REG_TCR_CKEG0 0x0008
|
| 75 |
|
|
#define CYGARC_REG_TCR_CKEG1 0x0010
|
| 76 |
|
|
#define CYGARC_REG_TCR_UNIE 0x0020
|
| 77 |
|
|
#define CYGARC_REG_TCR_UNF 0x0100
|
| 78 |
|
|
|
| 79 |
|
|
#define CYGARC_REG_TCR_TPSC_4 (0)
|
| 80 |
|
|
#define CYGARC_REG_TCR_TPSC_16 (CYGARC_REG_TCR_TPSC0)
|
| 81 |
|
|
#define CYGARC_REG_TCR_TPSC_64 (CYGARC_REG_TCR_TPSC1)
|
| 82 |
|
|
#define CYGARC_REG_TCR_TPSC_256 (CYGARC_REG_TCR_TPSC0|CYGARC_REG_TCR_TPSC1)
|
| 83 |
|
|
|
| 84 |
|
|
// TCR2 additional bits
|
| 85 |
|
|
#define CYGARC_REG_TCR_ICPE0 0x0040
|
| 86 |
|
|
#define CYGARC_REG_TCR_ICPE1 0x0080
|
| 87 |
|
|
#define CYGARC_REG_TCR_ICPF 0x0200
|
