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skrzyp |
#ifndef CYGONCE_HAL_SD0001_H
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#define CYGONCE_HAL_SD0001_H
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//=============================================================================
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//
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// sd0001.h
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//
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// SD0001 support chip - used with SH/7729
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//
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//=============================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later
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// version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
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// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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//
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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//=============================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): jskov
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// Contributors:jskov
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// Date: 2001-05-25
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// Purpose: Support chip
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// Usage: Included from <cyg/hal/sh_regs.h>
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//
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//
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//####DESCRIPTIONEND####
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//
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//=============================================================================
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#ifndef _SD0001_BASE
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# define _SD0001_BASE 0xb0000000
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#endif
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//-----------------------------------------------------------------------------
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// System configuration
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#define CYGARC_REG_SD0001_RESET (_SD0001_BASE + 0x08)
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#define CYGARC_REG_SD0001_SDRAM (_SD0001_BASE + 0x10)
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#define CYGARC_REG_SD0001_INT_STS1 (_SD0001_BASE + 0x20)
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#define CYGARC_REG_SD0001_INT_ENABLE (_SD0001_BASE + 0x24)
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#define CYGARC_REG_SD0001_INT_STS2 (_SD0001_BASE + 0x28)
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#define CYGARC_REG_SD0001_PCI_CTL (_SD0001_BASE + 0x50)
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#define CYGARC_REG_PCI_IO_MEMOFFSET (_SD0001_BASE + 0x58)
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#define CYGARC_REG_PCI_MEM_MEMOFFSET (_SD0001_BASE + 0x5c)
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#define CYGARC_REG_PCI_CFG_ADDR (_SD0001_BASE + 0x60)
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#define CYGARC_REG_PCI_CFG_DATA (_SD0001_BASE + 0x64)
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#define CYGARC_REG_PCI_CFG_CMD (_SD0001_BASE + 0x68)
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#define CYGARC_REG_PCI_CFG_FLG (_SD0001_BASE + 0x6c)
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#define CYGARC_REG_PCI_CFG_ADDR_ENABLE 0x80000000
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#define CYGARC_REG_PCI_CFG_ADDR_BUSNO_shift 16
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#define CYGARC_REG_PCI_CFG_ADDR_FUNC_shift 8
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#define CYGARC_REG_PCI_CFG_CMD_BE3 0x00080000
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#define CYGARC_REG_PCI_CFG_CMD_BE2 0x00040000
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#define CYGARC_REG_PCI_CFG_CMD_BE1 0x00020000
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#define CYGARC_REG_PCI_CFG_CMD_BE0 0x00010000
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#define CYGARC_REG_PCI_CFG_CMD_CMDEN 0x00008000
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#define CYGARC_REG_PCI_CFG_CMD_IO_WRITE 0x00000300
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#define CYGARC_REG_PCI_CFG_CMD_IO_READ 0x00000200
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#define CYGARC_REG_PCI_CFG_CMD_WT 0x00000008
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#define CYGARC_REG_PCI_CFG_CMD_RD 0x00000004
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#define CYGARC_REG_PCI_CFG_CMD_CFWT 0x00000002
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#define CYGARC_REG_PCI_CFG_CMD_CFRD 0x00000001
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#define CYGARC_REG_PCI_CFG_CMD_WCFG (CYGARC_REG_PCI_CFG_CMD_BE3|CYGARC_REG_PCI_CFG_CMD_BE2|CYGARC_REG_PCI_CFG_CMD_BE1|CYGARC_REG_PCI_CFG_CMD_BE0|CYGARC_REG_PCI_CFG_CMD_CFWT)
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#define CYGARC_REG_PCI_CFG_CMD_RCFG (CYGARC_REG_PCI_CFG_CMD_BE3|CYGARC_REG_PCI_CFG_CMD_BE2|CYGARC_REG_PCI_CFG_CMD_BE1|CYGARC_REG_PCI_CFG_CMD_BE0|CYGARC_REG_PCI_CFG_CMD_CFRD)
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#define CYGARC_REG_SD0001_PCI_CTL_ENDIAN2 0x40000000
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#define CYGARC_REG_SD0001_PCI_CTL_MAX_DEADLOCK_CNT 0x0000ff00
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#define CYGARC_REG_SD0001_PCI_CTL_MAX_RETRY_CNT 0x000000f0
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#define CYGARC_REG_PCI_CFG_FLG_ACTIVE 0x00000001
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#define CYGARC_REG_SD0001_RESET_SWRST 0x80000000
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#define CYGARC_REG_SD0001_RESET_PCIRST 0x40000000
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#define CYGARC_REG_SD0001_SDRAM_SDKIND_128M 0x80000000
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#define CYGARC_REG_SD0001_SDRAM_SDSIZE_8 0x10000000
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#define CYGARC_REG_SD0001_SDRAM_REF_MUMBLE 0x00008000
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#define CYGARC_REG_SD0001_SDRAM_LMODE_CAS2 0x00000010
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#define CYGARC_REG_SD0001_SDRAM_INIT (CYGARC_REG_SD0001_SDRAM_SDKIND_128M\
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|CYGARC_REG_SD0001_SDRAM_SDSIZE_8\
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|CYGARC_REG_SD0001_SDRAM_REF_MUMBLE\
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|CYGARC_REG_SD0001_SDRAM_LMODE_CAS2)
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#define CYGARC_REG_SD0001_INT_EN 0x80000000
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#define CYGARC_REG_SD0001_INT_INTD 0x00000008
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#define CYGARC_REG_SD0001_INT_INTC 0x00000004
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#define CYGARC_REG_SD0001_INT_INTB 0x00000002
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#define CYGARC_REG_SD0001_INT_INTA 0x00000001
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#endif // CYGONCE_HAL_SD0001_H
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