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786 |
skrzyp |
//==========================================================================
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//
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// var_misc.c
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//
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// HAL miscellaneous functions
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//
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//==========================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later
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// version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
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// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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//
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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//==========================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): jskov
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// Contributors: jskov, jlarmour, nickg
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// Date: 1999-04-03
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// Purpose: HAL miscellaneous functions
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// Description: This file contains miscellaneous functions provided by the
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// HAL.
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//
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//####DESCRIPTIONEND####
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//
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//===========================================================================
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#include <pkgconf/hal.h>
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#include <cyg/infra/cyg_type.h>
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#include <cyg/infra/cyg_trac.h> // tracing macros
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#include <cyg/infra/cyg_ass.h> // assertion macros
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#include <cyg/infra/diag.h> // diag_printf
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#include <cyg/hal/hal_arch.h> // HAL header
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#include <cyg/hal/hal_cache.h> // HAL cache
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#include <cyg/hal/hal_intr.h> // HAL interrupts/exceptions
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//---------------------------------------------------------------------------
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// Initial cache enabling
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#ifdef CYGHWR_HAL_SH_CACHE_MODE_P0_WRITE_BACK
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# define CACHE_MODE_P0 0
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#else
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# define CACHE_MODE_P0 CYGARC_REG_CCR_WT
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#endif
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#ifdef CYGHWR_HAL_SH_CACHE_MODE_P1_WRITE_BACK
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# define CACHE_MODE_P1 CYGARC_REG_CCR_CB
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#else
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# define CACHE_MODE_P1 0
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#endif
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externC void
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cyg_var_enable_caches(void)
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{
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// If relying on a ROM monitor do not invalidate the caches as the
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// ROM monitor may have (non-synced) state in the caches.
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#if !defined(CYGSEM_HAL_USE_ROM_MONITOR)
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// Initialize cache.
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HAL_UCACHE_INVALIDATE_ALL();
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// Set cache modes
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HAL_UCACHE_WRITE_MODE_SH(CACHE_MODE_P0|CACHE_MODE_P1);
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#endif
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#ifdef CYGHWR_HAL_SH_CACHE_ENABLE
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// Enable cache.
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HAL_UCACHE_ENABLE();
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#endif
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}
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//---------------------------------------------------------------------------
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void
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hal_variant_init(void)
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{
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}
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//---------------------------------------------------------------------------
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// Interrupt function support
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externC cyg_uint8 cyg_hal_ILVL_table[];
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externC cyg_uint8 cyg_hal_IMASK_table[];
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static void
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hal_interrupt_update_level(int vector)
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{
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cyg_uint16 iprX;
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int level;
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level = cyg_hal_IMASK_table[vector] ? cyg_hal_ILVL_table[vector] : 0;
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switch( (vector) ) {
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/* IPRA */
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case CYGNUM_HAL_INTERRUPT_TMU0_TUNI0:
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HAL_READ_UINT16(CYGARC_REG_IPRA, iprX);
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iprX &= ~CYGARC_REG_IPRA_TMU0_MASK;
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iprX |= (level)*CYGARC_REG_IPRA_TMU0_PRI1;
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HAL_WRITE_UINT16(CYGARC_REG_IPRA, iprX);
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break;
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case CYGNUM_HAL_INTERRUPT_TMU1_TUNI1:
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HAL_READ_UINT16(CYGARC_REG_IPRA, iprX);
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iprX &= ~CYGARC_REG_IPRA_TMU1_MASK;
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iprX |= (level)*CYGARC_REG_IPRA_TMU1_PRI1;
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HAL_WRITE_UINT16(CYGARC_REG_IPRA, iprX);
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break;
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case CYGNUM_HAL_INTERRUPT_TMU2_TUNI2:
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case CYGNUM_HAL_INTERRUPT_TMU2_TICPI2:
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HAL_READ_UINT16(CYGARC_REG_IPRA, iprX);
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iprX &= ~CYGARC_REG_IPRA_TMU2_MASK;
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iprX |= (level)*CYGARC_REG_IPRA_TMU2_PRI1;
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HAL_WRITE_UINT16(CYGARC_REG_IPRA, iprX);
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break;
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case CYGNUM_HAL_INTERRUPT_RTC_ATI:
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case CYGNUM_HAL_INTERRUPT_RTC_PRI:
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case CYGNUM_HAL_INTERRUPT_RTC_CUI:
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HAL_READ_UINT16(CYGARC_REG_IPRA, iprX);
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iprX &= ~CYGARC_REG_IPRA_RTC_MASK;
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iprX |= (level)*CYGARC_REG_IPRA_RTC_PRI1;
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HAL_WRITE_UINT16(CYGARC_REG_IPRA, iprX);
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break;
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/* IPRB */
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case CYGNUM_HAL_INTERRUPT_SCI_ERI:
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case CYGNUM_HAL_INTERRUPT_SCI_RXI:
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case CYGNUM_HAL_INTERRUPT_SCI_TXI:
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case CYGNUM_HAL_INTERRUPT_SCI_TEI:
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HAL_READ_UINT16(CYGARC_REG_IPRB, iprX);
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iprX &= ~CYGARC_REG_IPRB_SCI_MASK;
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iprX |= (level)*CYGARC_REG_IPRB_SCI_PRI1;
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HAL_WRITE_UINT16(CYGARC_REG_IPRB, iprX);
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break;
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case CYGNUM_HAL_INTERRUPT_WDT_ITI:
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HAL_READ_UINT16(CYGARC_REG_IPRB, iprX);
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iprX &= ~CYGARC_REG_IPRB_WDT_MASK;
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iprX |= (level)*CYGARC_REG_IPRB_WDT_PRI1;
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HAL_WRITE_UINT16(CYGARC_REG_IPRB, iprX);
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break;
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case CYGNUM_HAL_INTERRUPT_REF_RCMI:
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case CYGNUM_HAL_INTERRUPT_REF_ROVI:
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HAL_READ_UINT16(CYGARC_REG_IPRB, iprX);
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iprX &= ~CYGARC_REG_IPRB_REF_MASK;
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iprX |= (level)*CYGARC_REG_IPRB_REF_PRI1;
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HAL_WRITE_UINT16(CYGARC_REG_IPRB, iprX);
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break;
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#if (CYGARC_SH_MOD_INTC >= 2)
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#ifndef CYGHWR_HAL_SH_IRQ_USE_IRQLVL
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/* IPRC */
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case CYGNUM_HAL_INTERRUPT_IRQ_IRQ0:
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HAL_READ_UINT16(CYGARC_REG_IPRC, iprX);
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iprX &= ~CYGARC_REG_IPRC_IRQ0_MASK;
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iprX |= (level)*CYGARC_REG_IPRC_IRQ0_PRI1;
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HAL_WRITE_UINT16(CYGARC_REG_IPRC, iprX);
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break;
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case CYGNUM_HAL_INTERRUPT_IRQ_IRQ1:
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HAL_READ_UINT16(CYGARC_REG_IPRC, iprX);
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iprX &= ~CYGARC_REG_IPRC_IRQ1_MASK;
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iprX |= (level)*CYGARC_REG_IPRC_IRQ1_PRI1;
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HAL_WRITE_UINT16(CYGARC_REG_IPRC, iprX);
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break;
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case CYGNUM_HAL_INTERRUPT_IRQ_IRQ2:
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HAL_READ_UINT16(CYGARC_REG_IPRC, iprX);
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iprX &= ~CYGARC_REG_IPRC_IRQ2_MASK;
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iprX |= (level)*CYGARC_REG_IPRC_IRQ2_PRI1;
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HAL_WRITE_UINT16(CYGARC_REG_IPRC, iprX);
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break;
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case CYGNUM_HAL_INTERRUPT_IRQ_IRQ3:
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HAL_READ_UINT16(CYGARC_REG_IPRC, iprX);
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iprX &= ~CYGARC_REG_IPRC_IRQ3_MASK;
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iprX |= (level)*CYGARC_REG_IPRC_IRQ3_PRI1;
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HAL_WRITE_UINT16(CYGARC_REG_IPRC, iprX);
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break;
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#endif
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/* IPRD */
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case CYGNUM_HAL_INTERRUPT_PINT_PINT07:
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HAL_READ_UINT16(CYGARC_REG_IPRD, iprX);
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iprX &= ~CYGARC_REG_IPRD_PINT07_MASK;
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iprX |= (level)*CYGARC_REG_IPRD_PINT07_PRI1;
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HAL_WRITE_UINT16(CYGARC_REG_IPRD, iprX);
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break;
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case CYGNUM_HAL_INTERRUPT_PINT_PINT8F:
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HAL_READ_UINT16(CYGARC_REG_IPRD, iprX);
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iprX &= ~CYGARC_REG_IPRD_PINT8F_MASK;
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iprX |= (level)*CYGARC_REG_IPRD_PINT8F_PRI1;
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HAL_WRITE_UINT16(CYGARC_REG_IPRD, iprX);
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break;
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case CYGNUM_HAL_INTERRUPT_IRQ_IRQ5:
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HAL_READ_UINT16(CYGARC_REG_IPRD, iprX);
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iprX &= ~CYGARC_REG_IPRD_IRQ5_MASK;
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iprX |= (level)*CYGARC_REG_IPRD_IRQ5_PRI1;
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| 216 |
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HAL_WRITE_UINT16(CYGARC_REG_IPRD, iprX);
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| 217 |
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break;
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| 218 |
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case CYGNUM_HAL_INTERRUPT_IRQ_IRQ4:
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| 219 |
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HAL_READ_UINT16(CYGARC_REG_IPRD, iprX);
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| 220 |
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iprX &= ~CYGARC_REG_IPRD_IRQ4_MASK;
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| 221 |
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iprX |= (level)*CYGARC_REG_IPRD_IRQ4_PRI1;
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| 222 |
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HAL_WRITE_UINT16(CYGARC_REG_IPRD, iprX);
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| 223 |
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break;
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| 224 |
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| 225 |
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/* IPRE */
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| 226 |
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case CYGNUM_HAL_INTERRUPT_DMAC_DEI0:
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| 227 |
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case CYGNUM_HAL_INTERRUPT_DMAC_DEI1:
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| 228 |
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case CYGNUM_HAL_INTERRUPT_DMAC_DEI2:
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| 229 |
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case CYGNUM_HAL_INTERRUPT_DMAC_DEI3:
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| 230 |
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HAL_READ_UINT16(CYGARC_REG_IPRE, iprX);
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| 231 |
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iprX &= ~CYGARC_REG_IPRE_DMAC_MASK;
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| 232 |
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iprX |= (level)*CYGARC_REG_IPRE_DMAC_PRI1;
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| 233 |
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HAL_WRITE_UINT16(CYGARC_REG_IPRE, iprX);
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| 234 |
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break;
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| 235 |
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case CYGNUM_HAL_INTERRUPT_IRDA_ERI1:
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| 236 |
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case CYGNUM_HAL_INTERRUPT_IRDA_RXI1:
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| 237 |
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case CYGNUM_HAL_INTERRUPT_IRDA_BRI1:
|
| 238 |
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case CYGNUM_HAL_INTERRUPT_IRDA_TXI1:
|
| 239 |
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HAL_READ_UINT16(CYGARC_REG_IPRE, iprX);
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| 240 |
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iprX &= ~CYGARC_REG_IPRE_IRDA_MASK;
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| 241 |
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iprX |= (level)*CYGARC_REG_IPRE_IRDA_PRI1;
|
| 242 |
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HAL_WRITE_UINT16(CYGARC_REG_IPRE, iprX);
|
| 243 |
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break;
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| 244 |
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case CYGNUM_HAL_INTERRUPT_SCIF_ERI2:
|
| 245 |
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case CYGNUM_HAL_INTERRUPT_SCIF_RXI2:
|
| 246 |
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case CYGNUM_HAL_INTERRUPT_SCIF_BRI2:
|
| 247 |
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case CYGNUM_HAL_INTERRUPT_SCIF_TXI2:
|
| 248 |
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HAL_READ_UINT16(CYGARC_REG_IPRE, iprX);
|
| 249 |
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iprX &= ~CYGARC_REG_IPRE_SCIF_MASK;
|
| 250 |
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iprX |= (level)*CYGARC_REG_IPRE_SCIF_PRI1;
|
| 251 |
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HAL_WRITE_UINT16(CYGARC_REG_IPRE, iprX);
|
| 252 |
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break;
|
| 253 |
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case CYGNUM_HAL_INTERRUPT_ADC_ADI:
|
| 254 |
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HAL_READ_UINT16(CYGARC_REG_IPRE, iprX);
|
| 255 |
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iprX &= ~CYGARC_REG_IPRE_ADC_MASK;
|
| 256 |
|
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iprX |= (level)*CYGARC_REG_IPRE_ADC_PRI1;
|
| 257 |
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HAL_WRITE_UINT16(CYGARC_REG_IPRE, iprX);
|
| 258 |
|
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break;
|
| 259 |
|
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#endif // (CYGARC_SH_MOD_INTC >= 2)
|
| 260 |
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|
| 261 |
|
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#if (CYGARC_SH_MOD_INTC >= 3)
|
| 262 |
|
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/* IPRF */
|
| 263 |
|
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case CYGNUM_HAL_INTERRUPT_LCDC_LCDI:
|
| 264 |
|
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HAL_READ_UINT16(CYGARC_REG_IPRF, iprX);
|
| 265 |
|
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iprX &= ~CYGARC_REG_IPRF_LCDI_MASK;
|
| 266 |
|
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iprX |= (level)*CYGARC_REG_IPRF_LCDI_PRI1;
|
| 267 |
|
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HAL_WRITE_UINT16(CYGARC_REG_IPRF, iprX);
|
| 268 |
|
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break;
|
| 269 |
|
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case CYGNUM_HAL_INTERRUPT_PCC_PCC0:
|
| 270 |
|
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HAL_READ_UINT16(CYGARC_REG_IPRF, iprX);
|
| 271 |
|
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iprX &= ~CYGARC_REG_IPRF_PCC0_MASK;
|
| 272 |
|
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iprX |= (level)*CYGARC_REG_IPRF_PCC0_PRI1;
|
| 273 |
|
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HAL_WRITE_UINT16(CYGARC_REG_IPRF, iprX);
|
| 274 |
|
|
break;
|
| 275 |
|
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case CYGNUM_HAL_INTERRUPT_PCC_PCC1:
|
| 276 |
|
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HAL_READ_UINT16(CYGARC_REG_IPRF, iprX);
|
| 277 |
|
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iprX &= ~CYGARC_REG_IPRF_PCC1_MASK;
|
| 278 |
|
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iprX |= (level)*CYGARC_REG_IPRF_PCC1_PRI1;
|
| 279 |
|
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HAL_WRITE_UINT16(CYGARC_REG_IPRF, iprX);
|
| 280 |
|
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break;
|
| 281 |
|
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#endif // (CYGARC_SH_MOD_INTC >= 3)
|
| 282 |
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|
|
| 283 |
|
|
case CYGNUM_HAL_INTERRUPT_RESERVED_1E0:
|
| 284 |
|
|
case CYGNUM_HAL_INTERRUPT_RESERVED_3E0:
|
| 285 |
|
|
/* Do nothing for these reserved vectors. */
|
| 286 |
|
|
break;
|
| 287 |
|
|
|
| 288 |
|
|
// Platform extensions
|
| 289 |
|
|
CYGPRI_HAL_INTERRUPT_UPDATE_LEVEL_PLF(vector, level)
|
| 290 |
|
|
|
| 291 |
|
|
default:
|
| 292 |
|
|
CYG_FAIL("Unknown interrupt vector");
|
| 293 |
|
|
break;
|
| 294 |
|
|
}
|
| 295 |
|
|
}
|
| 296 |
|
|
|
| 297 |
|
|
void
|
| 298 |
|
|
hal_interrupt_set_level(int vector, int level)
|
| 299 |
|
|
{
|
| 300 |
|
|
CYG_ASSERT((0 <= (level) && 15 >= (level)), "Illegal level");
|
| 301 |
|
|
CYG_ASSERT((CYGNUM_HAL_ISR_MIN <= (vector)
|
| 302 |
|
|
&& CYGNUM_HAL_ISR_MAX >= (vector)), "Illegal vector");
|
| 303 |
|
|
|
| 304 |
|
|
cyg_hal_ILVL_table[vector] = level;
|
| 305 |
|
|
|
| 306 |
|
|
hal_interrupt_update_level(vector);
|
| 307 |
|
|
}
|
| 308 |
|
|
|
| 309 |
|
|
void
|
| 310 |
|
|
hal_interrupt_mask(int vector)
|
| 311 |
|
|
{
|
| 312 |
|
|
switch( (vector) ) {
|
| 313 |
|
|
case CYGNUM_HAL_INTERRUPT_NMI:
|
| 314 |
|
|
/* fall through */
|
| 315 |
|
|
case CYGNUM_HAL_INTERRUPT_LVL0 ... CYGNUM_HAL_INTERRUPT_LVL14:
|
| 316 |
|
|
/* Normally can only be masked by fiddling Imask in SR,
|
| 317 |
|
|
but some platforms use external interrupt controller,
|
| 318 |
|
|
so allow regular handling. */
|
| 319 |
|
|
// fall through
|
| 320 |
|
|
case CYGNUM_HAL_INTERRUPT_TMU0_TUNI0 ... CYGNUM_HAL_ISR_MAX:
|
| 321 |
|
|
cyg_hal_IMASK_table[vector] = 0;
|
| 322 |
|
|
hal_interrupt_update_level(vector);
|
| 323 |
|
|
break;
|
| 324 |
|
|
case CYGNUM_HAL_INTERRUPT_RESERVED_1E0:
|
| 325 |
|
|
case CYGNUM_HAL_INTERRUPT_RESERVED_3E0:
|
| 326 |
|
|
/* Do nothing for these reserved vectors. */
|
| 327 |
|
|
break;
|
| 328 |
|
|
default:
|
| 329 |
|
|
CYG_FAIL("Unknown interrupt vector");
|
| 330 |
|
|
break;
|
| 331 |
|
|
}
|
| 332 |
|
|
}
|
| 333 |
|
|
|
| 334 |
|
|
void
|
| 335 |
|
|
hal_interrupt_unmask(int vector)
|
| 336 |
|
|
{
|
| 337 |
|
|
switch( (vector) ) {
|
| 338 |
|
|
case CYGNUM_HAL_INTERRUPT_NMI:
|
| 339 |
|
|
/* fall through */
|
| 340 |
|
|
case CYGNUM_HAL_INTERRUPT_LVL0 ... CYGNUM_HAL_INTERRUPT_LVL14:
|
| 341 |
|
|
/* Normally can only be masked by fiddling Imask in SR,
|
| 342 |
|
|
but some platforms use external interrupt controller,
|
| 343 |
|
|
so allow regular handling. */
|
| 344 |
|
|
// fall through
|
| 345 |
|
|
case CYGNUM_HAL_INTERRUPT_TMU0_TUNI0 ... CYGNUM_HAL_ISR_MAX:
|
| 346 |
|
|
cyg_hal_IMASK_table[vector] = 1;
|
| 347 |
|
|
hal_interrupt_update_level(vector);
|
| 348 |
|
|
break;
|
| 349 |
|
|
case CYGNUM_HAL_INTERRUPT_RESERVED_1E0:
|
| 350 |
|
|
case CYGNUM_HAL_INTERRUPT_RESERVED_3E0:
|
| 351 |
|
|
/* Do nothing for these reserved vectors. */
|
| 352 |
|
|
break;
|
| 353 |
|
|
default:
|
| 354 |
|
|
CYG_FAIL("Unknown interrupt vector");
|
| 355 |
|
|
break;
|
| 356 |
|
|
}
|
| 357 |
|
|
}
|
| 358 |
|
|
|
| 359 |
|
|
void
|
| 360 |
|
|
hal_interrupt_acknowledge(int vector)
|
| 361 |
|
|
{
|
| 362 |
|
|
#if (CYGARC_SH_MOD_INTC >= 2)
|
| 363 |
|
|
if ( (vector) >= CYGNUM_HAL_INTERRUPT_IRQ_IRQ0
|
| 364 |
|
|
&& (vector) <= CYGNUM_HAL_INTERRUPT_IRQ_IRQ5) {
|
| 365 |
|
|
|
| 366 |
|
|
cyg_uint8 irr0;
|
| 367 |
|
|
|
| 368 |
|
|
HAL_READ_UINT8(CYGARC_REG_IRR0, irr0);
|
| 369 |
|
|
switch ( vector ) {
|
| 370 |
|
|
#ifndef CYGHWR_HAL_SH_IRQ_USE_IRQLVL
|
| 371 |
|
|
case CYGNUM_HAL_INTERRUPT_IRQ_IRQ0:
|
| 372 |
|
|
irr0 &= ~CYGARC_REG_IRR0_IRQ0;
|
| 373 |
|
|
break;
|
| 374 |
|
|
case CYGNUM_HAL_INTERRUPT_IRQ_IRQ1:
|
| 375 |
|
|
irr0 &= ~CYGARC_REG_IRR0_IRQ1;
|
| 376 |
|
|
break;
|
| 377 |
|
|
case CYGNUM_HAL_INTERRUPT_IRQ_IRQ2:
|
| 378 |
|
|
irr0 &= ~CYGARC_REG_IRR0_IRQ2;
|
| 379 |
|
|
break;
|
| 380 |
|
|
case CYGNUM_HAL_INTERRUPT_IRQ_IRQ3:
|
| 381 |
|
|
irr0 &= ~CYGARC_REG_IRR0_IRQ3;
|
| 382 |
|
|
break;
|
| 383 |
|
|
#endif
|
| 384 |
|
|
case CYGNUM_HAL_INTERRUPT_IRQ_IRQ4:
|
| 385 |
|
|
irr0 &= ~CYGARC_REG_IRR0_IRQ4;
|
| 386 |
|
|
break;
|
| 387 |
|
|
case CYGNUM_HAL_INTERRUPT_IRQ_IRQ5:
|
| 388 |
|
|
irr0 &= ~CYGARC_REG_IRR0_IRQ5;
|
| 389 |
|
|
break;
|
| 390 |
|
|
default:
|
| 391 |
|
|
CYG_FAIL("Unhandled interrupt vector");
|
| 392 |
|
|
}
|
| 393 |
|
|
HAL_WRITE_UINT8(CYGARC_REG_IRR0, irr0);
|
| 394 |
|
|
}
|
| 395 |
|
|
#endif
|
| 396 |
|
|
|
| 397 |
|
|
CYGPRI_HAL_INTERRUPT_ACKNOWLEDGE_PLF(vector);
|
| 398 |
|
|
}
|
| 399 |
|
|
|
| 400 |
|
|
// Note: The PINTs can be masked and configured individually, even
|
| 401 |
|
|
// though there are only two vectors. Maybe add some fake vectors just
|
| 402 |
|
|
// for masking/configuring?
|
| 403 |
|
|
void
|
| 404 |
|
|
hal_interrupt_configure(int vector, int level, int up)
|
| 405 |
|
|
{
|
| 406 |
|
|
#if (CYGARC_SH_MOD_INTC >= 2)
|
| 407 |
|
|
if ( (vector) >= CYGNUM_HAL_INTERRUPT_IRQ_IRQ0
|
| 408 |
|
|
&& (vector) <= CYGNUM_HAL_INTERRUPT_IRQ_IRQ5) {
|
| 409 |
|
|
|
| 410 |
|
|
cyg_uint16 icr1, ss, mask;
|
| 411 |
|
|
ss = 0;
|
| 412 |
|
|
mask = CYGARC_REG_ICR1_SENSE_UP|CYGARC_REG_ICR1_SENSE_LEVEL;
|
| 413 |
|
|
if (up) ss |= CYGARC_REG_ICR1_SENSE_UP;
|
| 414 |
|
|
if (level) ss |= CYGARC_REG_ICR1_SENSE_LEVEL;
|
| 415 |
|
|
CYG_ASSERT(!(up && level), "Cannot trigger on high level!");
|
| 416 |
|
|
|
| 417 |
|
|
switch( (vector) ) {
|
| 418 |
|
|
case CYGNUM_HAL_INTERRUPT_IRQ_IRQ5:
|
| 419 |
|
|
ss <<= CYGARC_REG_ICR1_SENSE_IRQ5_shift;
|
| 420 |
|
|
mask <<= CYGARC_REG_ICR1_SENSE_IRQ5_shift;
|
| 421 |
|
|
break;
|
| 422 |
|
|
case CYGNUM_HAL_INTERRUPT_IRQ_IRQ4:
|
| 423 |
|
|
ss <<= CYGARC_REG_ICR1_SENSE_IRQ4_shift;
|
| 424 |
|
|
mask <<= CYGARC_REG_ICR1_SENSE_IRQ4_shift;
|
| 425 |
|
|
break;
|
| 426 |
|
|
#ifndef CYGHWR_HAL_SH_IRQ_USE_IRQLVL
|
| 427 |
|
|
case CYGNUM_HAL_INTERRUPT_IRQ_IRQ3:
|
| 428 |
|
|
ss <<= CYGARC_REG_ICR1_SENSE_IRQ3_shift;
|
| 429 |
|
|
mask <<= CYGARC_REG_ICR1_SENSE_IRQ3_shift;
|
| 430 |
|
|
break;
|
| 431 |
|
|
case CYGNUM_HAL_INTERRUPT_IRQ_IRQ2:
|
| 432 |
|
|
ss <<= CYGARC_REG_ICR1_SENSE_IRQ2_shift;
|
| 433 |
|
|
mask <<= CYGARC_REG_ICR1_SENSE_IRQ2_shift;
|
| 434 |
|
|
break;
|
| 435 |
|
|
case CYGNUM_HAL_INTERRUPT_IRQ_IRQ1:
|
| 436 |
|
|
ss <<= CYGARC_REG_ICR1_SENSE_IRQ1_shift;
|
| 437 |
|
|
mask <<= CYGARC_REG_ICR1_SENSE_IRQ1_shift;
|
| 438 |
|
|
break;
|
| 439 |
|
|
case CYGNUM_HAL_INTERRUPT_IRQ_IRQ0:
|
| 440 |
|
|
ss <<= CYGARC_REG_ICR1_SENSE_IRQ0_shift;
|
| 441 |
|
|
mask <<= CYGARC_REG_ICR1_SENSE_IRQ0_shift;
|
| 442 |
|
|
break;
|
| 443 |
|
|
#endif
|
| 444 |
|
|
default:
|
| 445 |
|
|
CYG_FAIL("Unhandled interrupt vector");
|
| 446 |
|
|
}
|
| 447 |
|
|
|
| 448 |
|
|
HAL_READ_UINT16(CYGARC_REG_ICR1, icr1);
|
| 449 |
|
|
icr1 &= ~mask;
|
| 450 |
|
|
icr1 |= ss;
|
| 451 |
|
|
HAL_WRITE_UINT16(CYGARC_REG_ICR1, icr1);
|
| 452 |
|
|
}
|
| 453 |
|
|
#endif
|
| 454 |
|
|
|
| 455 |
|
|
CYGPRI_HAL_INTERRUPT_CONFIGURE_PLF(vector, level, up);
|
| 456 |
|
|
}
|
| 457 |
|
|
|
| 458 |
|
|
//---------------------------------------------------------------------------
|
| 459 |
|
|
// End of hal_misc.c
|
