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##==========================================================================
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##
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## variant.S
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##
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## SH3 variant assembly code
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##
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##==========================================================================
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## ####ECOSGPLCOPYRIGHTBEGIN####
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## -------------------------------------------
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## This file is part of eCos, the Embedded Configurable Operating System.
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## Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
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##
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## eCos is free software; you can redistribute it and/or modify it under
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## the terms of the GNU General Public License as published by the Free
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## Software Foundation; either version 2 or (at your option) any later
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## version.
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##
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## eCos is distributed in the hope that it will be useful, but WITHOUT
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## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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## for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with eCos; if not, write to the Free Software Foundation, Inc.,
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## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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##
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## As a special exception, if other files instantiate templates or use
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## macros or inline functions from this file, or you compile this file
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## and link it with other works to produce a work based on this file,
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## this file does not by itself cause the resulting work to be covered by
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## the GNU General Public License. However the source code for this file
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## must still be made available in accordance with section (3) of the GNU
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## General Public License v2.
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##
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## This exception does not invalidate any other reasons why a work based
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## on this file might be covered by the GNU General Public License.
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## -------------------------------------------
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## ####ECOSGPLCOPYRIGHTEND####
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##==========================================================================
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#######DESCRIPTIONBEGIN####
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##
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## Author(s): jskov
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## Contributors: jskov
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## Date: 2000-10-30
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## Purpose: SH3 misc assembly code
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######DESCRIPTIONEND####
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##
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##==========================================================================
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#include
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#include
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#include
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#include
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#include
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#---------------------------------------------------------------------------
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# Cache operations
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# These need to be written in assembly to ensure they do not rely on data
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# in cachable space (i.e., code must use registers exclusively, not the stack).
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# This macro must be used at the top of each cache function. It ensures
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# that the code gets executed from a shadow region where caching is disabled
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# (0xA0000000).
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.macro GOTO_NONCACHED_SHADOW
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mova 10f,r0
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mov.l $MASK,r1
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and r1,r0
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mov.l $BASE,r1
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or r1,r0
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jmp @r0
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nop
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.align 2
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10:
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.endm
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FUNC_START(cyg_hal_cache_enable)
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GOTO_NONCACHED_SHADOW
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mov #CYGARC_REG_CCR & 0x0FF,r1
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mov.l @r1,r0
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mov #CYGARC_REG_CCR_CE,r2
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or r2,r0
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mov.l r0,@r1
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nop
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rts
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nop
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FUNC_START(cyg_hal_cache_disable)
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GOTO_NONCACHED_SHADOW
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mov #CYGARC_REG_CCR & 0x0FF,r1
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mov.l @r1,r0
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mov #CYGARC_REG_CCR_CE,r2
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not r2,r2
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and r2,r0
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mov.l r0,@r1
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nop
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rts
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nop
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FUNC_START(cyg_hal_cache_invalidate_all)
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GOTO_NONCACHED_SHADOW
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mov #CYGARC_REG_CCR & 0x0FF,r1
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mov.l @r1,r0
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mov #CYGARC_REG_CCR_CF,r2
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or r2,r0
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mov.l r0,@r1
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nop ! Nothing in the docs suggest we need
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nop ! nops here, but without them, the
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nop ! CPU crashes.
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rts
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nop
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FUNC_START(cyg_hal_cache_sync)
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GOTO_NONCACHED_SHADOW
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mov.l $CYGARC_REG_CACHE_ADDRESS_FLUSH,r0
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mov.l $CYGARC_REG_CACHE_ADDRESS_BASE,r1
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mov.l $CYGARC_REG_CACHE_ADDRESS_TOP,r2
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mov.l $CYGARC_REG_CACHE_ADDRESS_STEP,r3
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1: cmp/hi r1,r2
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bf 2f
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mov.l r0,@r1
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bra 1b
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add r3,r1 ! delay slot!
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2: nop
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rts
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nop
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! r4 = base
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! r5 = size
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FUNC_START(cyg_hal_cache_sync_region)
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GOTO_NONCACHED_SHADOW
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mov.l 10f,r0
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and r4,r0 ! array index
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mov.l 11f,r1
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add r0,r1 ! base (aligned, A set)
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! make sure top is aligned to start of _next_ cache line
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mov r1,r0
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add r5,r0 ! top (non-aligned)
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add #2*HAL_UCACHE_LINE_SIZE-1,r0
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mov.l 13f,r2
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and r0,r2
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mov.l $CYGARC_REG_CACHE_ADDRESS_STEP,r3
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mov.l 12f,r5
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1: cmp/hi r1,r2
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bf 3f
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mov r4,r0 ! create address tag
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and r5,r0
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mov.l r0,@r1 ! store tag in array, causing (sync+)invalidate
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! if the tag matches any of the lines
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add r3,r4 ! inc address tag
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bra 1b
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add r3,r1 ! inc array index, delay slot!
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3: nop
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rts
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nop
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.align 2
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10: .long ((HAL_UCACHE_SIZE/HAL_UCACHE_WAYS)-1)&~0xf ! mask
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11: .long CYGARC_REG_CACHE_ADDRESS_BASE|CYGARC_REG_CACHE_ADDRESS_ADDRESS
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12: .long CYGARC_REG_CACHE_ADDRESS_TAG_Mask
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13: .long ~(HAL_UCACHE_LINE_SIZE-1)
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FUNC_START(cyg_hal_cache_write_mode)
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GOTO_NONCACHED_SHADOW
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# Mode argument in r4.
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# Read current state and mask out the two caching mode bits
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mov #CYGARC_REG_CCR & 0x0FF,r1
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mov.l @r1,r3
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mov #CYGARC_REG_CCR_CB|CYGARC_REG_CCR_WT,r2
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and r2,r4
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not r2,r2
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and r2,r3
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# Or in the new settings and restore to CCR
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or r4,r3
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mov.l r3,@r1
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nop
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rts
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nop
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.align 2
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$CYGARC_REG_CACHE_ADDRESS_FLUSH:
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.long CYGARC_REG_CACHE_ADDRESS_FLUSH
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$CYGARC_REG_CACHE_ADDRESS_BASE:
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.long CYGARC_REG_CACHE_ADDRESS_BASE
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$CYGARC_REG_CACHE_ADDRESS_TOP:
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.long CYGARC_REG_CACHE_ADDRESS_TOP
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$CYGARC_REG_CACHE_ADDRESS_STEP:
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.long CYGARC_REG_CACHE_ADDRESS_STEP
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$MASK:
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.long 0x1fffffff ! mask off top 3 bits
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$BASE:
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.long 0xa0000000 ! base of non-cachable memory
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.data
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SYM_DEF(cyg_hal_ILVL_table)
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# The first entries in the table have static priorities.
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.byte 0xf // NMI
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.byte 0xf // Reserved
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.byte 0xf // LVL0
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.byte 0xe // LVL1
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.byte 0xd // LVL2
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.byte 0xc // LVL3
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.byte 0xb // LVL4
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.byte 0xa // LVL5
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.byte 0x9 // LVL6
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.byte 0x8 // LVL7
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.byte 0x7 // LVL8
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.byte 0x6 // LVL9
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.byte 0x5 // LVL10
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.byte 0x4 // LVL11
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.byte 0x3 // LVL12
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.byte 0x2 // LVL13
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.byte 0x1 // LVL14
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.byte 0xf // Reserved
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# The rest of the table consists of programmable levels, maintained
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# by the HAL_INTERRUPT_SET_LEVEL macro.
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# These default to the highest level so that a spurious
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# interrupt cause the IPL to be suddenly lowered to allow all
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# interrupts. This should give a better chance at tracking down
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# the problem.
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.rept (CYGNUM_HAL_ISR_MAX-CYGNUM_HAL_INTERRUPT_RESERVED_3E0)
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.byte 0xf
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.endr
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# All interrupts are masked initally. Set to 1 to enable.
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SYM_DEF(cyg_hal_IMASK_table)
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.rept (CYGNUM_HAL_ISR_MAX)
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.byte 0x0
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.endr
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