OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [ecos-3.0/] [packages/] [hal/] [sh/] [sh4/] [current/] [include/] [mod_7750.h] - Blame information for rev 786

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 786 skrzyp
#ifndef CYGONCE_HAL_MOD_77xx_H
2
#define CYGONCE_HAL_MOD_77xx_H
3
 
4
//=============================================================================
5
//
6
//      mod_7750.h
7
//
8
//      List modules available on CPU
9
//
10
//=============================================================================
11
// ####ECOSGPLCOPYRIGHTBEGIN####                                            
12
// -------------------------------------------                              
13
// This file is part of eCos, the Embedded Configurable Operating System.   
14
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
15
//
16
// eCos is free software; you can redistribute it and/or modify it under    
17
// the terms of the GNU General Public License as published by the Free     
18
// Software Foundation; either version 2 or (at your option) any later      
19
// version.                                                                 
20
//
21
// eCos is distributed in the hope that it will be useful, but WITHOUT      
22
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
23
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
24
// for more details.                                                        
25
//
26
// You should have received a copy of the GNU General Public License        
27
// along with eCos; if not, write to the Free Software Foundation, Inc.,    
28
// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
29
//
30
// As a special exception, if other files instantiate templates or use      
31
// macros or inline functions from this file, or you compile this file      
32
// and link it with other works to produce a work based on this file,       
33
// this file does not by itself cause the resulting work to be covered by   
34
// the GNU General Public License. However the source code for this file    
35
// must still be made available in accordance with section (3) of the GNU   
36
// General Public License v2.                                               
37
//
38
// This exception does not invalidate any other reasons why a work based    
39
// on this file might be covered by the GNU General Public License.         
40
// -------------------------------------------                              
41
// ####ECOSGPLCOPYRIGHTEND####                                              
42
//=============================================================================
43
//#####DESCRIPTIONBEGIN####
44
//
45
// Author(s):   jskov
46
// Contributors:Haruki Kashiwaya
47
// Date:        2000-08-09
48
// Purpose:     Define modules (and versions) available on this CPU.
49
// Usage:       Included from <cyg/hal/sh_regs.h>
50
//
51
//              
52
//####DESCRIPTIONEND####
53
//
54
//=============================================================================
55
 
56
//-----------------------------------------------------------------------------
57
// Modules provided by the CPU
58
 
59
#define CYGARC_SH_MOD_CPG  1
60
#define CYGARC_SH_MOD_SCIF 1
61
//#define CYGARC_SH_MOD_UBC  1
62
#define CYGARC_SH_MOD_INTC 1
63
 
64
 
65
//-----------------------------------------------------------------------------
66
// Extra details for Cache Module (CAC)
67
 
68
//=============================================================================
69
// Icache
70
// Cache dimenions
71
#define CYGARC_SH_MOD_CAC_I_SIZE        8192  // Size of cache in bytes
72
#define CYGARC_SH_MOD_CAC_I_LINE_SIZE   32    // Size of a cache line
73
#define CYGARC_SH_MOD_CAC_I_WAYS        1     // Associativity of the cache
74
 
75
// Cache addressing information
76
// entry: bits 12 -  5
77
#define CYGARC_SH_MOD_ICAC_ADDRESS_BASE   0xf0000000
78
#define CYGARC_SH_MOD_ICAC_ADDRESS_TOP    0xf0002000
79
#define CYGARC_SH_MOD_ICAC_ADDRESS_STEP   0x00000020
80
// V : bit 0
81
// Writing zero to V forces an invalidate of the line
82
#define CYGARC_SH_MOD_ICAC_ADDRESS_FLUSH  0x00000000
83
 
84
 
85
//=============================================================================
86
// Dcache
87
// Cache dimenions
88
#define CYGARC_SH_MOD_CAC_D_SIZE        16384 // Size of cache in bytes
89
#define CYGARC_SH_MOD_CAC_D_LINE_SIZE   32    // Size of a cache line
90
#define CYGARC_SH_MOD_CAC_D_WAYS        1     // Associativity of the cache
91
 
92
// Cache addressing information
93
// entry: bits 13 -  5
94
#define CYGARC_SH_MOD_DCAC_ADDRESS_BASE   0xf4000000
95
#define CYGARC_SH_MOD_DCAC_ADDRESS_TOP    0xf4004000
96
#define CYGARC_SH_MOD_DCAC_ADDRESS_STEP   0x00000020
97
// U : bit 1
98
// V : bit 0
99
// Writing zero to both forces a flush of the line if it is dirty.
100
#define CYGARC_SH_MOD_DCAC_ADDRESS_FLUSH  0x00000000
101
 
102
//-----------------------------------------------------------------------------
103
// Extra details for interrupt handling
104
#define CYGARC_SH_SOFTWARE_IP_UPDATE
105
 
106
#endif // CYGONCE_HAL_MOD_77xx_H

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.