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//=============================================================================
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//
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// mod_regs_bsc.h
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//
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// BSC (bus state controller) Module register definitions
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//
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//=============================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later
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// version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
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// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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//
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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//=============================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): jskov
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// Contributors:jskov
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// Date: 2000-10-30
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//
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//####DESCRIPTIONEND####
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//
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//=============================================================================
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//--------------------------------------------------------------------------
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// Register definitions
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#define CYGARC_REG_BCR1 0xFF800000
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#define CYGARC_REG_BCR2 0xFF800004
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#define CYGARC_REG_WCR1 0xFF800008
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#define CYGARC_REG_WCR2 0xFF80000C
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#define CYGARC_REG_WCR3 0xFF800010
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#define CYGARC_REG_MCR 0xFF800014
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#define CYGARC_REG_PCR 0xFF800018
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#define CYGARC_REG_RTCSR 0xFF80001C
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#define CYGARC_REG_RTCNT 0xFF800020
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#define CYGARC_REG_RTCOR 0xFF800024
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#define CYGARC_REG_RFCR 0xFF800028
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#define CYGARC_REG_PCTRA 0xFF80002c
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#define CYGARC_REG_PDTRA 0xFF800030
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#define CYGARC_REG_PCTRB 0xFF800040
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#define CYGARC_REG_PDTRB 0xFF800044
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#define CYGARC_REG_GPIOIC 0xFF800048
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#define CYGARC_REG_SDMR_AREA2_BASE 0xff900000
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#define CYGARC_REG_SDMR_AREA3_BASE 0xff940000
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#define CYGARC_REG_BCR1_MASTER 0x40000000
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#define CYGARC_REG_MCR_RASD 0x80000000
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#define CYGARC_REG_MCR_MRSET 0x40000000
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#define CYGARC_REG_MCR_TCAS 0x00800000
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#define CYGARC_REG_MCR_BE 0x00000100
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#define CYGARC_REG_MCR_RFSH 0x00000004
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#define CYGARC_REG_MCR_RMODE 0x00000002
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#define CYGARC_REG_MCR_EDO_MODE 0x00000001
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//-----------------------------------------------------------------------------
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// Calculate constants needed to drive the proper SDRAM refresh rate. Argument
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// is delay between required refresh events in microseconds (us). Should be
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// available off the SDRAM spec sheet.
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// These should be a part of a fully CDLicized memory controller setup.
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#define CYGARC_RTCSR_PRESCALE(_r_) \
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(((CYGHWR_HAL_SH_BOARD_SPEED*(_r_)/(4*1000000))<256) ? 4 : \
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((CYGHWR_HAL_SH_BOARD_SPEED*(_r_)/(16*1000000))<256) ? 16 : \
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((CYGHWR_HAL_SH_BOARD_SPEED*(_r_)/(64*1000000))<256) ? 64 : \
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((CYGHWR_HAL_SH_BOARD_SPEED*(_r_)/(256*1000000))<256) ? 256 : \
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((CYGHWR_HAL_SH_BOARD_SPEED*(_r_)/(1024*1000000))<256) ? 1024 : \
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((CYGHWR_HAL_SH_BOARD_SPEED*(_r_)/(2048*1000000))<256) ? 2048 : 4096)
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// These two macros provide the static values we need to stuff into the
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// registers.
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#define CYGARC_RTCSR_CKSx(_r_) \
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(( 4 == CYGARC_RTCSR_PRESCALE(_r_)) ? 0x08 : \
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( 16 == CYGARC_RTCSR_PRESCALE(_r_)) ? 0x10 : \
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( 64 == CYGARC_RTCSR_PRESCALE(_r_)) ? 0x18 : \
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( 256 == CYGARC_RTCSR_PRESCALE(_r_)) ? 0x20 : \
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(1024 == CYGARC_RTCSR_PRESCALE(_r_)) ? 0x28 : \
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(2048 == CYGARC_RTCSR_PRESCALE(_r_)) ? 0x30 : 0x38 )
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#define CYGARC_RTCSR_N(_r_) \
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(CYGHWR_HAL_SH_BOARD_SPEED*(_r_)/(CYGARC_RTCSR_PRESCALE(_r_)*1000000))
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