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skrzyp |
#ifndef CYGONCE_HAL_PLATFORM_INC
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#define CYGONCE_HAL_PLATFORM_INC
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##=============================================================================
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##
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## platform.inc
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##
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## SuperH SH4-202 MicroDev CPU board assembler header file
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##
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##=============================================================================
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## ####ECOSGPLCOPYRIGHTBEGIN####
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## -------------------------------------------
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## This file is part of eCos, the Embedded Configurable Operating System.
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## Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
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##
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## eCos is free software; you can redistribute it and/or modify it under
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## the terms of the GNU General Public License as published by the Free
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## Software Foundation; either version 2 or (at your option) any later
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## version.
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##
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## eCos is distributed in the hope that it will be useful, but WITHOUT
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## ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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## for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with eCos; if not, write to the Free Software Foundation, Inc.,
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## 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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##
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## As a special exception, if other files instantiate templates or use
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## macros or inline functions from this file, or you compile this file
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## and link it with other works to produce a work based on this file,
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## this file does not by itself cause the resulting work to be covered by
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## the GNU General Public License. However the source code for this file
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## must still be made available in accordance with section (3) of the GNU
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## General Public License v2.
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##
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## This exception does not invalidate any other reasons why a work based
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## on this file might be covered by the GNU General Public License.
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## -------------------------------------------
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## ####ECOSGPLCOPYRIGHTEND####
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##=============================================================================
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#######DESCRIPTIONBEGIN####
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##
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## Author(s): jskov, nickg
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## Contributors:jskov, nickg
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## Date: 2003-08-20
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## Purpose: SuperH SH4-202 MicroDev CPU platform startup
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## Description: This file contains various definitions and macros that are
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## useful for writing assembly code for the SuperH SH4-202
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## MicroDev CPU board.
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## Usage:
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## #include
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## ...
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##
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##
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######DESCRIPTIONEND####
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##
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##=============================================================================
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#include
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#include
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#include
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#------------------------------------------------------------------------------
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# Hardware initialization.
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#define END 0
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#define INT8 1
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#define INT16 2
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#define INT32 3
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#define DELAY 4
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#define SPIN 5
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.macro hal_hardware_init
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mova init_table,r0
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mov r0,r3
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1: mov.l @r3+,r0 // Data type
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cmp/eq #END,r0 // End of table
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bf 0f
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bra 9f
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nop
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0: cmp/eq #INT8,r0
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bf 2f
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// 8 bit data
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mov.l @r3+,r0 // addr
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mov.l @r3+,r1 // data
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bra 1b
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mov.b r1,@r0
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2: cmp/eq #INT16,r0
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bf 3f
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// 16 bit data
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mov.l @r3+,r0 // addr
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mov.l @r3+,r1 // data
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bra 1b
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mov.w r1,@r0
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3: cmp/eq #INT32,r0
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bf 4f
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// 32 bit data
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mov.l @r3+,r0 // addr
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mov.l @r3+,r1 // data
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bra 1b
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mov.l r1,@r0
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4: cmp/eq #DELAY,r0
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bf 6f
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// delay
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mov.l @r3+,r0 // count
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5: cmp/eq #0,r0
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bt 1b
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bra 5b
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add #-1,r0
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6: cmp/eq #SPIN,r0
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bf 8f
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// delay
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mov.l @r3+,r0 // ID
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mov #0,r0
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7: cmp/eq #0,r0
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bt 1b
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bra 7b
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nop
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8: bra 1b
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nop
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.align 2
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init_table:
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# Clock setup
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.long INT16, CYGARC_REG_WTCSR, 0xA567
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.long INT16, CYGARC_REG_WTCNT, 0x5A00
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.long INT16, CYGARC_REG_FRQCR, CYGARC_REG_FRQCR_INIT
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.long INT32, CYGARC_REG_FRQCR3, 0x006a
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# FEMI setup
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#if 0
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# We rely on the FPGA to set up FEMI area 0
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.long INT32, CYGARC_REG_FEMI_A0MCR, 0x0b777138
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#endif
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.long INT32, CYGARC_REG_FEMI_A1MCR, 0x0b777108
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.long INT32, CYGARC_REG_FEMI_A2MCR, 0x03777510
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.long INT32, CYGARC_REG_FEMI_A3MCR, 0x0b777110
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.long INT32, CYGARC_REG_FEMI_A4MCR, 0x0b777108
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#ifndef CYG_HAL_STARTUP_RAM
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# EMI setup
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.long SPIN, 0xA5A50000
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.long INT32, CYGARC_REG_EMI_COC, 0x00000010
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.long DELAY, 10000
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.long SPIN, 0xA5A50001
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.long INT32, CYGARC_REG_EMI_MIM, 0x00000021
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.long SPIN, 0xA5A50002
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.long INT32, CYGARC_REG_EMI_STR, 0x0000116b
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.long SPIN, 0xA5A50003
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.long INT32, CYGARC_REG_EMI_SDRA0, 0x0a001900
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.long SPIN, 0xA5A50004
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.long INT32, CYGARC_REG_EMI_SDRA1, 0x0c001900
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.long SPIN, 0xA5A50005
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.long INT32, CYGARC_REG_EMI_SCR, 0x00000003
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.long SPIN, 0xA5A50006
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.long DELAY, 10000
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.long SPIN, 0xA5A50007
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.long INT32, CYGARC_REG_EMI_SCR, 0x00000002
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.long INT32, CYGARC_REG_EMI_SCR, 0x00000004
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.long INT32, CYGARC_REG_EMI_SCR, 0x00000004
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.long INT32, CYGARC_REG_EMI_SCR, 0x00000004
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.long INT32, CYGARC_REG_EMI_SCR, 0x00000004
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.long INT32, CYGARC_REG_EMI_SCR, 0x00000004
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.long INT32, CYGARC_REG_EMI_SCR, 0x00000004
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.long INT32, CYGARC_REG_EMI_SCR, 0x00000004
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.long INT32, CYGARC_REG_EMI_SCR, 0x00000004
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.long SPIN, 0xA5A50008
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.long INT32, CYGARC_REG_EMI_SDMR0+0x110, 0xffffffff
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.long SPIN, 0xA5A50009
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.long INT32, CYGARC_REG_EMI_SDMR1+0x110, 0xffffffff
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.long SPIN, 0xA5A5000a
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.long INT32, CYGARC_REG_EMI_MIM, 0x00900281
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.long SPIN, 0xA5A5000b
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.long INT32, CYGARC_REG_EMI_SCR, 0x00000000
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.long SPIN, 0xA5A5000c
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#endif
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.long END
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9:
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.endm
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#------------------------------------------------------------------------------
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# Monitor initialization.
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#ifndef CYGPKG_HAL_SH_MON_DEFINED
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#if !defined(CYG_HAL_STARTUP_RAM) || \
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( defined(CYG_HAL_STARTUP_RAM) && \
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!defined(CYGSEM_HAL_USE_ROM_MONITOR))
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# If we are not starting up from RAM, or we are starting in
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# RAM and NOT using a ROM monitor, initialize the VSR table.
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.macro hal_mon_init
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mov.l $hal_vsr_table,r3
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# Write exception vectors
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mov.l $cyg_hal_default_exception_vsr,r4
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mov #CYGNUM_HAL_VSR_EXCEPTION_COUNT,r5
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1: mov.l r4,@r3
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add #4,r3
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dt r5
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bf 1b
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# Write interrupt vector
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mov.l $cyg_hal_default_interrupt_vsr,r4
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mov.l $hal_vsr_table,r3
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add #CYGNUM_HAL_VECTOR_INTERRUPT*4,r3
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mov.l r4,@r3
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bra 2f
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nop
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.align 2
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SYM_PTR_REF(cyg_hal_default_exception_vsr)
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SYM_PTR_REF(cyg_hal_default_interrupt_vsr)
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SYM_PTR_REF(hal_vsr_table)
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2:
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.endm
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#elif defined(CYG_HAL_STARTUP_RAM) && defined(CYGSEM_HAL_USE_ROM_MONITOR)
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# Initialize the VSR table entries
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# We only take control of the interrupt vector,
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# the rest are left to the ROM for now...
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.macro hal_mon_init
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# Write interrupt vector
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mov.l $hal_vsr_table,r3
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mov.l $cyg_hal_default_interrupt_vsr,r4
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add #CYGNUM_HAL_VECTOR_INTERRUPT*4,r3
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mov.l r4,@r3
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bra 2f
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nop
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.align 2
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SYM_PTR_REF(cyg_hal_default_interrupt_vsr)
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SYM_PTR_REF(hal_vsr_table)
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2:
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.endm
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#else
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.macro hal_mon_init
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.endm
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#endif
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#define CYGPKG_HAL_SH_MON_DEFINED
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#endif // CYGPKG_HAL_SH_MON_DEFINED
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#endif // CYGONCE_HAL_PLATFORM_INC
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