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[/] [openrisc/] [trunk/] [rtos/] [ecos-3.0/] [packages/] [hal/] [sh/] [sh4_202_md/] [current/] [include/] [plf_intr.h] - Blame information for rev 867

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1 786 skrzyp
#ifndef CYGONCE_HAL_PLF_INTR_H
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#define CYGONCE_HAL_PLF_INTR_H
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//==========================================================================
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//
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//      plf_intr.h
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//
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//      Platform specific Interrupt and clock support
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//
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//==========================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####                                            
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// -------------------------------------------                              
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// This file is part of eCos, the Embedded Configurable Operating System.   
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// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under    
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// the terms of the GNU General Public License as published by the Free     
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// Software Foundation; either version 2 or (at your option) any later      
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// version.                                                                 
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT      
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or    
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License    
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// for more details.                                                        
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//
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// You should have received a copy of the GNU General Public License        
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// along with eCos; if not, write to the Free Software Foundation, Inc.,    
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// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.            
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//
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// As a special exception, if other files instantiate templates or use      
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// macros or inline functions from this file, or you compile this file      
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// and link it with other works to produce a work based on this file,       
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// this file does not by itself cause the resulting work to be covered by   
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// the GNU General Public License. However the source code for this file    
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// must still be made available in accordance with section (3) of the GNU   
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// General Public License v2.                                               
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//
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// This exception does not invalidate any other reasons why a work based    
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// on this file might be covered by the GNU General Public License.         
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// -------------------------------------------                              
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// ####ECOSGPLCOPYRIGHTEND####                                              
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//==========================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s):    nickg
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// Contributors: nickg
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// Date:         2003-08-20
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// Purpose:      Define Interrupt support
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// Description:  The macros defined here provide the HAL APIs for handling
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//               interrupts and the clock for the SuperH SH4-202 MicroDev
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//               CPU board.
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// Usage:
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//               #include <cyg/hal/plf_intr.h>
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//               ...
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//              
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//
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//####DESCRIPTIONEND####
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//
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//==========================================================================
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#include <pkgconf/hal.h>
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//----------------------------------------------------------------------------
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// External interrupts.
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#define CYGNUM_HAL_INTERRUPT_ETH           CYGNUM_HAL_INTERRUPT_LVL3
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//----------------------------------------------------------------------------
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// FPGA Interrupt controller
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#define FPGA_INTC_BASE          0xA6110000ul                    /* INTC base address on CPU-board FPGA */
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#define FPGA_INTENB_REG         (FPGA_INTC_BASE+0ul)            /* Interrupt Enable Register on INTC on CPU-board FPGA */
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#define FPGA_INTDSB_REG         (FPGA_INTC_BASE+8ul)            /* Interrupt Disable Register on INTC on CPU-board FPGA */
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#define FPGA_INTENB_MASK(n)     (1ul<<(n))                      /* Interupt mask to enable Ethernet on INTC in CPU-board FPGA */
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#define FPGA_INTPRI_REG(n)      (FPGA_INTC_BASE+0x10+((n)/8)*8) /* Interrupt Priority Register on INTC on CPU-board FPGA */
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#define FPGA_INTPRI_LEVEL(n,x)  ((x)<<(((n)%8)*4))              /* FPGA_INTPRI_LEVEL(int_number, int_level) */
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#define FPGA_INTPRI_MASK(n)     (FPGA_INTPRI_LEVEL((n),0xful))  /* Interrupt Priority Mask on INTC on CPU-board FPGA */
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#define FPGA_ETHERNET_INT       (18)                            /* Interrupt number for Ethernet in INTC on CPU-board FPGA */
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#define ETHERNET_INT_PRIORITY   (0xc)                           /* Interrupt Priority of Ethenet IRQ */
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//----------------------------------------------------------------------------
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// Interrupt configuration extension macros
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#define CYGPRI_HAL_INTERRUPT_UPDATE_LEVEL_PLF(vec, level)                               \
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    case CYGNUM_HAL_INTERRUPT_ETH:                                                      \
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        {                                                                               \
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            volatile cyg_uint32* const intEnableReg = (cyg_uint32*)FPGA_INTENB_REG;     \
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            volatile cyg_uint32* const intDisableReg = (cyg_uint32*)FPGA_INTDSB_REG;    \
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                                                                                        \
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            if( level )                                                                 \
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                *intEnableReg |= FPGA_INTENB_MASK(FPGA_ETHERNET_INT);                   \
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            else                                                                        \
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                *intDisableReg |= FPGA_INTENB_MASK(FPGA_ETHERNET_INT);                  \
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        }                                                                               \
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        break;                                                                          \
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    case CYGNUM_HAL_INTERRUPT_NMI:                                                      \
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        /* fall through */                                                              \
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    case CYGNUM_HAL_INTERRUPT_LVL0 ... CYGNUM_HAL_INTERRUPT_LVL2:                       \
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        /* fall through */                                                              \
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    case CYGNUM_HAL_INTERRUPT_LVL4 ... CYGNUM_HAL_INTERRUPT_LVL14:                      \
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        /* Cannot change levels */                                                      \
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        break;
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//----------------------------------------------------------------------------
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// Reset.
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// Block interrupts and cause an exception. This forces a reset.
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#define HAL_PLATFORM_RESET() \
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    asm volatile ("ldc %0,sr;trapa #0x00;" : : "r" (CYGARC_REG_SR_BL))
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#define HAL_PLATFORM_RESET_ENTRY 0x80000000
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//--------------------------------------------------------------------------
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#endif // ifndef CYGONCE_HAL_PLF_INTR_H
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// End of plf_intr.h

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