OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [ecos-3.0/] [packages/] [hal/] [sparc/] [erc32/] [current/] [include/] [halboot.si] - Blame information for rev 786

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 786 skrzyp
#ifndef CYGONCE_HAL_HALBOOT_SI /* -*-asm-*- */
2
#define CYGONCE_HAL_HALBOOT_SI
3
// ====================================================================
4
//
5
//      /halboot.si
6
//
7
//      HAL bootup platform-oriented code (assembler)
8
//
9
// ====================================================================
10
// ####ECOSGPLCOPYRIGHTBEGIN####
11
// -------------------------------------------
12
// This file is part of eCos, the Embedded Configurable Operating System.
13
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
14
//
15
// eCos is free software; you can redistribute it and/or modify it under
16
// the terms of the GNU General Public License as published by the Free
17
// Software Foundation; either version 2 or (at your option) any later
18
// version.
19
//
20
// eCos is distributed in the hope that it will be useful, but WITHOUT
21
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
22
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
23
// for more details.
24
//
25
// You should have received a copy of the GNU General Public License
26
// along with eCos; if not, write to the Free Software Foundation, Inc.,
27
// 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
28
//
29
// As a special exception, if other files instantiate templates or use
30
// macros or inline functions from this file, or you compile this file
31
// and link it with other works to produce a work based on this file,
32
// this file does not by itself cause the resulting work to be covered by
33
// the GNU General Public License. However the source code for this file
34
// must still be made available in accordance with section (3) of the GNU
35
// General Public License v2.
36
//
37
// This exception does not invalidate any other reasons why a work based
38
// on this file might be covered by the GNU General Public License.
39
// -------------------------------------------
40
// ####ECOSGPLCOPYRIGHTEND####
41
// ====================================================================
42
//#####DESCRIPTIONBEGIN####
43
//
44
// Author(s):           hmt
45
// Contributors:        hmt
46
// Date:                1999-02-01
47
// Purpose:             Bootup code, platform oriented.
48
// Description:
49
//
50
//####DESCRIPTIONEND####
51
//
52
// ====================================================================
53
 
54
// External Platform Initial Setup
55
//
56
// This should set up RAM and caches, and calm down any external
57
// interrupt sources.
58
//
59
// It is just plain included in vectors.S
60
//
61
// RAM has not yet been touched at all; in fact all you have is a
62
// register window selected.
63
 
64
 
65
        ! Empty macro for debugging vectors.S
66
        .macro led val
67
        .endm
68
 
69
 
70
        set     0x01f80000, %l0         ! MEC register base address
71
        ld      [%l0], %l1              ! Check if MEC has been initialised
72
        set     0xfe080000, %l2         ! by checking baud rate register
73
        andcc   %l2, %l1, %g0
74
        bne     2f                      ! skip
75
        nop
76
 
77
        ! Set memory according to simulator config
78
 
79
        st      %g0, [%l0 + 0x64]       ! Disable watchdog for now
80
        ld      [%l0], %g1
81
        or      %g1, 1, %g1
82
        st      %g1, [%l0]              ! Enable power down
83
        st      %g0, [%l0 + 0x18]       ! No waitstates
84
        ld      [%l0 + 0xF8], %g1       ! load simulator rom size
85
        clr     %l2
86
        srl     %g1, 17, %g1            ! calculate appropriate MEC rom size
87
1:
88
        srl     %g1, 1, %g1
89
        tst     %g1
90
        bne,a   1b
91
        inc     %l2
92
        sll     %l2, 8, %l2
93
        ld      [%l0 + 0xF4], %g2       ! load simulator ram size
94
        srl     %g2, 18, %g1            ! calculate appropriate MEC ram size
95
1:
96
        srl     %g1, 1, %g1
97
        tst     %g1
98
        bne,a   1b
99
        inc     %l2
100
        sll     %l2, 10, %l2
101
        st      %l2, [%l0 + 0x10]       ! program MEC memory config register
102
        set     0x2000000, %l2
103
        add     %g2, %l2, %fp
104
        sub     %fp, 96*4, %sp
105
 
106
!       st      %g0, [%sp]              ! probe for FPU
107
!       ld      [%sp], %fsr
108
 
109
        set     13, %l1
110
        st      %l1, [%l0 + 0x84]       ! RTC scaler = 13
111
 
112
2:
113
        set     reset_vector, %g1
114
        set     0x0d00, %l1
115
        st      %l1, [%g1 + 0x7c0]      ! Store TCR mirror
116
        st      %l1, [%l0 + 0x98]       ! Start RTC
117
        mov     %g3, %o7
118
 
119
 
120
4:
121
        ! then copy the branch instructions into the vector
122
        rd      %tbr, %g1
123
        andn    %g1, 0xfff, %g1         ! clear non-address bits
124
        sethi   %hi(real_vector_instructions), %l0
125
        or      %l0, %lo(real_vector_instructions), %l0
126
        ld      [ %l0 ], %l1
127
        st      %l1, [ %g1 ]            ! into the vector
128
        ld      [ %l0 + 4 ], %l1
129
        st      %l1, [ %g1 + 4 ]        ! into the vector
130
 
131
#endif  /* CYGONCE_HAL_HALBOOT_SI */
132
/* EOF halboot.si */

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.