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skrzyp |
#ifndef CYGONCE_HAL_XPIC_H
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#define CYGONCE_HAL_XPIC_H
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//=============================================================================
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//
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// hal_xpic.h
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//
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// HAL eXternal Programmable Interrupt Controller support
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//
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//=============================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later
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// version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
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// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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//
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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//=============================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): nickg, gthomas, hmt
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// Contributors: nickg, gthomas, hmt
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// Date: 1999-01-28
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// Purpose: Define Interrupt support
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// Description: The macros defined here provide the HAL APIs for handling
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// an external interrupt controller, and which interrupt is
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// used for what.
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//
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// Usage:
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// #include <cyg/hal/hal_intr.h> // which includes this file
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// ...
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//
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//
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//####DESCRIPTIONEND####
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//
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//=============================================================================
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#include <cyg/hal/hal_hwio.h> // HAL_SPARC_86940_READ/WRITE
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//-----------------------------------------------------------------------------
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// Interrupt controller access
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//
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// In the Fuitsu SPARClite Evaluation Boards, when the external IRC (86940)
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// is used (set Switch 1, position 8 (SW1#8)), interrupts are as follows:
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//
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// 15 : NMI Push Switch (SW7)
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// 14 : N_INT# Ethernet LAN Controller (MB86964)
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// 13 : EX_IRQ13 from expansion board, active HIGH
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// 12 : EX_IRQ12 from expansion board, active LOW
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// 11 : EX_IRQ11 from expansion board, active LOW
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// 10 : RRDY0 Serial CH0 receive ready signal
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// 9 : TRDY0 Serial CH0 transmit ready signal
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// 8 : TIMER1 Timer 1 output counter
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// 7 : RRDY1 Serial CH1 receive ready signal
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// 6 : TRDY1 Serial CH1 transmit ready signal
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// 5 : EX_IRQ5 from expansion board, active LOW
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// 4 : EX_IRQ4 from expansion board, active LOW
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// 3 : EX_IRQ3 from expansion board, active HIGH
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// 2 : EX_IRQ2 from expansion board, active LOW
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// 1 : TIMER2 Timer 2 output counter
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// The vector used by the Real time clock
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//#define CYG_VECTOR_RTC CYG_VECTOR_INTERRUPT_8
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#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_VECTOR_INTERRUPT_8
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#define HAL_SPARC_86940_REG_IRC_TRGM0 ( 0 * 4 )
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#define HAL_SPARC_86940_REG_IRC_TRGM1 ( 1 * 4 )
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#define HAL_SPARC_86940_REG_IRC_RQSNS ( 2 * 4 )
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#define HAL_SPARC_86940_REG_IRC_RQCLR ( 3 * 4 )
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#define HAL_SPARC_86940_REG_IRC_IMASK ( 4 * 4 )
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#define HAL_SPARC_86940_REG_IRC_CLIRL ( 5 * 4 )
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#define HAL_SPARC_86940_FLAG_CLIRL_CL (0x10)
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#define HAL_SPARC_86940_IRC_IMASK_READ( r ) \
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HAL_SPARC_86940_READ( HAL_SPARC_86940_REG_IRC_IMASK, r )
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#define HAL_SPARC_86940_IRC_IMASK_WRITE( v ) \
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HAL_SPARC_86940_WRITE( HAL_SPARC_86940_REG_IRC_IMASK, v )
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#define HAL_SPARC_86940_IRC_RQSNS_READ( r ) \
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HAL_SPARC_86940_READ( HAL_SPARC_86940_REG_IRC_RQSNS, r )
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#define HAL_SPARC_86940_IRC_RQCLR_WRITE( v ) \
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HAL_SPARC_86940_WRITE( HAL_SPARC_86940_REG_IRC_RQCLR, v )
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#define HAL_SPARC_86940_IRC_CLIRL_READ( r ) \
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HAL_SPARC_86940_READ( HAL_SPARC_86940_REG_IRC_CLIRL, r )
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#define HAL_SPARC_86940_IRC_CLIRL_WRITE( v ) \
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HAL_SPARC_86940_WRITE( HAL_SPARC_86940_REG_IRC_CLIRL, v )
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//-----------------------------------------------------------------------------
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#define HAL_INTERRUPT_MASK( _vector_ ) CYG_MACRO_START \
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cyg_uint32 _traps_, _mask_; \
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HAL_DISABLE_TRAPS( _traps_ ); \
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HAL_SPARC_86940_IRC_IMASK_READ( _mask_ ); \
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_mask_ |= (1 << (_vector_) ); \
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HAL_SPARC_86940_IRC_IMASK_WRITE( _mask_ ); \
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HAL_SPARC_86940_IRC_RQCLR_WRITE( (1 << (_vector_) ) ); \
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HAL_SPARC_86940_IRC_CLIRL_WRITE( HAL_SPARC_86940_FLAG_CLIRL_CL ); \
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HAL_RESTORE_INTERRUPTS( _traps_ ); \
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CYG_MACRO_END
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#define HAL_INTERRUPT_UNMASK( _vector_ ) CYG_MACRO_START \
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cyg_uint32 _traps_, _mask_; \
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HAL_DISABLE_TRAPS( _traps_ ); \
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HAL_SPARC_86940_IRC_IMASK_READ( _mask_ ); \
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_mask_ &=~ (1 << (_vector_) ); \
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HAL_SPARC_86940_IRC_IMASK_WRITE( _mask_ ); \
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HAL_RESTORE_INTERRUPTS( _traps_ ); \
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CYG_MACRO_END
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#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) CYG_MACRO_START \
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cyg_uint32 _traps_; \
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cyg_uint32 _req_, _irl_; \
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HAL_DISABLE_TRAPS( _traps_ ); \
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HAL_SPARC_86940_IRC_RQCLR_WRITE( (1 << (_vector_) ) ); \
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do { \
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HAL_SPARC_86940_IRC_CLIRL_WRITE( HAL_SPARC_86940_FLAG_CLIRL_CL ); \
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HAL_SPARC_86940_IRC_RQSNS_READ( _req_ ); \
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HAL_SPARC_86940_IRC_CLIRL_READ( _irl_ ); \
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_req_ &= (1 << (_vector_)); /* if there really is a new intr */ \
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_irl_ &= 0x0f; /* then get out - else poll until */ \
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} while ( (!_req_) && (_irl_ == (_vector_)) ); /* no intr here */ \
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HAL_RESTORE_INTERRUPTS( _traps_ ); \
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CYG_MACRO_END
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// Set an interrupt source's sensitivity:
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// _level_ != 0 ? level-sensitive : edge-sensitive
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// _up_ != 0 ? high/up : low/down
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// SPARClite's 86940 has values as follows:
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// 0 : high level
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// 1 : low level
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// 2 : rising edge
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// 3 : falling edge
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// TRGM0 controls sources 15-8, TRGM1 sources 7-1.
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#define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ ) CYG_MACRO_START \
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int _reg_ = (8 > (_vector_)) ? HAL_SPARC_86940_REG_IRC_TRGM1 \
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: HAL_SPARC_86940_REG_IRC_TRGM0; \
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int _val_, _myvect_ = (_vector_); \
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cyg_uint32 _traps_; \
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HAL_DISABLE_TRAPS( _traps_ ); \
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(_myvect_) &= 7; \
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(_myvect_) <<= 1; \
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HAL_SPARC_86940_READ( _reg_, _val_ ); \
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_val_ &=~ (3 << (_myvect_)); \
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_val_ |= ( ((_level_) ? 0 : 2) + ((_up_) ? 0 : 1) ) << (_myvect_); \
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HAL_SPARC_86940_WRITE( _reg_, _val_ ); \
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HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ); \
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HAL_RESTORE_INTERRUPTS( _traps_ ); \
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CYG_MACRO_END
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// This is not a standard macro - platform dependent for debugging only:
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// o level, up tell you how this source was configured as above.
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// o hipri returns the number of the highest prio requesting interrupt
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// o mask tells you whether this source is masked off
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// o req tells you whether this source is requesting right now.
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#define HAL_INTERRUPT_QUERY_INFO( _vector_, _level_, _up_, \
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_hipri_, _mask_, _req_ ) CYG_MACRO_START \
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int _reg_ = (8 > (_vector_)) ? HAL_SPARC_86940_REG_IRC_TRGM1 \
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: HAL_SPARC_86940_REG_IRC_TRGM0; \
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int _val_, _myvect_ = (_vector_); \
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HAL_SPARC_86940_IRC_IMASK_READ( _val_ ); \
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_mask_ = (0 != ((1 << (_vector_)) & _val_ )); \
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HAL_SPARC_86940_IRC_RQSNS_READ( _val_ ); \
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_req_ = (0 != ((1 << (_vector_)) & _val_ )); \
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HAL_SPARC_86940_IRC_CLIRL_READ( _hipri_ ); \
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(_myvect_) &= 7; \
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(_myvect_) <<= 1; \
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HAL_SPARC_86940_READ( _reg_, _val_ ); \
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_val_ >>= (_myvect_); \
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(_level_) = !(_val_ & 2); \
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(_up_) = !(_val_ & 1); \
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CYG_MACRO_END
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// This may set the priority of a vector to a particular level:
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// SPARClite does not support this.
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#define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ ) /* nothing */
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//-----------------------------------------------------------------------------
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#endif // ifndef CYGONCE_HAL_XPIC_H
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// End of hal_xpic.h
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