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skrzyp |
#ifndef CYGONCE_HAL_HAL_INTR_H
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#define CYGONCE_HAL_HAL_INTR_H
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//==========================================================================
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//
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// hal_intr.h
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//
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// HAL Interrupt and clock support
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//
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//==========================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later
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// version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
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// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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//
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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//==========================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): proven
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// Contributors: proven, jskov, pjo, nickg, bartv
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// Date: 1999-02-20
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// Purpose: Define Interrupt support
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// Description: The macros defined here provide the HAL APIs for handling
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// interrupts and the clock.
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//
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// Usage:
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// #include <cyg/hal/hal_intr.h>
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// ...
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//
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//####DESCRIPTIONEND####
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//
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//==========================================================================
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// Interrupt and exception handling in the synthetic target is very much
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// tied up with POSIX signal handling.
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//
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// There are two interrupt sources to consider. The system clock is
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// provided most conveniently by a timer signal SIGALRM. All other
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// interrupts are handled by communication with the auxiliary program
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// and involve SIGIO. The model that is actually presented to
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// higher-level code is a single VSR, and 32 ISRs. ISR 0 is
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// arbitrarily assigned to the clock. The remaining 31 ISRs correspond
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// to devices managed through the auxiliary, effectively providing an
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// interrupt controller. A single VSR suffices because it is passed
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// the signal number as argument.
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//
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// Exceptions also correspond to signals, but are not handled through
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// the same VSR: slightly different processing is needed for
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// interrupts vs. exceptions, for example the latter does not involve
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// calling interrupt_end(). The exceptions of interest are SIGILL,
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// SIGBUS, SIGFPE, and SIGSEGV. SIGBUS and SIGSEGV are treated as a
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// single exception. Obviously there are other signals but they do not
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// have obvious meanings in the context of the synthetic target. NOTE:
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// SIGSTKFLT may be needed as well at some point.
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#define CYGNUM_HAL_INTERRUPT_RTC 0
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#define CYGNUM_HAL_ISR_MIN 0
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#define CYGNUM_HAL_ISR_MAX 31
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#define CYGNUM_HAL_ISR_COUNT (CYGNUM_HAL_ISR_MAX + 1)
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#define CYGNUM_HAL_EXCEPTION_ILLEGAL_INSTRUCTION 0
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#define CYGNUM_HAL_EXCEPTION_DATA_ACCESS 1
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#define CYGNUM_HAL_EXCEPTION_FPU 2
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#define CYGNUM_HAL_EXCEPTION_MIN 0
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#define CYGNUM_HAL_EXCEPTION_MAX CYGNUM_HAL_EXCEPTION_FPU
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#define CYGNUM_HAL_EXCEPTION_COUNT (CYGNUM_HAL_EXCEPTION_MAX + 1)
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#define CYGNUM_HAL_VECTOR_SIGNAL 0
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#define CYGNUM_HAL_VSR_MIN 0
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#define CYGNUM_HAL_VSR_MAX CYGNUM_HAL_VECTOR_SIGNAL
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#define CYGNUM_HAL_VSR_COUNT (CYGNUM_HAL_VSR_MAX + 1)
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// These #include's cannot happen until after the above are defined.
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// There are dependencies on e.g. CYGNUM_HAL_EXCEPTION_COUNT.
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// Basic data types
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#include <cyg/infra/cyg_type.h>
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// cyg_vector_t etc., supplied either by the kernel or the common HAL
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#include <cyg/hal/drv_api.h>
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// Nearly all interrupt state control happens via functions. This
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// facilitates debugging, for example it is easier to set breakpoints
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// that way, at the cost of performance. However performance is not a
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// critical issue for the synthetic target, Instead it is intended to
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// facilitate application development, and hence debugability has a
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// higher priority. There is one exception: the sequence
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// disable_interrupts() followed by restore_interrupts() occurs
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// frequently and is worth some inlining.
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//
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// Note: some of the details such as the existence of a global
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// variable hal_interrupts_enabled are known to the context switch
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// code in the variant HAL.
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typedef cyg_bool_t CYG_INTERRUPT_STATE;
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externC volatile cyg_bool_t hal_interrupts_enabled;
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externC void hal_enable_interrupts(void);
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externC cyg_bool_t hal_interrupt_in_use(cyg_vector_t);
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externC void hal_interrupt_attach(cyg_vector_t, cyg_ISR_t*, CYG_ADDRWORD, CYG_ADDRESS);
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externC void hal_interrupt_detach(cyg_vector_t, cyg_ISR_t*);
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externC void (*hal_vsr_get(cyg_vector_t))(void);
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externC void hal_vsr_set(cyg_vector_t, void (*)(void), void (**)(void));
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externC void hal_interrupt_mask(cyg_vector_t);
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externC void hal_interrupt_unmask(cyg_vector_t);
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externC void hal_interrupt_acknowledge(cyg_vector_t);
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externC void hal_interrupt_configure(cyg_vector_t, cyg_bool_t, cyg_bool_t);
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externC void hal_interrupt_set_level(cyg_vector_t, cyg_priority_t);
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#define HAL_ENABLE_INTERRUPTS() \
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CYG_MACRO_START \
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hal_enable_interrupts(); \
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CYG_MACRO_END
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#define HAL_DISABLE_INTERRUPTS(_old_) \
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CYG_MACRO_START \
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_old_ = hal_interrupts_enabled; \
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hal_interrupts_enabled = false; \
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CYG_MACRO_END
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#define HAL_RESTORE_INTERRUPTS(_old_) \
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CYG_MACRO_START \
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if (!_old_) { \
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hal_interrupts_enabled = false; \
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} else if (!hal_interrupts_enabled) { \
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hal_enable_interrupts(); \
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} \
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CYG_MACRO_END
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#define HAL_QUERY_INTERRUPTS(_old_) \
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CYG_MACRO_START \
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_old_ = hal_interrupts_enabled; \
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CYG_MACRO_END
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#define HAL_TRANSLATE_VECTOR(_vector_, _index_) \
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CYG_MACRO_START \
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(_index_) = (_vector_); \
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CYG_MACRO_END
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#define HAL_INTERRUPT_IN_USE(_vector_, _state_) \
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CYG_MACRO_START \
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(_state_) = hal_interrupt_in_use(_vector_); \
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CYG_MACRO_END
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#define HAL_INTERRUPT_ATTACH(_vector_, _isr_, _data_, _object_ ) \
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CYG_MACRO_START \
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hal_interrupt_attach(_vector_, _isr_, (CYG_ADDRWORD) _data_, (CYG_ADDRESS) _object_); \
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CYG_MACRO_END
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#define HAL_INTERRUPT_DETACH(_vector_, _isr_) \
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CYG_MACRO_START \
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hal_interrupt_detach(_vector_, _isr_); \
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CYG_MACRO_END
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#define HAL_VSR_GET(_vector_, _vsr_) \
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CYG_MACRO_START \
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(*_vsr_) = hal_vsr_get(_vector_); \
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CYG_MACRO_END
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#define HAL_VSR_SET(_vector_, _vsr_, _poldvsr_) \
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CYG_MACRO_START \
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hal_vsr_set(_vector_, _vsr_, _poldvsr_); \
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CYG_MACRO_END
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#define HAL_INTERRUPT_MASK(_vector_) \
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CYG_MACRO_START \
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hal_interrupt_mask(_vector_); \
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CYG_MACRO_END
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#define HAL_INTERRUPT_UNMASK(_vector_) \
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CYG_MACRO_START \
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hal_interrupt_unmask(_vector_); \
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CYG_MACRO_END
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#define HAL_INTERRUPT_ACKNOWLEDGE(_vector_) \
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CYG_MACRO_START \
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hal_interrupt_acknowledge(_vector_); \
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CYG_MACRO_END
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#define HAL_INTERRUPT_CONFIGURE(_vector_, _level_, _up_) \
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CYG_MACRO_START \
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hal_interrupt_configure(_vector_, _level_, _up_); \
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CYG_MACRO_END
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#define HAL_INTERRUPT_SET_LEVEL(_vector_, _level_) \
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CYG_MACRO_START \
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hal_interrupt_set_level(_vector_, _level_); \
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CYG_MACRO_END
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// Additional data exported by the synthetic target interrupt handling
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// subsystem. These two variables correspond to typical interrupt
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// status and mask registers.
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extern volatile cyg_uint32 synth_pending_isrs;
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extern volatile cyg_uint32 synth_masked_isrs;
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// ----------------------------------------------------------------------------
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// The clock support
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externC void hal_clock_initialize(cyg_uint32);
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externC cyg_uint32 hal_clock_read(void);
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#define HAL_CLOCK_INITIALIZE( _period_ ) \
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CYG_MACRO_START \
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hal_clock_initialize(_period_); \
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CYG_MACRO_END
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// No special action is needed for reset.
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#define HAL_CLOCK_RESET( _vector_, _period_ ) \
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CYG_EMPTY_STATEMENT
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#define HAL_CLOCK_READ(_pvalue_) \
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CYG_MACRO_START \
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*(_pvalue_) = hal_clock_read(); \
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CYG_MACRO_END
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// ----------------------------------------------------------------------------
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// HAL_DELAY_US() support. The macro is provided by the processor-specific
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// HAL, but the bogomips rating is provided by the architectural code.
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extern int hal_bogomips;
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#include <cyg/hal/var_intr.h>
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// ----------------------------------------------------------------------------
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// Resetting the Synth target is not possible, but existing the process is.
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externC void cyg_hal_sys_exit(int);
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#define HAL_PLATFORM_RESET() \
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CYG_MACRO_START \
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cyg_hal_sys_exit(0); \
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CYG_MACRO_END
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// ----------------------------------------------------------------------------
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// Test case exit support.
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#define CYGHWR_TEST_PROGRAM_EXIT() \
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CYG_MACRO_START \
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cyg_hal_sys_exit(0); \
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CYG_MACRO_END
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//---------------------------------------------------------------------------
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#endif // ifndef CYGONCE_HAL_HAL_INTR_H
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// End of hal_intr.h
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