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//==========================================================================
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//
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// adc2.c
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//
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// ADC performance test
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//
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//==========================================================================
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// ####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 2009 Free Software Foundation, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later
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// version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with eCos; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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//
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// As a special exception, if other files instantiate templates or use
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// macros or inline functions from this file, or you compile this file
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// and link it with other works to produce a work based on this file,
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// this file does not by itself cause the resulting work to be covered by
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// the GNU General Public License. However the source code for this file
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// must still be made available in accordance with section (3) of the GNU
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// General Public License v2.
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//
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// This exception does not invalidate any other reasons why a work based
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// on this file might be covered by the GNU General Public License.
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// -------------------------------------------
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// ####ECOSGPLCOPYRIGHTEND####
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//==========================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): Simon Kallweit <simon.kallweit@intefo.ch>
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// Contributors:
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// Date: 2009-03-02
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// Description: ADC performance test
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//####DESCRIPTIONEND####
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#include <pkgconf/system.h>
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#include <cyg/infra/testcase.h>
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#include <cyg/infra/cyg_ass.h>
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#include <cyg/infra/diag.h>
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#include <cyg/hal/hal_diag.h>
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#include <cyg/hal/hal_arch.h>
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// Package requirements
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#if defined(CYGPKG_IO_ADC) && defined(CYGPKG_KERNEL)
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#include <pkgconf/kernel.h>
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#include <cyg/io/io.h>
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#include <cyg/io/devtab.h>
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#include <cyg/io/adc.h>
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// Package option requirements
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#if defined(CYGFUN_KERNEL_API_C)
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#include <cyg/kernel/kapi.h>
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#define MAX_CHANNELS 64 // Max channels to test
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#define TICKS_PER_SECOND \
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(1000000000 / (CYGNUM_HAL_RTC_NUMERATOR / CYGNUM_HAL_RTC_DENOMINATOR))
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// ADC test channel
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typedef struct test_channel {
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const char *dev; // ADC channel device name
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cyg_io_handle_t handle; // ADC channel handle
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cyg_uint32 count; // Sample counter
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} test_channel;
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// ADC test channels
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static test_channel test_channels[MAX_CHANNELS];
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// Thread data
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cyg_handle_t thread_handle;
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cyg_thread thread_data;
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cyg_uint8 thread_stack[CYGNUM_HAL_STACK_SIZE_TYPICAL];
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static void
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adc_thread(cyg_addrword_t data)
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{
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cyg_uint32 num = 0;
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cyg_devtab_entry_t *t;
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test_channel *chan;
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cyg_adc_sample_t sample;
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Cyg_ErrNo res;
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cyg_uint32 cfg_data;
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cyg_uint32 len;
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cyg_uint32 start_time;
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cyg_uint32 end_time;
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int i;
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cyg_uint8 seconds = 0;
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float final_seconds;
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cyg_uint32 samples_expected;
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CYG_TEST_INFO("ADC performance test");
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// This test reads samples from all enabled ADC channels. Each second, the
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// number of already acquired samples is printed. After 10 seconds, all ADC
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// channels are stpped and each ADC buffer is read until empty. If the
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// number of acquired samples is much smaller than the number of expected
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// samples, the rate is too high.
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CYG_TEST_INFO("Opening available ADC channels");
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for (t = &__DEVTAB__[0]; t != &__DEVTAB_END__; t++) {
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if (t->handlers != &cyg_io_adc_devio)
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continue;
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chan = &test_channels[num++];
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chan->dev = t->name;
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if (cyg_io_lookup(chan->dev, &chan->handle) != ENOERR)
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CYG_TEST_FAIL_FINISH("Cannot open ADC channel");
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}
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diag_printf("Opened %d ADC channels\n", num);
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CYG_TEST_INFO("Preparing ADC channels for test");
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for (i = 0; i < num; i++) {
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chan = &test_channels[i];
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// Disable channel
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res = cyg_io_set_config(chan->handle, CYG_IO_SET_CONFIG_ADC_DISABLE, 0, 0);
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if (res != ENOERR)
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CYG_TEST_FAIL_FINISH("Failed to disable ADC channel");
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// Make channel non-blocking
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cfg_data = 0;
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len = sizeof(cfg_data);
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res = cyg_io_set_config(chan->handle,
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CYG_IO_SET_CONFIG_READ_BLOCKING,
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&cfg_data, &len);
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if (res != ENOERR)
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CYG_TEST_FAIL_FINISH("Failed to make ADC channel non-blocking");
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// Set channel sampling rate
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cfg_data = CYGNUM_IO_ADC_PERFORMANCE_TEST_RATE;
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len = sizeof(cfg_data);
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res = cyg_io_set_config(chan->handle,
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CYG_IO_SET_CONFIG_ADC_RATE,
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&cfg_data, &len);
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if (res != ENOERR)
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CYG_TEST_FAIL_FINISH("Failed to set ADC channel sampling rate");
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// Flush channel
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do {
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len = sizeof(sample);
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res = cyg_io_read(chan->handle, &sample, &len);
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} while (res == ENOERR);
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chan->count = 0;
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}
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CYG_TEST_INFO("Starting measurement");
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for (i = 0; i < num; i++) {
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chan = &test_channels[i];
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// Enable channel
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res = cyg_io_set_config(chan->handle, CYG_IO_SET_CONFIG_ADC_ENABLE, 0, 0);
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if (res != ENOERR)
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CYG_TEST_FAIL_FINISH("Failed to enabled ADC channel");
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}
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start_time = cyg_current_time();
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do {
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for (i = 0; i < num; i++) {
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chan = &test_channels[i];
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// Read & count samples
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do {
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cyg_uint32 len = sizeof(sample);
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res = cyg_io_read(chan->handle, &sample, &len);
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if (res == ENOERR)
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chan->count++;
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} while (res == ENOERR);
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}
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// Print number of acquired samples - if one second is expired. We
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// expect that the number of acquired samples is nearly the sample rate
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end_time = cyg_current_time();
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if ((end_time - start_time) >= TICKS_PER_SECOND) {
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start_time = end_time;
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diag_printf("\n");
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for (i = 0; i < num; i++) {
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chan = &test_channels[i];
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diag_printf("%-20s\t= %d\n", chan->dev, chan->count);
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}
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seconds++;
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}
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} while (seconds < 10);
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for (i = 0; i < num; i++) {
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chan = &test_channels[i];
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// Disable channel
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res = cyg_io_set_config(chan->handle, CYG_IO_SET_CONFIG_ADC_DISABLE, 0, 0);
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if (res != ENOERR)
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CYG_TEST_FAIL_FINISH("Failed to disable ADC channel");
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}
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end_time = cyg_current_time();
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for (i = 0; i < num; i++) {
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chan = &test_channels[i];
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// Count remainding samples
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do {
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len = sizeof(sample);
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res = cyg_io_read(chan->handle, &sample, &len);
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if (res == ENOERR)
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chan->count++;
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} while (res == ENOERR);
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}
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CYG_TEST_INFO("Finished measurement");
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diag_printf("\n\n----------------------------------------\n");
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final_seconds = (end_time - start_time) + (seconds * TICKS_PER_SECOND);
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final_seconds /= TICKS_PER_SECOND;
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samples_expected = final_seconds * CYGNUM_IO_ADC_PERFORMANCE_TEST_RATE;
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diag_printf("Samples expected after %d milliseconds: %d\n",
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(unsigned int) (final_seconds * 1000), samples_expected);
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diag_printf("Samples read (per channel):\n");
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for (i = 0; i < num; i++) {
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chan = &test_channels[i];
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diag_printf("%-20s\t= %d\n", chan->dev, chan->count);
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}
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CYG_TEST_PASS_FINISH("ADC performance test OK");
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}
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void
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cyg_start(void)
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{
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CYG_TEST_INIT();
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// Create the main ADC test thread
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cyg_thread_create(
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4,
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adc_thread,
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(cyg_addrword_t) 0,
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"adc2",
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thread_stack,
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sizeof(thread_stack),
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&thread_handle,
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&thread_data
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);
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cyg_thread_resume(thread_handle);
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cyg_scheduler_start();
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}
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#else // CYGFUN_KERNEL_API_C
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#define N_A_MSG "Needs kernel C API"
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#endif
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#else // CYGPKG_IO_ADC && CYGPKG_KERNEL
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#define N_A_MSG "Needs Kernel and ADC support"
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#endif
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#ifdef N_A_MSG
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void
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cyg_start( void )
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{
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CYG_TEST_INIT();
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CYG_TEST_NA(N_A_MSG);
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}
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#endif // N_A_MSG
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