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jeremybenn |
//*-----------------------------------------------------------------------------
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//* ATMEL Microcontroller Software Support - ROUSSET -
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//*-----------------------------------------------------------------------------
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//* The software is delivered "AS IS" without warranty or condition of any
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//* kind, either express, implied or statutory. This includes without
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//* limitation any warranty or condition with respect to merchantability or
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//* fitness for any particular purpose, or against the infringements of
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//* intellectual property rights of others.
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//*-----------------------------------------------------------------------------
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//* File Name : ebi.h
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//* Object : External Bus Interface Definition File
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//* Translator : ARM Software Development Toolkit V2.11a
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//*
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//* 1.0 03/11/97 JCZ : Creation
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//* 2.0 21/10/98 JCZ : Clean up
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//*-----------------------------------------------------------------------------
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#ifndef ebi_h
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#define ebi_h
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/*----------------------------------------*/
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/* Memory Controller Interface Definition */
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/*----------------------------------------*/
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typedef struct
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{
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at91_reg EBI_CSR[8] ; /* Chip Select Register */
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at91_reg EBI_RCR ; /* Remap Control Register */
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at91_reg EBI_MCR ; /* Memory Control Register */
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} StructEBI ;
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/*-----------------------*/
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/* Chip Select Registers */
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/*-----------------------*/
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/* Data Bus Width */
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#define DataBus16 (1<<0)
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#define DataBus8 (2<<0)
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#define DBW (3<<0)
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/* Number of Wait States */
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#define B_NWS 2
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#define WaitState1 (0<<B_NWS)
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#define WaitState2 (1<<B_NWS)
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#define WaitState3 (2<<B_NWS)
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#define WaitState4 (3<<B_NWS)
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#define WaitState5 (4<<B_NWS)
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#define WaitState6 (5<<B_NWS)
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#define WaitState7 (6<<B_NWS)
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#define WaitState8 (7<<B_NWS)
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#define NWS (7<<B_NWS)
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/* Wait State Enable */
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#define WaitStateDisable (0<<5)
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#define WaitStateEnable (1<<5)
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#define WSE (1<<5)
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/* Page size */
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#define PageSize1M (0<<7)
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#define PageSize4M (1<<7)
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#define PageSize16M (2<<7)
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#define PageSize64M (3<<7)
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#define PAGES (3<<7)
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/* Number of Data Float Output Time Clock Cycle */
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#define B_TDF 9
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#define tDF_0cycle (0<<B_TDF)
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#define tDF_1cycle (1<<B_TDF)
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#define tDF_2cycle (2<<B_TDF)
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#define tDF_3cycle (3<<B_TDF)
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#define tDF_4cycle (4<<B_TDF)
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#define tDF_5cycle (5<<B_TDF)
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#define tDF_6cycle (6<<B_TDF)
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#define tDF_7cycle (7<<B_TDF)
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#define TDF (7<<B_TDF)
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/* Byte Access Type */
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#define ByteWriteAccessType (0<<12)
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#define ByteSelectAccessType (1<<12)
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#define BAT 1<<12)
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/* Chip Select Enable */
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#define CSEnable (1<<13)
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#define CSDisable (0<<13)
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#define CSE (1<<13)
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#define BA ((u_int)(0xFFF)<<20)
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/*-------------------------*/
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/* Memory Control Register */
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/*-------------------------*/
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/* Address Line Enable */
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#define ALE (7<<0)
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#define BankSize16M (0<<0)
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#define BankSize8M (4<<0)
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#define BankSize4M (5<<0)
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#define BankSize2M (6<<0)
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#define BankSize1M (7<<0)
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/* Data Read Protocol */
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#define StandardReadProtocol (0<<4)
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#define EarlyReadProtocol (1<<4)
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#define DRP (1<<4)
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/*------------------------*/
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/* Remap Control Register */
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/*------------------------*/
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#define RCB (1<<0)
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/*--------------------------------*/
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/* Device Dependancies Definition */
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/*--------------------------------*/
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#ifdef AT91M40400
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/* External Bus Interface User Interface BAse Address */
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#define EBI_BASE ((StructEBI *) 0xFFE00000)
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#endif
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#endif /* ebi_h */
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