OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [ARM7_AT91FR40008_GCC/] [ebi.h] - Blame information for rev 578

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 577 jeremybenn
//*-----------------------------------------------------------------------------
2
//*         ATMEL Microcontroller Software Support  -  ROUSSET  -
3
//*-----------------------------------------------------------------------------
4
//* The software is delivered "AS IS" without warranty or condition of any
5
//* kind, either express, implied or statutory. This includes without
6
//* limitation any warranty or condition with respect to merchantability or
7
//* fitness for any particular purpose, or against the infringements of
8
//* intellectual property rights of others.
9
//*-----------------------------------------------------------------------------
10
//* File Name           : ebi.h
11
//* Object              : External Bus Interface Definition File
12
//* Translator          : ARM Software Development Toolkit V2.11a
13
//*
14
//* 1.0 03/11/97 JCZ    : Creation
15
//* 2.0 21/10/98 JCZ    : Clean up
16
//*-----------------------------------------------------------------------------
17
 
18
#ifndef ebi_h
19
#define ebi_h
20
 
21
/*----------------------------------------*/
22
/* Memory Controller Interface Definition */
23
/*----------------------------------------*/
24
 
25
typedef struct
26
{
27
    at91_reg        EBI_CSR[8] ;        /* Chip Select Register */
28
    at91_reg        EBI_RCR ;           /* Remap Control Register */
29
    at91_reg        EBI_MCR ;           /* Memory Control Register */
30
} StructEBI ;
31
 
32
/*-----------------------*/
33
/* Chip Select Registers */
34
/*-----------------------*/
35
 
36
/* Data Bus Width */
37
#define DataBus16               (1<<0)
38
#define DataBus8                (2<<0)
39
#define DBW                     (3<<0)
40
 
41
/* Number of Wait States */
42
#define B_NWS                   2
43
#define WaitState1              (0<<B_NWS)
44
#define WaitState2              (1<<B_NWS)
45
#define WaitState3              (2<<B_NWS)
46
#define WaitState4              (3<<B_NWS)
47
#define WaitState5              (4<<B_NWS)
48
#define WaitState6              (5<<B_NWS)
49
#define WaitState7              (6<<B_NWS)
50
#define WaitState8              (7<<B_NWS)
51
#define NWS                     (7<<B_NWS)
52
 
53
/* Wait State Enable */
54
#define WaitStateDisable        (0<<5)
55
#define WaitStateEnable         (1<<5)
56
#define WSE                     (1<<5)
57
 
58
/* Page size */
59
#define PageSize1M              (0<<7)
60
#define PageSize4M              (1<<7)
61
#define PageSize16M             (2<<7)
62
#define PageSize64M             (3<<7)
63
#define PAGES                   (3<<7)
64
 
65
/* Number of Data Float Output Time Clock Cycle */
66
#define B_TDF                   9
67
#define tDF_0cycle              (0<<B_TDF)
68
#define tDF_1cycle              (1<<B_TDF)
69
#define tDF_2cycle              (2<<B_TDF)
70
#define tDF_3cycle              (3<<B_TDF)
71
#define tDF_4cycle              (4<<B_TDF)
72
#define tDF_5cycle              (5<<B_TDF)
73
#define tDF_6cycle              (6<<B_TDF)
74
#define tDF_7cycle              (7<<B_TDF)
75
#define TDF                     (7<<B_TDF)
76
 
77
/* Byte Access Type */
78
#define ByteWriteAccessType (0<<12)
79
#define ByteSelectAccessType    (1<<12)
80
#define BAT                     1<<12)
81
 
82
/* Chip Select Enable */
83
#define CSEnable                (1<<13)
84
#define CSDisable               (0<<13)
85
#define CSE                     (1<<13)
86
 
87
#define BA                      ((u_int)(0xFFF)<<20)
88
 
89
/*-------------------------*/
90
/* Memory Control Register */
91
/*-------------------------*/
92
 
93
/* Address Line Enable */
94
#define ALE                     (7<<0)
95
#define BankSize16M             (0<<0)
96
#define BankSize8M              (4<<0)
97
#define BankSize4M              (5<<0)
98
#define BankSize2M              (6<<0)
99
#define BankSize1M              (7<<0)
100
 
101
/* Data Read Protocol */
102
#define StandardReadProtocol    (0<<4)
103
#define EarlyReadProtocol       (1<<4)
104
#define DRP                     (1<<4)
105
 
106
/*------------------------*/
107
/* Remap Control Register */
108
/*------------------------*/
109
 
110
#define RCB                     (1<<0)
111
 
112
/*--------------------------------*/
113
/* Device Dependancies Definition */
114
/*--------------------------------*/
115
 
116
#ifdef AT91M40400
117
/* External Bus Interface User Interface BAse Address */
118
#define EBI_BASE            ((StructEBI *) 0xFFE00000)
119
#endif
120
 
121
#endif /* ebi_h */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.