1 |
577 |
jeremybenn |
// ---------------------------------------------------------
|
2 |
|
|
// ATMEL Microcontroller Software Support - ROUSSET -
|
3 |
|
|
// ---------------------------------------------------------
|
4 |
|
|
// The software is delivered "AS IS" without warranty or
|
5 |
|
|
// condition of any kind, either express, implied or
|
6 |
|
|
// statutory. This includes without limitation any warranty
|
7 |
|
|
// or condition with respect to merchantability or fitness
|
8 |
|
|
// for any particular purpose, or against the infringements of
|
9 |
|
|
// intellectual property rights of others.
|
10 |
|
|
// ---------------------------------------------------------
|
11 |
|
|
// File: SAM7_RAM.mac
|
12 |
|
|
//
|
13 |
|
|
// User setup file for CSPY debugger to simulate interrupt
|
14 |
|
|
// driven Fibonacchi data input.
|
15 |
|
|
// 1.1 16/Jun/04 JPP : Creation
|
16 |
|
|
// 1.2 27/Aug/04 JPP : PLL setting
|
17 |
|
|
//
|
18 |
|
|
// $Revision: 2 $
|
19 |
|
|
//
|
20 |
|
|
// ---------------------------------------------------------
|
21 |
|
|
|
22 |
|
|
__var i;
|
23 |
|
|
__var pt;
|
24 |
|
|
|
25 |
|
|
execUserPreload()
|
26 |
|
|
{
|
27 |
|
|
//*
|
28 |
|
|
PllSetting();
|
29 |
|
|
//* Set the RAM memory at 0x0020 0000 for code AT 0 flash area
|
30 |
|
|
CheckNoRemap();
|
31 |
|
|
//* Get the Chip ID (AT91C_DBGU_C1R & AT91C_DBGU_C2R
|
32 |
|
|
i=__readMemory32(0xFFFFF240,"Memory");
|
33 |
|
|
__message " ---------------------------------------- Chip ID 0x",i:%X;
|
34 |
|
|
i=__readMemory32(0xFFFFF244,"Memory");
|
35 |
|
|
__message " ---------------------------------------- Extention 0x",i:%X;
|
36 |
|
|
i=__readMemory32(0xFFFFFF6C,"Memory");
|
37 |
|
|
__message " ---------------------------------------- Flash Version 0x",i:%X;
|
38 |
|
|
//* Get the chip status
|
39 |
|
|
|
40 |
|
|
//* Init AIC
|
41 |
|
|
AIC();
|
42 |
|
|
//* Watchdog Disable
|
43 |
|
|
Watchdog();
|
44 |
|
|
}
|
45 |
|
|
//-----------------------------------------------------------------------------
|
46 |
|
|
// PllSetting
|
47 |
|
|
//-------------------------------
|
48 |
|
|
// Set PLL
|
49 |
|
|
//-----------------------------------------------------------------------------
|
50 |
|
|
PllSetting()
|
51 |
|
|
{
|
52 |
|
|
// -1- Enabling the Main Oscillator:
|
53 |
|
|
//*#define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register
|
54 |
|
|
//*#define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register
|
55 |
|
|
//*#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register
|
56 |
|
|
|
57 |
|
|
//*pPMC->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x06 <<8) | //0x0000 0600
|
58 |
|
|
// AT91C_CKGR_MOSCEN )); //0x0000 0001
|
59 |
|
|
__writeMemory32(0x00000601,0xFFFFFC20,"Memory");
|
60 |
|
|
|
61 |
|
|
// -2- Wait
|
62 |
|
|
// -3- Setting PLL and divider:
|
63 |
|
|
// - div by 5 Fin = 3,6864 =(18,432 / 5)
|
64 |
|
|
// - Mul 25+1: Fout = 95,8464 =(3,6864 *26)
|
65 |
|
|
// for 96 MHz the erroe is 0.16%
|
66 |
|
|
// Field out NOT USED = 0
|
67 |
|
|
// PLLCOUNT pll startup time esrtimate at : 0.844 ms
|
68 |
|
|
// PLLCOUNT 28 = 0.000844 /(1/32768)
|
69 |
|
|
// pPMC->PMC_PLLR = ((AT91C_CKGR_DIV & 0x05) | //0x0000 0005
|
70 |
|
|
// (AT91C_CKGR_PLLCOUNT & (28<<8)) //0x0000 1C00
|
71 |
|
|
// (AT91C_CKGR_MUL & (25<<16))); //0x0019 0000
|
72 |
|
|
__writeMemory32(0x00191C05,0xFFFFFC2C,"Memory");
|
73 |
|
|
// -2- Wait
|
74 |
|
|
// -5- Selection of Master Clock and Processor Clock
|
75 |
|
|
// select the PLL clock divided by 2
|
76 |
|
|
// pPMC->PMC_MCKR = AT91C_PMC_CSS_PLL_CLK | //0x0000 0003
|
77 |
|
|
// AT91C_PMC_PRES_CLK_2 ; //0x0000 0004
|
78 |
|
|
__writeMemory32(0x00000007,0xFFFFFC30,"Memory");
|
79 |
|
|
|
80 |
|
|
__message "------------------------------- PLL Enable ----------------------------------------";
|
81 |
|
|
}
|
82 |
|
|
|
83 |
|
|
//-----------------------------------------------------------------------------
|
84 |
|
|
// Watchdog
|
85 |
|
|
//-------------------------------
|
86 |
|
|
// Normally, the Watchdog is enable at the reset for load it's preferable to
|
87 |
|
|
// Disable.
|
88 |
|
|
//-----------------------------------------------------------------------------
|
89 |
|
|
Watchdog()
|
90 |
|
|
{
|
91 |
|
|
//* Watchdog Disable
|
92 |
|
|
// AT91C_BASE_WDTC->WDTC_WDMR= AT91C_SYSC_WDDIS;
|
93 |
|
|
__writeMemory32(0x00008000,0xFFFFFD44,"Memory");
|
94 |
|
|
__message "------------------------------- Watchdog Disable ----------------------------------------";
|
95 |
|
|
}
|
96 |
|
|
|
97 |
|
|
CheckNoRemap()
|
98 |
|
|
{
|
99 |
|
|
//* Read the value at 0x0
|
100 |
|
|
i=__readMemory32(0x00000000,"Memory");
|
101 |
|
|
i=i+1;
|
102 |
|
|
__writeMemory32(i,0x00,"Memory");
|
103 |
|
|
pt=__readMemory32(0x00000000,"Memory");
|
104 |
|
|
|
105 |
|
|
if (i == pt)
|
106 |
|
|
{
|
107 |
|
|
__message "------------------------------- The Remap is done ----------------------------------------";
|
108 |
|
|
|
109 |
|
|
} else {
|
110 |
|
|
__message "------------------------------- The Remap is NOT -----------------------------------------";
|
111 |
|
|
//* Toggel RESET The remap
|
112 |
|
|
__writeMemory32(0x00000001,0xFFFFFF00,"Memory");
|
113 |
|
|
}
|
114 |
|
|
|
115 |
|
|
}
|
116 |
|
|
|
117 |
|
|
execUserSetup()
|
118 |
|
|
{
|
119 |
|
|
ini();
|
120 |
|
|
__message "-------------------------------Set PC ----------------------------------------";
|
121 |
|
|
__writeMemory32(0x00000000,0xB4,"Register");
|
122 |
|
|
}
|
123 |
|
|
|
124 |
|
|
//-----------------------------------------------------------------------------
|
125 |
|
|
// Reset the Interrupt Controller
|
126 |
|
|
//-------------------------------
|
127 |
|
|
// Normally, the code is executed only if a reset has been actually performed.
|
128 |
|
|
// So, the AIC initialization resumes at setting up the default vectors.
|
129 |
|
|
//-----------------------------------------------------------------------------
|
130 |
|
|
AIC()
|
131 |
|
|
{
|
132 |
|
|
// Mask All interrupt pAic->AIC_IDCR = 0xFFFFFFFF;
|
133 |
|
|
__writeMemory32(0xFFFFFFFF,0xFFFFF124,"Memory");
|
134 |
|
|
|
135 |
|
|
for (i=0;i < 8; i++)
|
136 |
|
|
{
|
137 |
|
|
// AT91C_BASE_AIC->AIC_EOICR
|
138 |
|
|
pt = __readMemory32(0xFFFFF130,"Memory");
|
139 |
|
|
|
140 |
|
|
}
|
141 |
|
|
__message "------------------------------- AIC INIT ---------------------------------------------";
|
142 |
|
|
}
|
143 |
|
|
|
144 |
|
|
ini()
|
145 |
|
|
{
|
146 |
|
|
__writeMemory32(0x0,0x00,"Register");
|
147 |
|
|
__writeMemory32(0x0,0x04,"Register");
|
148 |
|
|
__writeMemory32(0x0,0x08,"Register");
|
149 |
|
|
__writeMemory32(0x0,0x0C,"Register");
|
150 |
|
|
__writeMemory32(0x0,0x10,"Register");
|
151 |
|
|
__writeMemory32(0x0,0x14,"Register");
|
152 |
|
|
__writeMemory32(0x0,0x18,"Register");
|
153 |
|
|
__writeMemory32(0x0,0x1C,"Register");
|
154 |
|
|
__writeMemory32(0x0,0x20,"Register");
|
155 |
|
|
__writeMemory32(0x0,0x24,"Register");
|
156 |
|
|
__writeMemory32(0x0,0x28,"Register");
|
157 |
|
|
__writeMemory32(0x0,0x2C,"Register");
|
158 |
|
|
__writeMemory32(0x0,0x30,"Register");
|
159 |
|
|
__writeMemory32(0x0,0x34,"Register");
|
160 |
|
|
__writeMemory32(0x0,0x38,"Register");
|
161 |
|
|
|
162 |
|
|
// Set CPSR
|
163 |
|
|
__writeMemory32(0x0D3,0x98,"Register");
|
164 |
|
|
|
165 |
|
|
}
|
166 |
|
|
|
167 |
|
|
RG()
|
168 |
|
|
{
|
169 |
|
|
|
170 |
|
|
i=__readMemory32(0x00,"Register"); __message "R00 0x",i:%X;
|
171 |
|
|
i=__readMemory32(0x04,"Register"); __message "R01 0x",i:%X;
|
172 |
|
|
i=__readMemory32(0x08,"Register"); __message "R02 0x",i:%X;
|
173 |
|
|
i=__readMemory32(0x0C,"Register"); __message "R03 0x",i:%X;
|
174 |
|
|
i=__readMemory32(0x10,"Register"); __message "R04 0x",i:%X;
|
175 |
|
|
i=__readMemory32(0x14,"Register"); __message "R05 0x",i:%X;
|
176 |
|
|
i=__readMemory32(0x18,"Register"); __message "R06 0x",i:%X;
|
177 |
|
|
i=__readMemory32(0x1C,"Register"); __message "R07 0x",i:%X;
|
178 |
|
|
i=__readMemory32(0x20,"Register"); __message "R08 0x",i:%X;
|
179 |
|
|
i=__readMemory32(0x24,"Register"); __message "R09 0x",i:%X;
|
180 |
|
|
i=__readMemory32(0x28,"Register"); __message "R10 0x",i:%X;
|
181 |
|
|
i=__readMemory32(0x2C,"Register"); __message "R11 0x",i:%X;
|
182 |
|
|
i=__readMemory32(0x30,"Register"); __message "R12 0x",i:%X;
|
183 |
|
|
i=__readMemory32(0x34,"Register"); __message "R13 0x",i:%X;
|
184 |
|
|
i=__readMemory32(0x38,"Register"); __message "R14 0x",i:%X;
|
185 |
|
|
i=__readMemory32(0x3C,"Register"); __message "R13 SVC 0x",i:%X;
|
186 |
|
|
i=__readMemory32(0x40,"Register"); __message "R14 SVC 0x",i:%X;
|
187 |
|
|
i=__readMemory32(0x44,"Register"); __message "R13 ABT 0x",i:%X;
|
188 |
|
|
i=__readMemory32(0x48,"Register"); __message "R14 ABT 0x",i:%X;
|
189 |
|
|
i=__readMemory32(0x4C,"Register"); __message "R13 UND 0x",i:%X;
|
190 |
|
|
i=__readMemory32(0x50,"Register"); __message "R14 UND 0x",i:%X;
|
191 |
|
|
i=__readMemory32(0x54,"Register"); __message "R13 IRQ 0x",i:%X;
|
192 |
|
|
i=__readMemory32(0x58,"Register"); __message "R14 IRQ 0x",i:%X;
|
193 |
|
|
i=__readMemory32(0x5C,"Register"); __message "R08 FIQ 0x",i:%X;
|
194 |
|
|
i=__readMemory32(0x60,"Register"); __message "R09 FIQ 0x",i:%X;
|
195 |
|
|
i=__readMemory32(0x64,"Register"); __message "R10 FIQ 0x",i:%X;
|
196 |
|
|
i=__readMemory32(0x68,"Register"); __message "R11 FIQ 0x",i:%X;
|
197 |
|
|
i=__readMemory32(0x6C,"Register"); __message "R12 FIQ 0x",i:%X;
|
198 |
|
|
i=__readMemory32(0x70,"Register"); __message "R13 FIQ 0x",i:%X;
|
199 |
|
|
i=__readMemory32(0x74,"Register"); __message "R14 FIQ0x",i:%X;
|
200 |
|
|
i=__readMemory32(0x98,"Register"); __message "CPSR ",i:%X;
|
201 |
|
|
i=__readMemory32(0x94,"Register"); __message "SPSR ",i:%X;
|
202 |
|
|
i=__readMemory32(0x9C,"Register"); __message "SPSR ABT ",i:%X;
|
203 |
|
|
i=__readMemory32(0xA0,"Register"); __message "SPSR ABT ",i:%X;
|
204 |
|
|
i=__readMemory32(0xA4,"Register"); __message "SPSR UND ",i:%X;
|
205 |
|
|
i=__readMemory32(0xA8,"Register"); __message "SPSR IRQ ",i:%X;
|
206 |
|
|
i=__readMemory32(0xAC,"Register"); __message "SPSR FIQ ",i:%X;
|
207 |
|
|
|
208 |
|
|
i=__readMemory32(0xB4,"Register"); __message "PC 0x",i:%X;
|
209 |
|
|
|
210 |
|
|
}
|
211 |
|
|
|