URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [ARM7_AT91SAM7X256_Eclipse/] [RTOSDemo/] [boot.s] - Blame information for rev 613

Go to most recent revision | Details | Compare with Previous | View Log


        /* Sample initialization file */
 
        .extern main
        .extern exit
        .extern AT91F_LowLevelInit
        .extern vPortYieldProcessor
 
        .text
        .code 32
 
 
        .align  0
 
        .extern __stack_end__
        .extern __bss_beg__
        .extern __bss_end__
        .extern __data_beg__
        .extern __data_end__
        .extern __data+beg_src__
 
        .global start
        .global endless_loop
 
        /* Stack Sizes */
    .set  UND_STACK_SIZE, 0x00000004
    .set  ABT_STACK_SIZE, 0x00000004
    .set  FIQ_STACK_SIZE, 0x00000004
    .set  IRQ_STACK_SIZE, 0X00000400
    .set  SVC_STACK_SIZE, 0x00000400
 
        /* Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs */
    .set  MODE_USR, 0x10            /* User Mode */
    .set  MODE_FIQ, 0x11            /* FIQ Mode */
    .set  MODE_IRQ, 0x12            /* IRQ Mode */
    .set  MODE_SVC, 0x13            /* Supervisor Mode */
    .set  MODE_ABT, 0x17            /* Abort Mode */
    .set  MODE_UND, 0x1B            /* Undefined Mode */
    .set  MODE_SYS, 0x1F            /* System Mode */
 
    .equ  I_BIT, 0x80               /* when I bit is set, IRQ is disabled */
    .equ  F_BIT, 0x40               /* when F bit is set, FIQ is disabled */
 
 
start:
_start:
_mainCRTStartup:
 
        /* Setup a stack for each mode - note that this only sets up a usable stack
        for system/user, SWI and IRQ modes.   Also each mode is setup with
        interrupts initially disabled. */
    ldr   r0, .LC6
    msr   CPSR_c, #MODE_UND|I_BIT|F_BIT /* Undefined Instruction Mode */
    mov   sp, r0
    sub   r0, r0, #UND_STACK_SIZE
    msr   CPSR_c, #MODE_ABT|I_BIT|F_BIT /* Abort Mode */
    mov   sp, r0
    sub   r0, r0, #ABT_STACK_SIZE
    msr   CPSR_c, #MODE_FIQ|I_BIT|F_BIT /* FIQ Mode */
    mov   sp, r0
    sub   r0, r0, #FIQ_STACK_SIZE
    msr   CPSR_c, #MODE_IRQ|I_BIT|F_BIT /* IRQ Mode */
    mov   sp, r0
    sub   r0, r0, #IRQ_STACK_SIZE
    msr   CPSR_c, #MODE_SVC|I_BIT|F_BIT /* Supervisor Mode */
    mov   sp, r0
    sub   r0, r0, #SVC_STACK_SIZE
    msr   CPSR_c, #MODE_SYS|I_BIT|F_BIT /* System Mode */
    mov   sp, r0
 
        /* We want to start in supervisor mode.  Operation will switch to system
        mode when the first task starts. */
        msr   CPSR_c, #MODE_SVC|I_BIT|F_BIT
 
    bl          AT91F_LowLevelInit
 
        /* Clear BSS. */
 
        mov     a2, #0                   /* Fill value */
        mov             fp, a2                  /* Null frame pointer */
        mov             r7, a2                  /* Null frame pointer for Thumb */
 
        ldr             r1, .LC1                /* Start of memory block */
        ldr             r3, .LC2                /* End of memory block */
        subs    r3, r3, r1      /* Length of block */
        beq             .end_clear_loop
        mov             r2, #0
 
.clear_loop:
        strb    r2, [r1], #1
        subs    r3, r3, #1
        bgt             .clear_loop
 
.end_clear_loop:
 
        /* Initialise data. */
 
        ldr             r1, .LC3                /* Start of memory block */
        ldr             r2, .LC4                /* End of memory block */
        ldr             r3, .LC5
        subs    r3, r3, r1              /* Length of block */
        beq             .end_set_loop
 
.set_loop:
        ldrb    r4, [r2], #1
        strb    r4, [r1], #1
        subs    r3, r3, #1
        bgt             .set_loop
 
.end_set_loop:
 
        mov             r0, #0          /* no arguments  */
        mov             r1, #0          /* no argv either */
 
    ldr lr, =main
        bx      lr
 
endless_loop:
        b               endless_loop
 
 
        .align 0
 
        .LC1:
        .word   __bss_beg__
        .LC2:
        .word   __bss_end__
        .LC3:
        .word   __data_beg__
        .LC4:
        .word   __data_beg_src__
        .LC5:
        .word   __data_end__
        .LC6:
        .word   __stack_end__
 
 
        /* Setup vector table.  Note that undf, pabt, dabt, fiq just execute
        a null loop. */
 
.section .startup,"ax"
         .code 32
         .align 0
 
        b     _start                                            /* reset - _start                       */
        ldr   pc, _undf                                         /* undefined - _undf            */
        ldr   pc, _swi                                          /* SWI - _swi                           */
        ldr   pc, _pabt                                         /* program abort - _pabt        */
        ldr   pc, _dabt                                         /* data abort - _dabt           */
        nop                                                                     /* reserved                                     */
        ldr   pc, [pc,#-0xF20]                          /* IRQ - read the AIC           */
        ldr   pc, _fiq                                          /* FIQ - _fiq                           */
 
_undf:  .word __undf                    /* undefined                            */
_swi:   .word vPortYieldProcessor       /* SWI                                          */
_pabt:  .word __pabt                    /* program abort                        */
_dabt:  .word __dabt                    /* data abort                           */
_fiq:   .word __fiq                     /* FIQ                                          */
 
__undf: b     .                         /* undefined                            */
__pabt: b     .                         /* program abort                        */
__dabt: b     .                         /* data abort                           */
__fiq:  b     .                         /* FIQ                                          */

Line No.	Rev	Author	Line
1	577	jeremybenn	`/* Sample initialization file */`
2
3			`.extern main`
4			`.extern exit`
5			`.extern AT91F_LowLevelInit`
6			`.extern vPortYieldProcessor`
7
8			`.text`
9			`.code 32`
10
11
12			`.align 0`
13
14			`.extern __stack_end__`
15			`.extern __bss_beg__`
16			`.extern __bss_end__`
17			`.extern __data_beg__`
18			`.extern __data_end__`
19			`.extern __data+beg_src__`
20
21			`.global start`
22			`.global endless_loop`
23
24			`/* Stack Sizes */`
25			`.set UND_STACK_SIZE, 0x00000004`
26			`.set ABT_STACK_SIZE, 0x00000004`
27			`.set FIQ_STACK_SIZE, 0x00000004`
28			`.set IRQ_STACK_SIZE, 0X00000400`
29			`.set SVC_STACK_SIZE, 0x00000400`
30
31			`/* Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs */`
32			`.set MODE_USR, 0x10 /* User Mode */`
33			`.set MODE_FIQ, 0x11 /* FIQ Mode */`
34			`.set MODE_IRQ, 0x12 /* IRQ Mode */`
35			`.set MODE_SVC, 0x13 /* Supervisor Mode */`
36			`.set MODE_ABT, 0x17 /* Abort Mode */`
37			`.set MODE_UND, 0x1B /* Undefined Mode */`
38			`.set MODE_SYS, 0x1F /* System Mode */`
39
40			`.equ I_BIT, 0x80 /* when I bit is set, IRQ is disabled */`
41			`.equ F_BIT, 0x40 /* when F bit is set, FIQ is disabled */`
42
43
44			`start:`
45			`_start:`
46			`_mainCRTStartup:`
47
48			`/* Setup a stack for each mode - note that this only sets up a usable stack`
49			`for system/user, SWI and IRQ modes. Also each mode is setup with`
50			`interrupts initially disabled. */`
51			`ldr r0, .LC6`
52			`msr CPSR_c, #MODE_UND\|I_BIT\|F_BIT /* Undefined Instruction Mode */`
53			`mov sp, r0`
54			`sub r0, r0, #UND_STACK_SIZE`
55			`msr CPSR_c, #MODE_ABT\|I_BIT\|F_BIT /* Abort Mode */`
56			`mov sp, r0`
57			`sub r0, r0, #ABT_STACK_SIZE`
58			`msr CPSR_c, #MODE_FIQ\|I_BIT\|F_BIT /* FIQ Mode */`
59			`mov sp, r0`
60			`sub r0, r0, #FIQ_STACK_SIZE`
61			`msr CPSR_c, #MODE_IRQ\|I_BIT\|F_BIT /* IRQ Mode */`
62			`mov sp, r0`
63			`sub r0, r0, #IRQ_STACK_SIZE`
64			`msr CPSR_c, #MODE_SVC\|I_BIT\|F_BIT /* Supervisor Mode */`
65			`mov sp, r0`
66			`sub r0, r0, #SVC_STACK_SIZE`
67			`msr CPSR_c, #MODE_SYS\|I_BIT\|F_BIT /* System Mode */`
68			`mov sp, r0`
69
70			`/* We want to start in supervisor mode. Operation will switch to system`
71			`mode when the first task starts. */`
72			`msr CPSR_c, #MODE_SVC\|I_BIT\|F_BIT`
73
74			`bl AT91F_LowLevelInit`
75
76			`/* Clear BSS. */`
77
78			`mov a2, #0 /* Fill value */`
79			`mov fp, a2 /* Null frame pointer */`
80			`mov r7, a2 /* Null frame pointer for Thumb */`
81
82			`ldr r1, .LC1 /* Start of memory block */`
83			`ldr r3, .LC2 /* End of memory block */`
84			`subs r3, r3, r1 /* Length of block */`
85			`beq .end_clear_loop`
86			`mov r2, #0`
87
88			`.clear_loop:`
89			`strb r2, [r1], #1`
90			`subs r3, r3, #1`
91			`bgt .clear_loop`
92
93			`.end_clear_loop:`
94
95			`/* Initialise data. */`
96
97			`ldr r1, .LC3 /* Start of memory block */`
98			`ldr r2, .LC4 /* End of memory block */`
99			`ldr r3, .LC5`
100			`subs r3, r3, r1 /* Length of block */`
101			`beq .end_set_loop`
102
103			`.set_loop:`
104			`ldrb r4, [r2], #1`
105			`strb r4, [r1], #1`
106			`subs r3, r3, #1`
107			`bgt .set_loop`
108
109			`.end_set_loop:`
110
111			`mov r0, #0 /* no arguments */`
112			`mov r1, #0 /* no argv either */`
113
114			`ldr lr, =main`
115			`bx lr`
116
117			`endless_loop:`
118			`b endless_loop`
119
120
121			`.align 0`
122
123			`.LC1:`
124			`.word __bss_beg__`
125			`.LC2:`
126			`.word __bss_end__`
127			`.LC3:`
128			`.word __data_beg__`
129			`.LC4:`
130			`.word __data_beg_src__`
131			`.LC5:`
132			`.word __data_end__`
133			`.LC6:`
134			`.word __stack_end__`
135
136
137			`/* Setup vector table. Note that undf, pabt, dabt, fiq just execute`
138			`a null loop. */`
139
140			`.section .startup,"ax"`
141			`.code 32`
142			`.align 0`
143
144			`b _start /* reset - _start */`
145			`ldr pc, _undf /* undefined - _undf */`
146			`ldr pc, _swi /* SWI - _swi */`
147			`ldr pc, _pabt /* program abort - _pabt */`
148			`ldr pc, _dabt /* data abort - _dabt */`
149			`nop /* reserved */`
150			`ldr pc, [pc,#-0xF20] /* IRQ - read the AIC */`
151			`ldr pc, _fiq /* FIQ - _fiq */`
152
153			`_undf: .word __undf /* undefined */`
154			`_swi: .word vPortYieldProcessor /* SWI */`
155			`_pabt: .word __pabt /* program abort */`
156			`_dabt: .word __dabt /* data abort */`
157			`_fiq: .word __fiq /* FIQ */`
158
159			`__undf: b . /* undefined */`
160			`__pabt: b . /* program abort */`
161			`__dabt: b . /* data abort */`
162			`__fiq: b . /* FIQ */`

Browse

Tools

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [ARM7_AT91SAM7X256_Eclipse/] [RTOSDemo/] [boot.s] - Blame information for rev 613