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577 |
jeremybenn |
/*
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FreeRTOS V6.1.1 - Copyright (C) 2011 Real Time Engineers Ltd.
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***************************************************************************
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* *
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* If you are: *
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* *
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* + New to FreeRTOS, *
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* + Wanting to learn FreeRTOS or multitasking in general quickly *
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* + Looking for basic training, *
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* + Wanting to improve your FreeRTOS skills and productivity *
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* *
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* then take a look at the FreeRTOS books - available as PDF or paperback *
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* *
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* "Using the FreeRTOS Real Time Kernel - a Practical Guide" *
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* http://www.FreeRTOS.org/Documentation *
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* *
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* A pdf reference manual is also available. Both are usually delivered *
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* to your inbox within 20 minutes to two hours when purchased between 8am *
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* and 8pm GMT (although please allow up to 24 hours in case of *
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* exceptional circumstances). Thank you for your support! *
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* *
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***************************************************************************
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This file is part of the FreeRTOS distribution.
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FreeRTOS is free software; you can redistribute it and/or modify it under
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the terms of the GNU General Public License (version 2) as published by the
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Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
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***NOTE*** The exception to the GPL is included to allow you to distribute
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a combined work that includes FreeRTOS without being obliged to provide the
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source code for proprietary components outside of the FreeRTOS kernel.
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FreeRTOS is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details. You should have received a copy of the GNU General Public
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License and the FreeRTOS license exception along with FreeRTOS; if not it
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can be viewed here: http://www.freertos.org/a00114.html and also obtained
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by writing to Richard Barry, contact details for whom are available on the
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FreeRTOS WEB site.
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1 tab == 4 spaces!
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http://www.FreeRTOS.org - Documentation, latest information, license and
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contact details.
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http://www.SafeRTOS.com - A version that is certified for use in safety
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critical systems.
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http://www.OpenRTOS.com - Commercial support, development, porting,
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licensing and training services.
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*/
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/* Standard includes. */
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#include <string.h>
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/* Scheduler includes. */
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#include "FreeRTOS.h"
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#include "semphr.h"
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#include "task.h"
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/* Demo application includes. */
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#include "SAM7_EMAC.h"
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/* uIP includes. */
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#include "uip.h"
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/* Hardware specific includes. */
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#include "Emac.h"
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#include "mii.h"
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#include "AT91SAM7X256.h"
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/* USE_RMII_INTERFACE must be defined as 1 to use an RMII interface, or 0
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to use an MII interface. */
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#define USE_RMII_INTERFACE 0
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/* The buffer addresses written into the descriptors must be aligned so the
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last few bits are zero. These bits have special meaning for the EMAC
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peripheral and cannot be used as part of the address. */
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#define emacADDRESS_MASK ( ( unsigned long ) 0xFFFFFFFC )
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/* Bit used within the address stored in the descriptor to mark the last
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descriptor in the array. */
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#define emacRX_WRAP_BIT ( ( unsigned long ) 0x02 )
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/* Bit used within the Tx descriptor status to indicate whether the
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descriptor is under the control of the EMAC or the software. */
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#define emacTX_BUF_USED ( ( unsigned long ) 0x80000000 )
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/* A short delay is used to wait for a buffer to become available, should
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one not be immediately available when trying to transmit a frame. */
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#define emacBUFFER_WAIT_DELAY ( 2 )
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#define emacMAX_WAIT_CYCLES ( configTICK_RATE_HZ / 40 )
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/* Misc defines. */
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#define emacINTERRUPT_LEVEL ( 5 )
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#define emacNO_DELAY ( 0 )
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#define emacTOTAL_FRAME_HEADER_SIZE ( 54 )
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#define emacPHY_INIT_DELAY ( 5000 / portTICK_RATE_MS )
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#define emacRESET_KEY ( ( unsigned long ) 0xA5000000 )
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#define emacRESET_LENGTH ( ( unsigned long ) ( 0x01 << 8 ) )
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/* The Atmel header file only defines the TX frame length mask. */
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#define emacRX_LENGTH_FRAME ( 0xfff )
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/* Peripheral setup for the EMAC. */
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#define emacPERIPHERAL_A_SETUP ( ( unsigned long ) AT91C_PB2_ETX0 ) | \
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( ( unsigned long ) AT91C_PB12_ETXER ) | \
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( ( unsigned long ) AT91C_PB16_ECOL ) | \
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( ( unsigned long ) AT91C_PB11_ETX3 ) | \
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( ( unsigned long ) AT91C_PB6_ERX1 ) | \
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( ( unsigned long ) AT91C_PB15_ERXDV ) | \
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( ( unsigned long ) AT91C_PB13_ERX2 ) | \
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( ( unsigned long ) AT91C_PB3_ETX1 ) | \
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( ( unsigned long ) AT91C_PB8_EMDC ) | \
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( ( unsigned long ) AT91C_PB5_ERX0 ) | \
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( ( unsigned long ) AT91C_PB14_ERX3 ) | \
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( ( unsigned long ) AT91C_PB4_ECRS_ECRSDV ) | \
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( ( unsigned long ) AT91C_PB1_ETXEN ) | \
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( ( unsigned long ) AT91C_PB10_ETX2 ) | \
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( ( unsigned long ) AT91C_PB0_ETXCK_EREFCK ) | \
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( ( unsigned long ) AT91C_PB9_EMDIO ) | \
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( ( unsigned long ) AT91C_PB7_ERXER ) | \
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( ( unsigned long ) AT91C_PB17_ERXCK );
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/*-----------------------------------------------------------*/
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/*
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* Prototype for the EMAC interrupt function - called by the asm wrapper.
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*/
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extern void vEMACISR_Wrapper( void ) __attribute__((naked));
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/*
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* Initialise both the Tx and Rx descriptors used by the EMAC.
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*/
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static void prvSetupDescriptors(void);
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/*
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* Write our MAC address into the EMAC. The MAC address is set as one of the
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* uip options.
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*/
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static void prvSetupMACAddress( void );
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/*
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* Configure the EMAC and AIC for EMAC interrupts.
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*/
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static void prvSetupEMACInterrupt( void );
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/*
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* Some initialisation functions taken from the Atmel EMAC sample code.
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*/
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static void vReadPHY( unsigned char ucPHYAddress, unsigned char ucAddress, unsigned long *pulValue );
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#if USE_RMII_INTERFACE != 1
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static void vWritePHY( unsigned char ucPHYAddress, unsigned char ucAddress, unsigned long ulValue);
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#endif
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static portBASE_TYPE xGetLinkSpeed( void );
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static portBASE_TYPE prvProbePHY( void );
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/*-----------------------------------------------------------*/
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/* Buffer written to by the EMAC DMA. Must be aligned as described by the
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comment above the emacADDRESS_MASK definition. */
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#pragma data_alignment=8
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static volatile char pcRxBuffer[ NB_RX_BUFFERS * ETH_RX_BUFFER_SIZE ];
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/* Buffer read by the EMAC DMA. Must be aligned as described by he comment
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above the emacADDRESS_MASK definition. */
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#pragma data_alignment=8
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static char pcTxBuffer[ NB_TX_BUFFERS * ETH_TX_BUFFER_SIZE ];
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/* Descriptors used to communicate between the program and the EMAC peripheral.
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These descriptors hold the locations and state of the Rx and Tx buffers. */
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static volatile AT91S_TxTdDescriptor xTxDescriptors[ NB_TX_BUFFERS ];
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static volatile AT91S_RxTdDescriptor xRxDescriptors[ NB_RX_BUFFERS ];
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/* The IP and Ethernet addresses are read from the uIP setup. */
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const char cMACAddress[ 6 ] = { uipMAC_ADDR0, uipMAC_ADDR1, uipMAC_ADDR2, uipMAC_ADDR3, uipMAC_ADDR4, uipMAC_ADDR5 };
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const unsigned char ucIPAddress[ 4 ] = { uipIP_ADDR0, uipIP_ADDR1, uipIP_ADDR2, uipIP_ADDR3 };
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/* The semaphore used by the EMAC ISR to wake the EMAC task. */
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static xSemaphoreHandle xSemaphore = NULL;
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/*-----------------------------------------------------------*/
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xSemaphoreHandle xEMACInit( void )
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{
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/* Code supplied by Atmel -------------------------------*/
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/* Disable pull up on RXDV => PHY normal mode (not in test mode),
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PHY has internal pull down. */
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AT91C_BASE_PIOB->PIO_PPUDR = 1 << 15;
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#if USE_RMII_INTERFACE != 1
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/* PHY has internal pull down : set MII mode. */
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AT91C_BASE_PIOB->PIO_PPUDR = 1 << 16;
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#endif
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/* Clear PB18 <=> PHY powerdown. */
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AT91C_BASE_PIOB->PIO_PER = 1 << 18;
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AT91C_BASE_PIOB->PIO_OER = 1 << 18;
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AT91C_BASE_PIOB->PIO_CODR = 1 << 18;
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/* After PHY power up, hardware reset. */
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AT91C_BASE_RSTC->RSTC_RMR = emacRESET_KEY | emacRESET_LENGTH;
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AT91C_BASE_RSTC->RSTC_RCR = emacRESET_KEY | AT91C_RSTC_EXTRST;
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/* Wait for hardware reset end. */
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while( !( AT91C_BASE_RSTC->RSTC_RSR & AT91C_RSTC_NRSTL ) )
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{
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__asm volatile ( "NOP" );
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}
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__asm volatile ( "NOP" );
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/* Setup the pins. */
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AT91C_BASE_PIOB->PIO_ASR = emacPERIPHERAL_A_SETUP;
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AT91C_BASE_PIOB->PIO_PDR = emacPERIPHERAL_A_SETUP;
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/* Enable com between EMAC PHY.
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Enable management port. */
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AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE;
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/* MDC = MCK/32. */
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AT91C_BASE_EMAC->EMAC_NCFGR |= ( 2 ) << 10;
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/* Wait for PHY auto init end (rather crude delay!). */
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vTaskDelay( emacPHY_INIT_DELAY );
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/* PHY configuration. */
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#if USE_RMII_INTERFACE != 1
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{
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unsigned long ulControl;
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/* PHY has internal pull down : disable MII isolate. */
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vReadPHY( AT91C_PHY_ADDR, MII_BMCR, &ulControl );
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vReadPHY( AT91C_PHY_ADDR, MII_BMCR, &ulControl );
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ulControl &= ~BMCR_ISOLATE;
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vWritePHY( AT91C_PHY_ADDR, MII_BMCR, ulControl );
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}
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#endif
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/* Disable management port again. */
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AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE;
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#if USE_RMII_INTERFACE != 1
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/* Enable EMAC in MII mode, enable clock ERXCK and ETXCK. */
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AT91C_BASE_EMAC->EMAC_USRIO = AT91C_EMAC_CLKEN ;
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#else
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/* Enable EMAC in RMII mode, enable RMII clock (50MHz from oscillator
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on ERFCK). */
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AT91C_BASE_EMAC->EMAC_USRIO = AT91C_EMAC_RMII | AT91C_EMAC_CLKEN ;
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#endif
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/* End of code supplied by Atmel ------------------------*/
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/* Setup the buffers and descriptors. */
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prvSetupDescriptors();
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/* Load our MAC address into the EMAC. */
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prvSetupMACAddress();
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/* Are we connected? */
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if( prvProbePHY() )
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{
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/* Enable the interrupt! */
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portENTER_CRITICAL();
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{
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prvSetupEMACInterrupt();
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vPassEMACSemaphore( xSemaphore );
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}
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portEXIT_CRITICAL();
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}
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| 274 |
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return xSemaphore;
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}
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/*-----------------------------------------------------------*/
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| 278 |
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| 279 |
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long lEMACSend( void )
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| 280 |
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{
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| 281 |
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static unsigned portBASE_TYPE uxTxBufferIndex = 0;
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| 282 |
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portBASE_TYPE xWaitCycles = 0;
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| 283 |
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long lReturn = pdPASS;
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| 284 |
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char *pcBuffer;
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| 285 |
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| 286 |
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/* Is a buffer available? */
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| 287 |
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while( !( xTxDescriptors[ uxTxBufferIndex ].U_Status.status & AT91C_TRANSMIT_OK ) )
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| 288 |
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{
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| 289 |
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/* There is no room to write the Tx data to the Tx buffer. Wait a
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| 290 |
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short while, then try again. */
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| 291 |
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xWaitCycles++;
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| 292 |
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if( xWaitCycles > emacMAX_WAIT_CYCLES )
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{
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| 294 |
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/* Give up. */
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lReturn = pdFAIL;
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break;
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| 297 |
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}
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| 298 |
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else
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| 299 |
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{
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| 300 |
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vTaskDelay( emacBUFFER_WAIT_DELAY );
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| 301 |
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}
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| 302 |
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}
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| 303 |
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| 304 |
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/* lReturn will only be pdPASS if a buffer is available. */
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| 305 |
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if( lReturn == pdPASS )
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| 306 |
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{
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| 307 |
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/* Copy the headers into the Tx buffer. These will be in the uIP buffer. */
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| 308 |
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pcBuffer = ( char * ) xTxDescriptors[ uxTxBufferIndex ].addr;
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| 309 |
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memcpy( ( void * ) pcBuffer, ( void * ) uip_buf, emacTOTAL_FRAME_HEADER_SIZE );
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| 310 |
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| 311 |
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/* If there is room, also copy in the application data if any. */
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| 312 |
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if( ( uip_len > emacTOTAL_FRAME_HEADER_SIZE ) && ( uip_len <= ( ETH_TX_BUFFER_SIZE - emacTOTAL_FRAME_HEADER_SIZE ) ) )
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| 313 |
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{
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| 314 |
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memcpy( ( void * ) &( pcBuffer[ emacTOTAL_FRAME_HEADER_SIZE ] ), ( void * ) uip_appdata, ( uip_len - emacTOTAL_FRAME_HEADER_SIZE ) );
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| 315 |
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}
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| 316 |
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| 317 |
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/* Send. */
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| 318 |
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portENTER_CRITICAL();
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| 319 |
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{
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| 320 |
|
|
if( uxTxBufferIndex >= ( NB_TX_BUFFERS - 1 ) )
|
| 321 |
|
|
{
|
| 322 |
|
|
/* Fill out the necessary in the descriptor to get the data sent. */
|
| 323 |
|
|
xTxDescriptors[ uxTxBufferIndex ].U_Status.status = ( uip_len & ( unsigned long ) AT91C_LENGTH_FRAME )
|
| 324 |
|
|
| AT91C_LAST_BUFFER
|
| 325 |
|
|
| AT91C_TRANSMIT_WRAP;
|
| 326 |
|
|
uxTxBufferIndex = 0;
|
| 327 |
|
|
}
|
| 328 |
|
|
else
|
| 329 |
|
|
{
|
| 330 |
|
|
/* Fill out the necessary in the descriptor to get the data sent. */
|
| 331 |
|
|
xTxDescriptors[ uxTxBufferIndex ].U_Status.status = ( uip_len & ( unsigned long ) AT91C_LENGTH_FRAME )
|
| 332 |
|
|
| AT91C_LAST_BUFFER;
|
| 333 |
|
|
uxTxBufferIndex++;
|
| 334 |
|
|
}
|
| 335 |
|
|
|
| 336 |
|
|
AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_TSTART;
|
| 337 |
|
|
}
|
| 338 |
|
|
portEXIT_CRITICAL();
|
| 339 |
|
|
}
|
| 340 |
|
|
|
| 341 |
|
|
return lReturn;
|
| 342 |
|
|
}
|
| 343 |
|
|
/*-----------------------------------------------------------*/
|
| 344 |
|
|
|
| 345 |
|
|
unsigned long ulEMACPoll( void )
|
| 346 |
|
|
{
|
| 347 |
|
|
static unsigned portBASE_TYPE ulNextRxBuffer = 0;
|
| 348 |
|
|
unsigned long ulSectionLength = 0, ulLengthSoFar = 0, ulEOF = pdFALSE;
|
| 349 |
|
|
char *pcSource;
|
| 350 |
|
|
|
| 351 |
|
|
/* Skip any fragments. */
|
| 352 |
|
|
while( ( xRxDescriptors[ ulNextRxBuffer ].addr & AT91C_OWNERSHIP_BIT ) && !( xRxDescriptors[ ulNextRxBuffer ].U_Status.status & AT91C_SOF ) )
|
| 353 |
|
|
{
|
| 354 |
|
|
/* Mark the buffer as free again. */
|
| 355 |
|
|
xRxDescriptors[ ulNextRxBuffer ].addr &= ~( AT91C_OWNERSHIP_BIT );
|
| 356 |
|
|
ulNextRxBuffer++;
|
| 357 |
|
|
if( ulNextRxBuffer >= NB_RX_BUFFERS )
|
| 358 |
|
|
{
|
| 359 |
|
|
ulNextRxBuffer = 0;
|
| 360 |
|
|
}
|
| 361 |
|
|
}
|
| 362 |
|
|
|
| 363 |
|
|
/* Is there a packet ready? */
|
| 364 |
|
|
|
| 365 |
|
|
while( ( xRxDescriptors[ ulNextRxBuffer ].addr & AT91C_OWNERSHIP_BIT ) && !ulSectionLength )
|
| 366 |
|
|
{
|
| 367 |
|
|
pcSource = ( char * )( xRxDescriptors[ ulNextRxBuffer ].addr & emacADDRESS_MASK );
|
| 368 |
|
|
ulSectionLength = xRxDescriptors[ ulNextRxBuffer ].U_Status.status & emacRX_LENGTH_FRAME;
|
| 369 |
|
|
|
| 370 |
|
|
if( ulSectionLength == 0 )
|
| 371 |
|
|
{
|
| 372 |
|
|
/* The frame is longer than the buffer pointed to by this
|
| 373 |
|
|
descriptor so copy the entire buffer to uIP - then move onto
|
| 374 |
|
|
the next descriptor to get the rest of the frame. */
|
| 375 |
|
|
if( ( ulLengthSoFar + ETH_RX_BUFFER_SIZE ) <= UIP_BUFSIZE )
|
| 376 |
|
|
{
|
| 377 |
|
|
memcpy( &( uip_buf[ ulLengthSoFar ] ), pcSource, ETH_RX_BUFFER_SIZE );
|
| 378 |
|
|
ulLengthSoFar += ETH_RX_BUFFER_SIZE;
|
| 379 |
|
|
}
|
| 380 |
|
|
}
|
| 381 |
|
|
else
|
| 382 |
|
|
{
|
| 383 |
|
|
/* This is the last section of the frame. Copy the section to
|
| 384 |
|
|
uIP. */
|
| 385 |
|
|
if( ulSectionLength < UIP_BUFSIZE )
|
| 386 |
|
|
{
|
| 387 |
|
|
/* The section length holds the length of the entire frame.
|
| 388 |
|
|
ulLengthSoFar holds the length of the frame sections already
|
| 389 |
|
|
copied to uIP, so the length of the final section is
|
| 390 |
|
|
ulSectionLength - ulLengthSoFar; */
|
| 391 |
|
|
if( ulSectionLength > ulLengthSoFar )
|
| 392 |
|
|
{
|
| 393 |
|
|
memcpy( &( uip_buf[ ulLengthSoFar ] ), pcSource, ( ulSectionLength - ulLengthSoFar ) );
|
| 394 |
|
|
}
|
| 395 |
|
|
}
|
| 396 |
|
|
|
| 397 |
|
|
/* Is this the last buffer for the frame? If not why? */
|
| 398 |
|
|
ulEOF = xRxDescriptors[ ulNextRxBuffer ].U_Status.status & AT91C_EOF;
|
| 399 |
|
|
}
|
| 400 |
|
|
|
| 401 |
|
|
/* Mark the buffer as free again. */
|
| 402 |
|
|
xRxDescriptors[ ulNextRxBuffer ].addr &= ~( AT91C_OWNERSHIP_BIT );
|
| 403 |
|
|
|
| 404 |
|
|
/* Increment to the next buffer, wrapping if necessary. */
|
| 405 |
|
|
ulNextRxBuffer++;
|
| 406 |
|
|
if( ulNextRxBuffer >= NB_RX_BUFFERS )
|
| 407 |
|
|
{
|
| 408 |
|
|
ulNextRxBuffer = 0;
|
| 409 |
|
|
}
|
| 410 |
|
|
}
|
| 411 |
|
|
|
| 412 |
|
|
/* If we obtained data but for some reason did not find the end of the
|
| 413 |
|
|
frame then discard the data as it must contain an error. */
|
| 414 |
|
|
if( !ulEOF )
|
| 415 |
|
|
{
|
| 416 |
|
|
ulSectionLength = 0;
|
| 417 |
|
|
}
|
| 418 |
|
|
|
| 419 |
|
|
return ulSectionLength;
|
| 420 |
|
|
}
|
| 421 |
|
|
/*-----------------------------------------------------------*/
|
| 422 |
|
|
|
| 423 |
|
|
static void prvSetupDescriptors(void)
|
| 424 |
|
|
{
|
| 425 |
|
|
unsigned portBASE_TYPE xIndex;
|
| 426 |
|
|
unsigned long ulAddress;
|
| 427 |
|
|
|
| 428 |
|
|
/* Initialise xRxDescriptors descriptor. */
|
| 429 |
|
|
for( xIndex = 0; xIndex < NB_RX_BUFFERS; ++xIndex )
|
| 430 |
|
|
{
|
| 431 |
|
|
/* Calculate the address of the nth buffer within the array. */
|
| 432 |
|
|
ulAddress = ( unsigned long )( pcRxBuffer + ( xIndex * ETH_RX_BUFFER_SIZE ) );
|
| 433 |
|
|
|
| 434 |
|
|
/* Write the buffer address into the descriptor. The DMA will place
|
| 435 |
|
|
the data at this address when this descriptor is being used. Mask off
|
| 436 |
|
|
the bottom bits of the address as these have special meaning. */
|
| 437 |
|
|
xRxDescriptors[ xIndex ].addr = ulAddress & emacADDRESS_MASK;
|
| 438 |
|
|
}
|
| 439 |
|
|
|
| 440 |
|
|
/* The last buffer has the wrap bit set so the EMAC knows to wrap back
|
| 441 |
|
|
to the first buffer. */
|
| 442 |
|
|
xRxDescriptors[ NB_RX_BUFFERS - 1 ].addr |= emacRX_WRAP_BIT;
|
| 443 |
|
|
|
| 444 |
|
|
/* Initialise xTxDescriptors. */
|
| 445 |
|
|
for( xIndex = 0; xIndex < NB_TX_BUFFERS; ++xIndex )
|
| 446 |
|
|
{
|
| 447 |
|
|
/* Calculate the address of the nth buffer within the array. */
|
| 448 |
|
|
ulAddress = ( unsigned long )( pcTxBuffer + ( xIndex * ETH_TX_BUFFER_SIZE ) );
|
| 449 |
|
|
|
| 450 |
|
|
/* Write the buffer address into the descriptor. The DMA will read
|
| 451 |
|
|
data from here when the descriptor is being used. */
|
| 452 |
|
|
xTxDescriptors[ xIndex ].addr = ulAddress & emacADDRESS_MASK;
|
| 453 |
|
|
xTxDescriptors[ xIndex ].U_Status.status = AT91C_TRANSMIT_OK;
|
| 454 |
|
|
}
|
| 455 |
|
|
|
| 456 |
|
|
/* The last buffer has the wrap bit set so the EMAC knows to wrap back
|
| 457 |
|
|
to the first buffer. */
|
| 458 |
|
|
xTxDescriptors[ NB_TX_BUFFERS - 1 ].U_Status.status = AT91C_TRANSMIT_WRAP | AT91C_TRANSMIT_OK;
|
| 459 |
|
|
|
| 460 |
|
|
/* Tell the EMAC where to find the descriptors. */
|
| 461 |
|
|
AT91C_BASE_EMAC->EMAC_RBQP = ( unsigned long ) xRxDescriptors;
|
| 462 |
|
|
AT91C_BASE_EMAC->EMAC_TBQP = ( unsigned long ) xTxDescriptors;
|
| 463 |
|
|
|
| 464 |
|
|
/* Clear all the bits in the receive status register. */
|
| 465 |
|
|
AT91C_BASE_EMAC->EMAC_RSR = ( AT91C_EMAC_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA );
|
| 466 |
|
|
|
| 467 |
|
|
/* Enable the copy of data into the buffers, ignore broadcasts,
|
| 468 |
|
|
and don't copy FCS. */
|
| 469 |
|
|
AT91C_BASE_EMAC->EMAC_NCFGR |= ( AT91C_EMAC_CAF | AT91C_EMAC_NBC | AT91C_EMAC_DRFCS);
|
| 470 |
|
|
|
| 471 |
|
|
/* Enable Rx and Tx, plus the stats register. */
|
| 472 |
|
|
AT91C_BASE_EMAC->EMAC_NCR |= ( AT91C_EMAC_TE | AT91C_EMAC_RE | AT91C_EMAC_WESTAT );
|
| 473 |
|
|
}
|
| 474 |
|
|
/*-----------------------------------------------------------*/
|
| 475 |
|
|
|
| 476 |
|
|
static void prvSetupMACAddress( void )
|
| 477 |
|
|
{
|
| 478 |
|
|
/* Must be written SA1L then SA1H. */
|
| 479 |
|
|
AT91C_BASE_EMAC->EMAC_SA1L = ( ( unsigned long ) cMACAddress[ 3 ] << 24 ) |
|
| 480 |
|
|
( ( unsigned long ) cMACAddress[ 2 ] << 16 ) |
|
| 481 |
|
|
( ( unsigned long ) cMACAddress[ 1 ] << 8 ) |
|
| 482 |
|
|
cMACAddress[ 0 ];
|
| 483 |
|
|
|
| 484 |
|
|
AT91C_BASE_EMAC->EMAC_SA1H = ( ( unsigned long ) cMACAddress[ 5 ] << 8 ) |
|
| 485 |
|
|
cMACAddress[ 4 ];
|
| 486 |
|
|
}
|
| 487 |
|
|
/*-----------------------------------------------------------*/
|
| 488 |
|
|
|
| 489 |
|
|
static void prvSetupEMACInterrupt( void )
|
| 490 |
|
|
{
|
| 491 |
|
|
/* Create the semaphore used to trigger the EMAC task. */
|
| 492 |
|
|
vSemaphoreCreateBinary( xSemaphore );
|
| 493 |
|
|
if( xSemaphore )
|
| 494 |
|
|
{
|
| 495 |
|
|
/* We start by 'taking' the semaphore so the ISR can 'give' it when the
|
| 496 |
|
|
first interrupt occurs. */
|
| 497 |
|
|
xSemaphoreTake( xSemaphore, emacNO_DELAY );
|
| 498 |
|
|
portENTER_CRITICAL();
|
| 499 |
|
|
{
|
| 500 |
|
|
/* We want to interrupt on Rx events. */
|
| 501 |
|
|
AT91C_BASE_EMAC->EMAC_IER = AT91C_EMAC_RCOMP;
|
| 502 |
|
|
|
| 503 |
|
|
/* Enable the interrupts in the AIC. */
|
| 504 |
|
|
AT91F_AIC_ConfigureIt( AT91C_ID_EMAC, emacINTERRUPT_LEVEL, AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL, ( void (*)( void ) ) vEMACISR_Wrapper );
|
| 505 |
|
|
AT91C_BASE_AIC->AIC_IECR = 0x1 << AT91C_ID_EMAC;
|
| 506 |
|
|
}
|
| 507 |
|
|
portEXIT_CRITICAL();
|
| 508 |
|
|
}
|
| 509 |
|
|
}
|
| 510 |
|
|
/*-----------------------------------------------------------*/
|
| 511 |
|
|
|
| 512 |
|
|
|
| 513 |
|
|
|
| 514 |
|
|
|
| 515 |
|
|
/*
|
| 516 |
|
|
* The following functions are initialisation functions taken from the Atmel
|
| 517 |
|
|
* EMAC sample code.
|
| 518 |
|
|
*/
|
| 519 |
|
|
|
| 520 |
|
|
static portBASE_TYPE prvProbePHY( void )
|
| 521 |
|
|
{
|
| 522 |
|
|
unsigned long ulPHYId1, ulPHYId2, ulStatus;
|
| 523 |
|
|
portBASE_TYPE xReturn = pdPASS;
|
| 524 |
|
|
|
| 525 |
|
|
/* Code supplied by Atmel (reformatted) -----------------*/
|
| 526 |
|
|
|
| 527 |
|
|
/* Enable management port */
|
| 528 |
|
|
AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE;
|
| 529 |
|
|
AT91C_BASE_EMAC->EMAC_NCFGR |= ( 2 ) << 10;
|
| 530 |
|
|
|
| 531 |
|
|
/* Read the PHY ID. */
|
| 532 |
|
|
vReadPHY( AT91C_PHY_ADDR, MII_PHYSID1, &ulPHYId1 );
|
| 533 |
|
|
vReadPHY( AT91C_PHY_ADDR, MII_PHYSID2, &ulPHYId2 );
|
| 534 |
|
|
|
| 535 |
|
|
/* AMD AM79C875:
|
| 536 |
|
|
PHY_ID1 = 0x0022
|
| 537 |
|
|
PHY_ID2 = 0x5541
|
| 538 |
|
|
Bits 3:0 Revision Number Four bit manufacturer’s revision number.
|
| 539 |
|
|
0001 stands for Rev. A, etc.
|
| 540 |
|
|
*/
|
| 541 |
|
|
if( ( ( ulPHYId1 << 16 ) | ( ulPHYId2 & 0xfff0 ) ) != MII_DM9161_ID )
|
| 542 |
|
|
{
|
| 543 |
|
|
/* Did not expect this ID. */
|
| 544 |
|
|
xReturn = pdFAIL;
|
| 545 |
|
|
}
|
| 546 |
|
|
else
|
| 547 |
|
|
{
|
| 548 |
|
|
ulStatus = xGetLinkSpeed();
|
| 549 |
|
|
|
| 550 |
|
|
if( ulStatus != pdPASS )
|
| 551 |
|
|
{
|
| 552 |
|
|
xReturn = pdFAIL;
|
| 553 |
|
|
}
|
| 554 |
|
|
}
|
| 555 |
|
|
|
| 556 |
|
|
/* Disable management port */
|
| 557 |
|
|
AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE;
|
| 558 |
|
|
|
| 559 |
|
|
/* End of code supplied by Atmel ------------------------*/
|
| 560 |
|
|
|
| 561 |
|
|
return xReturn;
|
| 562 |
|
|
}
|
| 563 |
|
|
/*-----------------------------------------------------------*/
|
| 564 |
|
|
|
| 565 |
|
|
static void vReadPHY( unsigned char ucPHYAddress, unsigned char ucAddress, unsigned long *pulValue )
|
| 566 |
|
|
{
|
| 567 |
|
|
/* Code supplied by Atmel (reformatted) ----------------------*/
|
| 568 |
|
|
|
| 569 |
|
|
AT91C_BASE_EMAC->EMAC_MAN = (AT91C_EMAC_SOF & (0x01<<30))
|
| 570 |
|
|
| (2 << 16) | (2 << 28)
|
| 571 |
|
|
| ((ucPHYAddress & 0x1f) << 23)
|
| 572 |
|
|
| (ucAddress << 18);
|
| 573 |
|
|
|
| 574 |
|
|
/* Wait until IDLE bit in Network Status register is cleared. */
|
| 575 |
|
|
while( !( AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE ) )
|
| 576 |
|
|
{
|
| 577 |
|
|
__asm( "NOP" );
|
| 578 |
|
|
}
|
| 579 |
|
|
|
| 580 |
|
|
*pulValue = ( AT91C_BASE_EMAC->EMAC_MAN & 0x0000ffff );
|
| 581 |
|
|
|
| 582 |
|
|
/* End of code supplied by Atmel ------------------------*/
|
| 583 |
|
|
}
|
| 584 |
|
|
/*-----------------------------------------------------------*/
|
| 585 |
|
|
|
| 586 |
|
|
#if USE_RMII_INTERFACE != 1
|
| 587 |
|
|
static void vWritePHY( unsigned char ucPHYAddress, unsigned char ucAddress, unsigned long ulValue )
|
| 588 |
|
|
{
|
| 589 |
|
|
/* Code supplied by Atmel (reformatted) ----------------------*/
|
| 590 |
|
|
|
| 591 |
|
|
AT91C_BASE_EMAC->EMAC_MAN = (( AT91C_EMAC_SOF & (0x01<<30))
|
| 592 |
|
|
| (2 << 16) | (1 << 28)
|
| 593 |
|
|
| ((ucPHYAddress & 0x1f) << 23)
|
| 594 |
|
|
| (ucAddress << 18))
|
| 595 |
|
|
| (ulValue & 0xffff);
|
| 596 |
|
|
|
| 597 |
|
|
/* Wait until IDLE bit in Network Status register is cleared */
|
| 598 |
|
|
while( !( AT91C_BASE_EMAC->EMAC_NSR & AT91C_EMAC_IDLE ) )
|
| 599 |
|
|
{
|
| 600 |
|
|
__asm( "NOP" );
|
| 601 |
|
|
};
|
| 602 |
|
|
|
| 603 |
|
|
/* End of code supplied by Atmel ------------------------*/
|
| 604 |
|
|
}
|
| 605 |
|
|
#endif
|
| 606 |
|
|
/*-----------------------------------------------------------*/
|
| 607 |
|
|
|
| 608 |
|
|
static portBASE_TYPE xGetLinkSpeed( void )
|
| 609 |
|
|
{
|
| 610 |
|
|
unsigned long ulBMSR, ulBMCR, ulLPA, ulMACCfg, ulSpeed, ulDuplex;
|
| 611 |
|
|
|
| 612 |
|
|
/* Code supplied by Atmel (reformatted) -----------------*/
|
| 613 |
|
|
|
| 614 |
|
|
/* Link status is latched, so read twice to get current value */
|
| 615 |
|
|
vReadPHY(AT91C_PHY_ADDR, MII_BMSR, &ulBMSR);
|
| 616 |
|
|
vReadPHY(AT91C_PHY_ADDR, MII_BMSR, &ulBMSR);
|
| 617 |
|
|
|
| 618 |
|
|
if( !( ulBMSR & BMSR_LSTATUS ) )
|
| 619 |
|
|
{
|
| 620 |
|
|
/* No Link. */
|
| 621 |
|
|
return pdFAIL;
|
| 622 |
|
|
}
|
| 623 |
|
|
|
| 624 |
|
|
vReadPHY(AT91C_PHY_ADDR, MII_BMCR, &ulBMCR);
|
| 625 |
|
|
if (ulBMCR & BMCR_ANENABLE)
|
| 626 |
|
|
{
|
| 627 |
|
|
/* AutoNegotiation is enabled. */
|
| 628 |
|
|
if (!(ulBMSR & BMSR_ANEGCOMPLETE))
|
| 629 |
|
|
{
|
| 630 |
|
|
/* Auto-negotiation in progress. */
|
| 631 |
|
|
return pdFAIL;
|
| 632 |
|
|
}
|
| 633 |
|
|
|
| 634 |
|
|
vReadPHY(AT91C_PHY_ADDR, MII_LPA, &ulLPA);
|
| 635 |
|
|
if( ( ulLPA & LPA_100FULL ) || ( ulLPA & LPA_100HALF ) )
|
| 636 |
|
|
{
|
| 637 |
|
|
ulSpeed = SPEED_100;
|
| 638 |
|
|
}
|
| 639 |
|
|
else
|
| 640 |
|
|
{
|
| 641 |
|
|
ulSpeed = SPEED_10;
|
| 642 |
|
|
}
|
| 643 |
|
|
|
| 644 |
|
|
if( ( ulLPA & LPA_100FULL ) || ( ulLPA & LPA_10FULL ) )
|
| 645 |
|
|
{
|
| 646 |
|
|
ulDuplex = DUPLEX_FULL;
|
| 647 |
|
|
}
|
| 648 |
|
|
else
|
| 649 |
|
|
{
|
| 650 |
|
|
ulDuplex = DUPLEX_HALF;
|
| 651 |
|
|
}
|
| 652 |
|
|
}
|
| 653 |
|
|
else
|
| 654 |
|
|
{
|
| 655 |
|
|
ulSpeed = ( ulBMCR & BMCR_SPEED100 ) ? SPEED_100 : SPEED_10;
|
| 656 |
|
|
ulDuplex = ( ulBMCR & BMCR_FULLDPLX ) ? DUPLEX_FULL : DUPLEX_HALF;
|
| 657 |
|
|
}
|
| 658 |
|
|
|
| 659 |
|
|
/* Update the MAC */
|
| 660 |
|
|
ulMACCfg = AT91C_BASE_EMAC->EMAC_NCFGR & ~( AT91C_EMAC_SPD | AT91C_EMAC_FD );
|
| 661 |
|
|
if( ulSpeed == SPEED_100 )
|
| 662 |
|
|
{
|
| 663 |
|
|
if( ulDuplex == DUPLEX_FULL )
|
| 664 |
|
|
{
|
| 665 |
|
|
/* 100 Full Duplex */
|
| 666 |
|
|
AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_SPD | AT91C_EMAC_FD;
|
| 667 |
|
|
}
|
| 668 |
|
|
else
|
| 669 |
|
|
{
|
| 670 |
|
|
/* 100 Half Duplex */
|
| 671 |
|
|
AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_SPD;
|
| 672 |
|
|
}
|
| 673 |
|
|
}
|
| 674 |
|
|
else
|
| 675 |
|
|
{
|
| 676 |
|
|
if (ulDuplex == DUPLEX_FULL)
|
| 677 |
|
|
{
|
| 678 |
|
|
/* 10 Full Duplex */
|
| 679 |
|
|
AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg | AT91C_EMAC_FD;
|
| 680 |
|
|
}
|
| 681 |
|
|
else
|
| 682 |
|
|
{
|
| 683 |
|
|
/* 10 Half Duplex */
|
| 684 |
|
|
AT91C_BASE_EMAC->EMAC_NCFGR = ulMACCfg;
|
| 685 |
|
|
}
|
| 686 |
|
|
}
|
| 687 |
|
|
|
| 688 |
|
|
/* End of code supplied by Atmel ------------------------*/
|
| 689 |
|
|
|
| 690 |
|
|
return pdPASS;
|
| 691 |
|
|
}
|
