OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [ARM7_LPC2106_GCC/] [ram_arm.bat] - Blame information for rev 577

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 577 jeremybenn
set USE_THUMB_MODE=NO
2
set DEBUG=-g
3
set OPTIM=-O0
4
set RUN_MODE=RUN_FROM_RAM
5
set LDSCRIPT=lpc2106-ram.ld
6
make

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.