| 1 |
577 |
jeremybenn |
/*
|
| 2 |
|
|
FreeRTOS V6.1.1 - Copyright (C) 2011 Real Time Engineers Ltd.
|
| 3 |
|
|
|
| 4 |
|
|
***************************************************************************
|
| 5 |
|
|
* *
|
| 6 |
|
|
* If you are: *
|
| 7 |
|
|
* *
|
| 8 |
|
|
* + New to FreeRTOS, *
|
| 9 |
|
|
* + Wanting to learn FreeRTOS or multitasking in general quickly *
|
| 10 |
|
|
* + Looking for basic training, *
|
| 11 |
|
|
* + Wanting to improve your FreeRTOS skills and productivity *
|
| 12 |
|
|
* *
|
| 13 |
|
|
* then take a look at the FreeRTOS books - available as PDF or paperback *
|
| 14 |
|
|
* *
|
| 15 |
|
|
* "Using the FreeRTOS Real Time Kernel - a Practical Guide" *
|
| 16 |
|
|
* http://www.FreeRTOS.org/Documentation *
|
| 17 |
|
|
* *
|
| 18 |
|
|
* A pdf reference manual is also available. Both are usually delivered *
|
| 19 |
|
|
* to your inbox within 20 minutes to two hours when purchased between 8am *
|
| 20 |
|
|
* and 8pm GMT (although please allow up to 24 hours in case of *
|
| 21 |
|
|
* exceptional circumstances). Thank you for your support! *
|
| 22 |
|
|
* *
|
| 23 |
|
|
***************************************************************************
|
| 24 |
|
|
|
| 25 |
|
|
This file is part of the FreeRTOS distribution.
|
| 26 |
|
|
|
| 27 |
|
|
FreeRTOS is free software; you can redistribute it and/or modify it under
|
| 28 |
|
|
the terms of the GNU General Public License (version 2) as published by the
|
| 29 |
|
|
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
|
| 30 |
|
|
***NOTE*** The exception to the GPL is included to allow you to distribute
|
| 31 |
|
|
a combined work that includes FreeRTOS without being obliged to provide the
|
| 32 |
|
|
source code for proprietary components outside of the FreeRTOS kernel.
|
| 33 |
|
|
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT
|
| 34 |
|
|
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
| 35 |
|
|
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
| 36 |
|
|
more details. You should have received a copy of the GNU General Public
|
| 37 |
|
|
License and the FreeRTOS license exception along with FreeRTOS; if not it
|
| 38 |
|
|
can be viewed here: http://www.freertos.org/a00114.html and also obtained
|
| 39 |
|
|
by writing to Richard Barry, contact details for whom are available on the
|
| 40 |
|
|
FreeRTOS WEB site.
|
| 41 |
|
|
|
| 42 |
|
|
1 tab == 4 spaces!
|
| 43 |
|
|
|
| 44 |
|
|
http://www.FreeRTOS.org - Documentation, latest information, license and
|
| 45 |
|
|
contact details.
|
| 46 |
|
|
|
| 47 |
|
|
http://www.SafeRTOS.com - A version that is certified for use in safety
|
| 48 |
|
|
critical systems.
|
| 49 |
|
|
|
| 50 |
|
|
http://www.OpenRTOS.com - Commercial support, development, porting,
|
| 51 |
|
|
licensing and training services.
|
| 52 |
|
|
*/
|
| 53 |
|
|
|
| 54 |
|
|
|
| 55 |
|
|
/*
|
| 56 |
|
|
BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART0.
|
| 57 |
|
|
*/
|
| 58 |
|
|
|
| 59 |
|
|
/* Standard includes. */
|
| 60 |
|
|
#include <stdlib.h>
|
| 61 |
|
|
|
| 62 |
|
|
/* Scheduler includes. */
|
| 63 |
|
|
#include "FreeRTOS.h"
|
| 64 |
|
|
#include "queue.h"
|
| 65 |
|
|
#include "task.h"
|
| 66 |
|
|
|
| 67 |
|
|
/* Demo application includes. */
|
| 68 |
|
|
#include "serial.h"
|
| 69 |
|
|
|
| 70 |
|
|
/*-----------------------------------------------------------*/
|
| 71 |
|
|
|
| 72 |
|
|
/* Constants to setup and access the UART. */
|
| 73 |
|
|
#define serDLAB ( ( unsigned char ) 0x80 )
|
| 74 |
|
|
#define serENABLE_INTERRUPTS ( ( unsigned char ) 0x03 )
|
| 75 |
|
|
#define serNO_PARITY ( ( unsigned char ) 0x00 )
|
| 76 |
|
|
#define ser1_STOP_BIT ( ( unsigned char ) 0x00 )
|
| 77 |
|
|
#define ser8_BIT_CHARS ( ( unsigned char ) 0x03 )
|
| 78 |
|
|
#define serFIFO_ON ( ( unsigned char ) 0x01 )
|
| 79 |
|
|
#define serCLEAR_FIFO ( ( unsigned char ) 0x06 )
|
| 80 |
|
|
#define serWANTED_CLOCK_SCALING ( ( unsigned long ) 16 )
|
| 81 |
|
|
|
| 82 |
|
|
/* Constants to setup and access the VIC. */
|
| 83 |
|
|
#define serU0VIC_CHANNEL ( ( unsigned long ) 0x0006 )
|
| 84 |
|
|
#define serU0VIC_CHANNEL_BIT ( ( unsigned long ) 0x0040 )
|
| 85 |
|
|
#define serU0VIC_ENABLE ( ( unsigned long ) 0x0020 )
|
| 86 |
|
|
#define serCLEAR_VIC_INTERRUPT ( ( unsigned long ) 0 )
|
| 87 |
|
|
|
| 88 |
|
|
/* Constants to determine the ISR source. */
|
| 89 |
|
|
#define serSOURCE_THRE ( ( unsigned char ) 0x02 )
|
| 90 |
|
|
#define serSOURCE_RX_TIMEOUT ( ( unsigned char ) 0x0c )
|
| 91 |
|
|
#define serSOURCE_ERROR ( ( unsigned char ) 0x06 )
|
| 92 |
|
|
#define serSOURCE_RX ( ( unsigned char ) 0x04 )
|
| 93 |
|
|
#define serINTERRUPT_SOURCE_MASK ( ( unsigned char ) 0x0f )
|
| 94 |
|
|
|
| 95 |
|
|
/* Misc. */
|
| 96 |
|
|
#define serINVALID_QUEUE ( ( xQueueHandle ) 0 )
|
| 97 |
|
|
#define serHANDLE ( ( xComPortHandle ) 1 )
|
| 98 |
|
|
#define serNO_BLOCK ( ( portTickType ) 0 )
|
| 99 |
|
|
|
| 100 |
|
|
/*-----------------------------------------------------------*/
|
| 101 |
|
|
|
| 102 |
|
|
/* Queues used to hold received characters, and characters waiting to be
|
| 103 |
|
|
transmitted. */
|
| 104 |
|
|
static xQueueHandle xRxedChars;
|
| 105 |
|
|
static xQueueHandle xCharsForTx;
|
| 106 |
|
|
static volatile long lTHREEmpty = pdFALSE;
|
| 107 |
|
|
|
| 108 |
|
|
/*-----------------------------------------------------------*/
|
| 109 |
|
|
|
| 110 |
|
|
/* The ISR. Note that this is called by a wrapper written in the file
|
| 111 |
|
|
SerialISR.s79. See the WEB documentation for this port for further
|
| 112 |
|
|
information. */
|
| 113 |
|
|
__arm void vSerialISR( void );
|
| 114 |
|
|
|
| 115 |
|
|
/*-----------------------------------------------------------*/
|
| 116 |
|
|
|
| 117 |
|
|
xComPortHandle xSerialPortInitMinimal( unsigned long ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )
|
| 118 |
|
|
{
|
| 119 |
|
|
unsigned long ulDivisor, ulWantedClock;
|
| 120 |
|
|
xComPortHandle xReturn = serHANDLE;
|
| 121 |
|
|
extern void ( vSerialISREntry) ( void );
|
| 122 |
|
|
|
| 123 |
|
|
/* Create the queues used to hold Rx and Tx characters. */
|
| 124 |
|
|
xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed char ) );
|
| 125 |
|
|
xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed char ) );
|
| 126 |
|
|
|
| 127 |
|
|
/* Initialise the THRE empty flag. */
|
| 128 |
|
|
lTHREEmpty = pdTRUE;
|
| 129 |
|
|
|
| 130 |
|
|
if(
|
| 131 |
|
|
( xRxedChars != serINVALID_QUEUE ) &&
|
| 132 |
|
|
( xCharsForTx != serINVALID_QUEUE ) &&
|
| 133 |
|
|
( ulWantedBaud != ( unsigned long ) 0 )
|
| 134 |
|
|
)
|
| 135 |
|
|
{
|
| 136 |
|
|
portENTER_CRITICAL();
|
| 137 |
|
|
{
|
| 138 |
|
|
/* Setup the baud rate: Calculate the divisor value. */
|
| 139 |
|
|
ulWantedClock = ulWantedBaud * serWANTED_CLOCK_SCALING;
|
| 140 |
|
|
ulDivisor = configCPU_CLOCK_HZ / ulWantedClock;
|
| 141 |
|
|
|
| 142 |
|
|
/* Set the DLAB bit so we can access the divisor. */
|
| 143 |
|
|
U0LCR |= serDLAB;
|
| 144 |
|
|
|
| 145 |
|
|
/* Setup the divisor. */
|
| 146 |
|
|
U0DLL = ( unsigned char ) ( ulDivisor & ( unsigned long ) 0xff );
|
| 147 |
|
|
ulDivisor >>= 8;
|
| 148 |
|
|
U0DLM = ( unsigned char ) ( ulDivisor & ( unsigned long ) 0xff );
|
| 149 |
|
|
|
| 150 |
|
|
/* Turn on the FIFO's and clear the buffers. */
|
| 151 |
|
|
U0FCR = ( serFIFO_ON | serCLEAR_FIFO );
|
| 152 |
|
|
|
| 153 |
|
|
/* Setup transmission format. */
|
| 154 |
|
|
U0LCR = serNO_PARITY | ser1_STOP_BIT | ser8_BIT_CHARS;
|
| 155 |
|
|
|
| 156 |
|
|
/* Setup the VIC for the UART. */
|
| 157 |
|
|
VICIntSelect &= ~( serU0VIC_CHANNEL_BIT );
|
| 158 |
|
|
VICIntEnable |= serU0VIC_CHANNEL_BIT;
|
| 159 |
|
|
VICVectAddr1 = ( unsigned long ) vSerialISREntry;
|
| 160 |
|
|
VICVectCntl1 = serU0VIC_CHANNEL | serU0VIC_ENABLE;
|
| 161 |
|
|
|
| 162 |
|
|
/* Enable UART0 interrupts. */
|
| 163 |
|
|
U0IER |= serENABLE_INTERRUPTS;
|
| 164 |
|
|
}
|
| 165 |
|
|
portEXIT_CRITICAL();
|
| 166 |
|
|
|
| 167 |
|
|
xReturn = ( xComPortHandle ) 1;
|
| 168 |
|
|
}
|
| 169 |
|
|
else
|
| 170 |
|
|
{
|
| 171 |
|
|
xReturn = ( xComPortHandle ) 0;
|
| 172 |
|
|
}
|
| 173 |
|
|
|
| 174 |
|
|
return xReturn;
|
| 175 |
|
|
}
|
| 176 |
|
|
/*-----------------------------------------------------------*/
|
| 177 |
|
|
|
| 178 |
|
|
signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed char *pcRxedChar, portTickType xBlockTime )
|
| 179 |
|
|
{
|
| 180 |
|
|
/* The port handle is not required as this driver only supports UART0. */
|
| 181 |
|
|
( void ) pxPort;
|
| 182 |
|
|
|
| 183 |
|
|
/* Get the next character from the buffer. Return false if no characters
|
| 184 |
|
|
are available, or arrive before xBlockTime expires. */
|
| 185 |
|
|
if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )
|
| 186 |
|
|
{
|
| 187 |
|
|
return pdTRUE;
|
| 188 |
|
|
}
|
| 189 |
|
|
else
|
| 190 |
|
|
{
|
| 191 |
|
|
return pdFALSE;
|
| 192 |
|
|
}
|
| 193 |
|
|
}
|
| 194 |
|
|
/*-----------------------------------------------------------*/
|
| 195 |
|
|
|
| 196 |
|
|
void vSerialPutString( xComPortHandle pxPort, const signed char * const pcString, unsigned short usStringLength )
|
| 197 |
|
|
{
|
| 198 |
|
|
signed char *pxNext;
|
| 199 |
|
|
|
| 200 |
|
|
/* NOTE: This implementation does not handle the queue being full as no
|
| 201 |
|
|
block time is used! */
|
| 202 |
|
|
|
| 203 |
|
|
/* The port handle is not required as this driver only supports UART0. */
|
| 204 |
|
|
( void ) pxPort;
|
| 205 |
|
|
( void ) usStringLength;
|
| 206 |
|
|
|
| 207 |
|
|
/* Send each character in the string, one at a time. */
|
| 208 |
|
|
pxNext = ( signed char * ) pcString;
|
| 209 |
|
|
while( *pxNext )
|
| 210 |
|
|
{
|
| 211 |
|
|
xSerialPutChar( pxPort, *pxNext, serNO_BLOCK );
|
| 212 |
|
|
pxNext++;
|
| 213 |
|
|
}
|
| 214 |
|
|
}
|
| 215 |
|
|
/*-----------------------------------------------------------*/
|
| 216 |
|
|
|
| 217 |
|
|
signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed char cOutChar, portTickType xBlockTime )
|
| 218 |
|
|
{
|
| 219 |
|
|
signed portBASE_TYPE xReturn;
|
| 220 |
|
|
|
| 221 |
|
|
/* The port handle is not required as this driver only supports UART0. */
|
| 222 |
|
|
( void ) pxPort;
|
| 223 |
|
|
|
| 224 |
|
|
portENTER_CRITICAL();
|
| 225 |
|
|
{
|
| 226 |
|
|
/* Is there space to write directly to the UART? */
|
| 227 |
|
|
if( lTHREEmpty == ( long ) pdTRUE )
|
| 228 |
|
|
{
|
| 229 |
|
|
/* We wrote the character directly to the UART, so was
|
| 230 |
|
|
successful. */
|
| 231 |
|
|
lTHREEmpty = pdFALSE;
|
| 232 |
|
|
U0THR = cOutChar;
|
| 233 |
|
|
xReturn = pdPASS;
|
| 234 |
|
|
}
|
| 235 |
|
|
else
|
| 236 |
|
|
{
|
| 237 |
|
|
/* We cannot write directly to the UART, so queue the character.
|
| 238 |
|
|
Block for a maximum of xBlockTime if there is no space in the
|
| 239 |
|
|
queue. It is ok to block within a critical section as each
|
| 240 |
|
|
task has it's own critical section management. */
|
| 241 |
|
|
xReturn = xQueueSend( xCharsForTx, &cOutChar, xBlockTime );
|
| 242 |
|
|
|
| 243 |
|
|
/* Depending on queue sizing and task prioritisation: While we
|
| 244 |
|
|
were blocked waiting to post interrupts were not disabled. It is
|
| 245 |
|
|
possible that the serial ISR has emptied the Tx queue, in which
|
| 246 |
|
|
case we need to start the Tx off again. */
|
| 247 |
|
|
if( lTHREEmpty == ( long ) pdTRUE )
|
| 248 |
|
|
{
|
| 249 |
|
|
xQueueReceive( xCharsForTx, &cOutChar, serNO_BLOCK );
|
| 250 |
|
|
lTHREEmpty = pdFALSE;
|
| 251 |
|
|
U0THR = cOutChar;
|
| 252 |
|
|
}
|
| 253 |
|
|
}
|
| 254 |
|
|
}
|
| 255 |
|
|
portEXIT_CRITICAL();
|
| 256 |
|
|
|
| 257 |
|
|
return xReturn;
|
| 258 |
|
|
}
|
| 259 |
|
|
/*-----------------------------------------------------------*/
|
| 260 |
|
|
|
| 261 |
|
|
__arm void vSerialISR( void )
|
| 262 |
|
|
{
|
| 263 |
|
|
signed char cChar;
|
| 264 |
|
|
portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;
|
| 265 |
|
|
|
| 266 |
|
|
/* What caused the interrupt? */
|
| 267 |
|
|
switch( U0IIR & serINTERRUPT_SOURCE_MASK )
|
| 268 |
|
|
{
|
| 269 |
|
|
case serSOURCE_ERROR : /* Not handling this, but clear the interrupt. */
|
| 270 |
|
|
cChar = U0LSR;
|
| 271 |
|
|
break;
|
| 272 |
|
|
|
| 273 |
|
|
case serSOURCE_THRE : /* The THRE is empty. If there is another
|
| 274 |
|
|
character in the Tx queue, send it now. */
|
| 275 |
|
|
if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xHigherPriorityTaskWoken ) == pdTRUE )
|
| 276 |
|
|
{
|
| 277 |
|
|
U0THR = cChar;
|
| 278 |
|
|
}
|
| 279 |
|
|
else
|
| 280 |
|
|
{
|
| 281 |
|
|
/* There are no further characters
|
| 282 |
|
|
queued to send so we can indicate
|
| 283 |
|
|
that the THRE is available. */
|
| 284 |
|
|
lTHREEmpty = pdTRUE;
|
| 285 |
|
|
}
|
| 286 |
|
|
break;
|
| 287 |
|
|
|
| 288 |
|
|
case serSOURCE_RX_TIMEOUT :
|
| 289 |
|
|
case serSOURCE_RX : /* A character was received. Place it in
|
| 290 |
|
|
the queue of received characters. */
|
| 291 |
|
|
cChar = U0RBR;
|
| 292 |
|
|
xQueueSendFromISR( xRxedChars, &cChar, &xHigherPriorityTaskWoken );
|
| 293 |
|
|
break;
|
| 294 |
|
|
|
| 295 |
|
|
default : /* There is nothing to do, leave the ISR. */
|
| 296 |
|
|
break;
|
| 297 |
|
|
}
|
| 298 |
|
|
|
| 299 |
|
|
/* Exit the ISR. If a task was woken by either a character being received
|
| 300 |
|
|
or transmitted then a context switch will occur. */
|
| 301 |
|
|
portEND_SWITCHING_ISR( xHigherPriorityTaskWoken );
|
| 302 |
|
|
|
| 303 |
|
|
/* Clear the ISR in the VIC. */
|
| 304 |
|
|
VICVectAddr = serCLEAR_VIC_INTERRUPT;
|
| 305 |
|
|
}
|
| 306 |
|
|
/*-----------------------------------------------------------*/
|
