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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [ARM7_LPC2129_Keil_RVDS/] [Startup.s] - Blame information for rev 587

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1 577 jeremybenn
;/*****************************************************************************/
2
;/* STARTUP.S: Startup file for Philips LPC2000                               */
3
;/*****************************************************************************/
4
;/* <<< Use Configuration Wizard in Context Menu >>>                          */ 
5
;/*****************************************************************************/
6
;/* This file is part of the uVision/ARM development tools.                   */
7
;/* Copyright (c) 2005-2007 Keil Software. All rights reserved.               */
8
;/* This software may only be used under the terms of a valid, current,       */
9
;/* end user licence from KEIL for a compatible version of KEIL software      */
10
;/* development tools. Nothing else gives you the right to use this software. */
11
;/*****************************************************************************/
12
 
13
 
14
;/*
15
; *  The STARTUP.S code is executed after CPU Reset. This file may be 
16
; *  translated with the following SET symbols. In uVision these SET 
17
; *  symbols are entered under Options - ASM - Define.
18
; *
19
; *  REMAP: when set the startup code initializes the register MEMMAP 
20
; *  which overwrites the settings of the CPU configuration pins. The 
21
; *  startup and interrupt vectors are remapped from:
22
; *     0x00000000  default setting (not remapped)
23
; *     0x80000000  when EXTMEM_MODE is used
24
; *     0x40000000  when RAM_MODE is used
25
; *
26
; *  EXTMEM_MODE: when set the device is configured for code execution
27
; *  from external memory starting at address 0x80000000.
28
; *
29
; *  RAM_MODE: when set the device is configured for code execution
30
; *  from on-chip RAM starting at address 0x40000000.
31
; *
32
; *  EXTERNAL_MODE: when set the PIN2SEL values are written that enable
33
; *  the external BUS at startup.
34
; */
35
 
36
 
37
; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs
38
 
39
Mode_USR        EQU     0x10
40
Mode_FIQ        EQU     0x11
41
Mode_IRQ        EQU     0x12
42
Mode_SVC        EQU     0x13
43
Mode_ABT        EQU     0x17
44
Mode_UND        EQU     0x1B
45
Mode_SYS        EQU     0x1F
46
 
47
I_Bit           EQU     0x80            ; when I bit is set, IRQ is disabled
48
F_Bit           EQU     0x40            ; when F bit is set, FIQ is disabled
49
 
50
 
51
;// <h> Stack Configuration (Stack Sizes in Bytes)
52
;//   <o0> Undefined Mode      <0x0-0xFFFFFFFF:8>
53
;//   <o1> Supervisor Mode     <0x0-0xFFFFFFFF:8>
54
;//   <o2> Abort Mode          <0x0-0xFFFFFFFF:8>
55
;//   <o3> Fast Interrupt Mode <0x0-0xFFFFFFFF:8>
56
;//   <o4> Interrupt Mode      <0x0-0xFFFFFFFF:8>
57
;//   <o5> User/System Mode    <0x0-0xFFFFFFFF:8>
58
;// </h>
59
 
60
UND_Stack_Size  EQU     0x00000008
61
SVC_Stack_Size  EQU     0x00000300
62
ABT_Stack_Size  EQU     0x00000008
63
FIQ_Stack_Size  EQU     0x00000008
64
IRQ_Stack_Size  EQU     0x00000300
65
USR_Stack_Size  EQU             0x00000008
66
 
67
Stack_Size      EQU     (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \
68
                         FIQ_Stack_Size + IRQ_Stack_Size + USR_Stack_Size )
69
 
70
                AREA    STACK, NOINIT, READWRITE, ALIGN=3
71
Stack_Mem       SPACE   Stack_Size
72
 
73
;__initial_sp    SPACE   ISR_Stack_Size
74
 
75
Stack_Top               EQU  Stack_Mem + Stack_Size
76
 
77
 
78
;// <h> Heap Configuration
79
;//   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF>
80
;// </h>
81
 
82
Heap_Size       EQU     0x00000000
83
 
84
                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
85
__heap_base
86
Heap_Mem        SPACE   Heap_Size
87
__heap_limit
88
 
89
 
90
; VPBDIV definitions
91
VPBDIV          EQU     0xE01FC100      ; VPBDIV Address
92
 
93
;// <e> VPBDIV Setup
94
;// <i> Peripheral Bus Clock Rate
95
;//   <o1.0..1>   VPBDIV: VPB Clock
96
;//               <0=> VPB Clock = CPU Clock / 4
97
;//               <1=> VPB Clock = CPU Clock
98
;//               <2=> VPB Clock = CPU Clock / 2
99
;//   <o1.4..5>   XCLKDIV: XCLK Pin
100
;//               <0=> XCLK Pin = CPU Clock / 4
101
;//               <1=> XCLK Pin = CPU Clock
102
;//               <2=> XCLK Pin = CPU Clock / 2
103
;// </e>
104
VPBDIV_SETUP    EQU     0
105
VPBDIV_Val      EQU     0x00000000
106
 
107
 
108
; Phase Locked Loop (PLL) definitions
109
PLL_BASE        EQU     0xE01FC080      ; PLL Base Address
110
PLLCON_OFS      EQU     0x00            ; PLL Control Offset
111
PLLCFG_OFS      EQU     0x04            ; PLL Configuration Offset
112
PLLSTAT_OFS     EQU     0x08            ; PLL Status Offset
113
PLLFEED_OFS     EQU     0x0C            ; PLL Feed Offset
114
PLLCON_PLLE     EQU     (1<<0)          ; PLL Enable
115
PLLCON_PLLC     EQU     (1<<1)          ; PLL Connect
116
PLLCFG_MSEL     EQU     (0x1F<<0)       ; PLL Multiplier
117
PLLCFG_PSEL     EQU     (0x03<<5)       ; PLL Divider
118
PLLSTAT_PLOCK   EQU     (1<<10)         ; PLL Lock Status
119
 
120
;// <e> PLL Setup
121
;//   <o1.0..4>   MSEL: PLL Multiplier Selection
122
;//               <1-32><#-1>
123
;//               <i> M Value
124
;//   <o1.5..6>   PSEL: PLL Divider Selection
125
;//               <0=> 1   <1=> 2   <2=> 4   <3=> 8
126
;//               <i> P Value
127
;// </e>
128
PLL_SETUP       EQU     1
129
PLLCFG_Val      EQU     0x00000024
130
 
131
 
132
; Memory Accelerator Module (MAM) definitions
133
MAM_BASE        EQU     0xE01FC000      ; MAM Base Address
134
MAMCR_OFS       EQU     0x00            ; MAM Control Offset
135
MAMTIM_OFS      EQU     0x04            ; MAM Timing Offset
136
 
137
;// <e> MAM Setup
138
;//   <o1.0..1>   MAM Control
139
;//               <0=> Disabled
140
;//               <1=> Partially Enabled
141
;//               <2=> Fully Enabled
142
;//               <i> Mode
143
;//   <o2.0..2>   MAM Timing
144
;//               <0=> Reserved  <1=> 1   <2=> 2   <3=> 3
145
;//               <4=> 4         <5=> 5   <6=> 6   <7=> 7
146
;//               <i> Fetch Cycles
147
;// </e>
148
MAM_SETUP       EQU     1
149
MAMCR_Val       EQU     0x00000002
150
MAMTIM_Val      EQU     0x00000004
151
 
152
 
153
; External Memory Controller (EMC) definitions
154
EMC_BASE        EQU     0xFFE00000      ; EMC Base Address
155
BCFG0_OFS       EQU     0x00            ; BCFG0 Offset
156
BCFG1_OFS       EQU     0x04            ; BCFG1 Offset
157
BCFG2_OFS       EQU     0x08            ; BCFG2 Offset
158
BCFG3_OFS       EQU     0x0C            ; BCFG3 Offset
159
 
160
;// <e> External Memory Controller (EMC)
161
EMC_SETUP       EQU     0
162
 
163
;//   <e> Bank Configuration 0 (BCFG0)
164
;//     <o1.0..3>   IDCY: Idle Cycles <0-15>
165
;//     <o1.5..9>   WST1: Wait States 1 <0-31>
166
;//     <o1.11..15> WST2: Wait States 2 <0-31>
167
;//     <o1.10>     RBLE: Read Byte Lane Enable
168
;//     <o1.26>     WP: Write Protect
169
;//     <o1.27>     BM: Burst ROM
170
;//     <o1.28..29> MW: Memory Width  <0=>  8-bit  <1=> 16-bit
171
;//                                   <2=> 32-bit  <3=> Reserved
172
;//   </e>
173
BCFG0_SETUP EQU         0
174
BCFG0_Val   EQU         0x0000FBEF
175
 
176
;//   <e> Bank Configuration 1 (BCFG1)
177
;//     <o1.0..3>   IDCY: Idle Cycles <0-15>
178
;//     <o1.5..9>   WST1: Wait States 1 <0-31>
179
;//     <o1.11..15> WST2: Wait States 2 <0-31>
180
;//     <o1.10>     RBLE: Read Byte Lane Enable
181
;//     <o1.26>     WP: Write Protect
182
;//     <o1.27>     BM: Burst ROM
183
;//     <o1.28..29> MW: Memory Width  <0=>  8-bit  <1=> 16-bit
184
;//                                   <2=> 32-bit  <3=> Reserved
185
;//   </e>
186
BCFG1_SETUP EQU         0
187
BCFG1_Val   EQU         0x0000FBEF
188
 
189
;//   <e> Bank Configuration 2 (BCFG2)
190
;//     <o1.0..3>   IDCY: Idle Cycles <0-15>
191
;//     <o1.5..9>   WST1: Wait States 1 <0-31>
192
;//     <o1.11..15> WST2: Wait States 2 <0-31>
193
;//     <o1.10>     RBLE: Read Byte Lane Enable
194
;//     <o1.26>     WP: Write Protect
195
;//     <o1.27>     BM: Burst ROM
196
;//     <o1.28..29> MW: Memory Width  <0=>  8-bit  <1=> 16-bit
197
;//                                   <2=> 32-bit  <3=> Reserved
198
;//   </e>
199
BCFG2_SETUP EQU         0
200
BCFG2_Val   EQU         0x0000FBEF
201
 
202
;//   <e> Bank Configuration 3 (BCFG3)
203
;//     <o1.0..3>   IDCY: Idle Cycles <0-15>
204
;//     <o1.5..9>   WST1: Wait States 1 <0-31>
205
;//     <o1.11..15> WST2: Wait States 2 <0-31>
206
;//     <o1.10>     RBLE: Read Byte Lane Enable
207
;//     <o1.26>     WP: Write Protect
208
;//     <o1.27>     BM: Burst ROM
209
;//     <o1.28..29> MW: Memory Width  <0=>  8-bit  <1=> 16-bit
210
;//                                   <2=> 32-bit  <3=> Reserved
211
;//   </e>
212
BCFG3_SETUP EQU         0
213
BCFG3_Val   EQU         0x0000FBEF
214
 
215
;// </e> End of EMC
216
 
217
 
218
; External Memory Pins definitions
219
PINSEL2         EQU     0xE002C014      ; PINSEL2 Address
220
PINSEL2_Val     EQU     0x0E6149E4      ; CS0..3, OE, WE, BLS0..3, 
221
                                        ; D0..31, A2..23, JTAG Pins
222
 
223
 
224
                PRESERVE8
225
 
226
 
227
; Area Definition and Entry Point
228
;  Startup Code must be linked first at Address at which it expects to run.
229
 
230
                AREA    RESET, CODE, READONLY
231
                ARM
232
 
233
 
234
; Exception Vectors
235
;  Mapped to Address 0.
236
;  Absolute addressing mode must be used.
237
;  Dummy Handlers are implemented as infinite loops which can be modified.
238
                                IMPORT  vPortYieldProcessor
239
 
240
Vectors         LDR     PC, Reset_Addr
241
                LDR     PC, Undef_Addr
242
                LDR     PC, SWI_Addr
243
                LDR     PC, PAbt_Addr
244
                LDR     PC, DAbt_Addr
245
                NOP                            ; Reserved Vector 
246
;               LDR     PC, IRQ_Addr
247
                LDR     PC, [PC, #-0x0FF0]     ; Vector from VicVectAddr
248
                LDR     PC, FIQ_Addr
249
 
250
Reset_Addr      DCD     Reset_Handler
251
Undef_Addr      DCD     Undef_Handler
252
SWI_Addr        DCD     vPortYieldProcessor
253
PAbt_Addr       DCD     PAbt_Handler
254
DAbt_Addr       DCD     DAbt_Handler
255
                DCD     0                      ; Reserved Address 
256
IRQ_Addr        DCD     IRQ_Handler
257
FIQ_Addr        DCD     FIQ_Handler
258
 
259
Undef_Handler   B       Undef_Handler
260
SWI_Handler     B       SWI_Handler
261
PAbt_Handler    B       PAbt_Handler
262
DAbt_Handler    B       DAbt_Handler
263
IRQ_Handler     B       IRQ_Handler
264
FIQ_Handler     B       FIQ_Handler
265
 
266
 
267
; Reset Handler
268
 
269
                EXPORT  Reset_Handler
270
Reset_Handler
271
 
272
 
273
; Setup External Memory Pins
274
                IF      :DEF:EXTERNAL_MODE
275
                LDR     R0, =PINSEL2
276
                LDR     R1, =PINSEL2_Val
277
                STR     R1, [R0]
278
                ENDIF
279
 
280
 
281
; Setup External Memory Controller
282
                IF      EMC_SETUP <> 0
283
                LDR     R0, =EMC_BASE
284
 
285
                IF      BCFG0_SETUP <> 0
286
                LDR     R1, =BCFG0_Val
287
                STR     R1, [R0, #BCFG0_OFS]
288
                ENDIF
289
 
290
                IF      BCFG1_SETUP <> 0
291
                LDR     R1, =BCFG1_Val
292
                STR     R1, [R0, #BCFG1_OFS]
293
                ENDIF
294
 
295
                IF      BCFG2_SETUP <> 0
296
                LDR     R1, =BCFG2_Val
297
                STR     R1, [R0, #BCFG2_OFS]
298
                ENDIF
299
 
300
                IF      BCFG3_SETUP <> 0
301
                LDR     R1, =BCFG3_Val
302
                STR     R1, [R0, #BCFG3_OFS]
303
                ENDIF
304
 
305
                ENDIF   ; EMC_SETUP
306
 
307
 
308
; Setup VPBDIV
309
                IF      VPBDIV_SETUP <> 0
310
                LDR     R0, =VPBDIV
311
                LDR     R1, =VPBDIV_Val
312
                STR     R1, [R0]
313
                ENDIF
314
 
315
 
316
; Setup PLL
317
                IF      PLL_SETUP <> 0
318
                LDR     R0, =PLL_BASE
319
                MOV     R1, #0xAA
320
                MOV     R2, #0x55
321
 
322
;  Configure and Enable PLL
323
                MOV     R3, #PLLCFG_Val
324
                STR     R3, [R0, #PLLCFG_OFS]
325
                MOV     R3, #PLLCON_PLLE
326
                STR     R3, [R0, #PLLCON_OFS]
327
                STR     R1, [R0, #PLLFEED_OFS]
328
                STR     R2, [R0, #PLLFEED_OFS]
329
 
330
;  Wait until PLL Locked
331
PLL_Loop        LDR     R3, [R0, #PLLSTAT_OFS]
332
                ANDS    R3, R3, #PLLSTAT_PLOCK
333
                BEQ     PLL_Loop
334
 
335
;  Switch to PLL Clock
336
                MOV     R3, #(PLLCON_PLLE:OR:PLLCON_PLLC)
337
                STR     R3, [R0, #PLLCON_OFS]
338
                STR     R1, [R0, #PLLFEED_OFS]
339
                STR     R2, [R0, #PLLFEED_OFS]
340
                ENDIF   ; PLL_SETUP
341
 
342
 
343
; Setup MAM
344
                IF      MAM_SETUP <> 0
345
                LDR     R0, =MAM_BASE
346
                MOV     R1, #MAMTIM_Val
347
                STR     R1, [R0, #MAMTIM_OFS]
348
                MOV     R1, #MAMCR_Val
349
                STR     R1, [R0, #MAMCR_OFS]
350
                ENDIF   ; MAM_SETUP
351
 
352
 
353
; Memory Mapping (when Interrupt Vectors are in RAM)
354
MEMMAP          EQU     0xE01FC040      ; Memory Mapping Control
355
                IF      :DEF:REMAP
356
                LDR     R0, =MEMMAP
357
                IF      :DEF:EXTMEM_MODE
358
                MOV     R1, #3
359
                ELIF    :DEF:RAM_MODE
360
                MOV     R1, #2
361
                ELSE
362
                MOV     R1, #1
363
                ENDIF
364
                STR     R1, [R0]
365
                ENDIF
366
 
367
 
368
; Initialise Interrupt System
369
;  ...
370
 
371
 
372
; Setup Stack for each mode
373
 
374
                LDR     R0, =Stack_Top
375
 
376
;  Enter Undefined Instruction Mode and set its Stack Pointer
377
                MSR     CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit
378
                MOV     SP, R0
379
                SUB     R0, R0, #UND_Stack_Size
380
 
381
;  Enter Abort Mode and set its Stack Pointer
382
                MSR     CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit
383
                MOV     SP, R0
384
                SUB     R0, R0, #ABT_Stack_Size
385
 
386
;  Enter FIQ Mode and set its Stack Pointer
387
                MSR     CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit
388
                MOV     SP, R0
389
                SUB     R0, R0, #FIQ_Stack_Size
390
 
391
;  Enter IRQ Mode and set its Stack Pointer
392
                MSR     CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit
393
                MOV     SP, R0
394
                SUB     R0, R0, #IRQ_Stack_Size
395
 
396
;  Enter Supervisor Mode and set its Stack Pointer
397
                MSR     CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit
398
                MOV     SP, R0
399
                SUB     R0, R0, #SVC_Stack_Size
400
 
401
; Enter the C code
402
 
403
                IMPORT  __main
404
                LDR     R0, =__main
405
                BX      R0
406
 
407
 
408
                IF      :DEF:__MICROLIB
409
 
410
                EXPORT  __heap_base
411
                EXPORT  __heap_limit
412
 
413
                ELSE
414
; User Initial Stack & Heap
415
                AREA    |.text|, CODE, READONLY
416
 
417
                IMPORT  __use_two_region_memory
418
                EXPORT  __user_initial_stackheap
419
__user_initial_stackheap
420
 
421
                LDR     R0, =  Heap_Mem
422
                LDR     R1, = (Stack_Mem + IRQ_Stack_Size + USR_Stack_Size)
423
                LDR     R2, = (Heap_Mem + Heap_Size)
424
                LDR     R3, = Stack_Mem
425
                BX      LR
426
                ENDIF
427
 
428
 
429
                END

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