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577 |
jeremybenn |
;/*****************************************************************************/
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;/* STARTUP.S: Startup file for Philips LPC2000 */
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;/*****************************************************************************/
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;/* <<< Use Configuration Wizard in Context Menu >>> */
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;/*****************************************************************************/
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;/* This file is part of the uVision/ARM development tools. */
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;/* Copyright (c) 2005-2007 Keil Software. All rights reserved. */
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;/* This software may only be used under the terms of a valid, current, */
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;/* end user licence from KEIL for a compatible version of KEIL software */
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;/* development tools. Nothing else gives you the right to use this software. */
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;/*****************************************************************************/
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;/*
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; * The STARTUP.S code is executed after CPU Reset. This file may be
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; * translated with the following SET symbols. In uVision these SET
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; * symbols are entered under Options - ASM - Define.
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; *
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; * REMAP: when set the startup code initializes the register MEMMAP
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; * which overwrites the settings of the CPU configuration pins. The
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; * startup and interrupt vectors are remapped from:
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; * 0x00000000 default setting (not remapped)
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; * 0x80000000 when EXTMEM_MODE is used
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; * 0x40000000 when RAM_MODE is used
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; *
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; * EXTMEM_MODE: when set the device is configured for code execution
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; * from external memory starting at address 0x80000000.
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; *
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; * RAM_MODE: when set the device is configured for code execution
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; * from on-chip RAM starting at address 0x40000000.
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; *
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; * EXTERNAL_MODE: when set the PIN2SEL values are written that enable
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; * the external BUS at startup.
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; */
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| 36 |
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; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs
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| 39 |
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Mode_USR EQU 0x10
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| 40 |
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Mode_FIQ EQU 0x11
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Mode_IRQ EQU 0x12
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| 42 |
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Mode_SVC EQU 0x13
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| 43 |
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Mode_ABT EQU 0x17
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Mode_UND EQU 0x1B
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Mode_SYS EQU 0x1F
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| 46 |
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| 47 |
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I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled
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F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled
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| 49 |
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| 50 |
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| 51 |
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;// <h> Stack Configuration (Stack Sizes in Bytes)
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;// <o0> Undefined Mode <0x0-0xFFFFFFFF:8>
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;// <o1> Supervisor Mode <0x0-0xFFFFFFFF:8>
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;// <o2> Abort Mode <0x0-0xFFFFFFFF:8>
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;// <o3> Fast Interrupt Mode <0x0-0xFFFFFFFF:8>
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;// <o4> Interrupt Mode <0x0-0xFFFFFFFF:8>
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;// <o5> User/System Mode <0x0-0xFFFFFFFF:8>
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;// </h>
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| 60 |
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UND_Stack_Size EQU 0x00000008
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SVC_Stack_Size EQU 0x00000300
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ABT_Stack_Size EQU 0x00000008
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FIQ_Stack_Size EQU 0x00000008
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IRQ_Stack_Size EQU 0x00000300
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USR_Stack_Size EQU 0x00000008
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| 67 |
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Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \
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FIQ_Stack_Size + IRQ_Stack_Size + USR_Stack_Size )
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AREA STACK, NOINIT, READWRITE, ALIGN=3
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Stack_Mem SPACE Stack_Size
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;__initial_sp SPACE ISR_Stack_Size
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Stack_Top EQU Stack_Mem + Stack_Size
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| 77 |
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| 78 |
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;// <h> Heap Configuration
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;// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF>
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;// </h>
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Heap_Size EQU 0x00000000
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AREA HEAP, NOINIT, READWRITE, ALIGN=3
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__heap_base
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Heap_Mem SPACE Heap_Size
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__heap_limit
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| 88 |
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| 89 |
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| 90 |
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; VPBDIV definitions
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VPBDIV EQU 0xE01FC100 ; VPBDIV Address
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;// <e> VPBDIV Setup
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;// <i> Peripheral Bus Clock Rate
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;// <o1.0..1> VPBDIV: VPB Clock
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;// <0=> VPB Clock = CPU Clock / 4
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;// <1=> VPB Clock = CPU Clock
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;// <2=> VPB Clock = CPU Clock / 2
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;// <o1.4..5> XCLKDIV: XCLK Pin
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;// <0=> XCLK Pin = CPU Clock / 4
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;// <1=> XCLK Pin = CPU Clock
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;// <2=> XCLK Pin = CPU Clock / 2
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;// </e>
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VPBDIV_SETUP EQU 0
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VPBDIV_Val EQU 0x00000000
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| 107 |
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| 108 |
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; Phase Locked Loop (PLL) definitions
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PLL_BASE EQU 0xE01FC080 ; PLL Base Address
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PLLCON_OFS EQU 0x00 ; PLL Control Offset
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PLLCFG_OFS EQU 0x04 ; PLL Configuration Offset
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PLLSTAT_OFS EQU 0x08 ; PLL Status Offset
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PLLFEED_OFS EQU 0x0C ; PLL Feed Offset
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PLLCON_PLLE EQU (1<<0) ; PLL Enable
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PLLCON_PLLC EQU (1<<1) ; PLL Connect
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PLLCFG_MSEL EQU (0x1F<<0) ; PLL Multiplier
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PLLCFG_PSEL EQU (0x03<<5) ; PLL Divider
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PLLSTAT_PLOCK EQU (1<<10) ; PLL Lock Status
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| 120 |
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;// <e> PLL Setup
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;// <o1.0..4> MSEL: PLL Multiplier Selection
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;// <1-32><#-1>
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;// <i> M Value
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;// <o1.5..6> PSEL: PLL Divider Selection
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;// <0=> 1 <1=> 2 <2=> 4 <3=> 8
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;// <i> P Value
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;// </e>
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PLL_SETUP EQU 1
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PLLCFG_Val EQU 0x00000024
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| 131 |
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| 132 |
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; Memory Accelerator Module (MAM) definitions
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MAM_BASE EQU 0xE01FC000 ; MAM Base Address
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MAMCR_OFS EQU 0x00 ; MAM Control Offset
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MAMTIM_OFS EQU 0x04 ; MAM Timing Offset
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| 136 |
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| 137 |
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;// <e> MAM Setup
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| 138 |
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;// <o1.0..1> MAM Control
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;// <0=> Disabled
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;// <1=> Partially Enabled
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| 141 |
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;// <2=> Fully Enabled
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| 142 |
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;// <i> Mode
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;// <o2.0..2> MAM Timing
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;// <0=> Reserved <1=> 1 <2=> 2 <3=> 3
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;// <4=> 4 <5=> 5 <6=> 6 <7=> 7
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;// <i> Fetch Cycles
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;// </e>
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MAM_SETUP EQU 1
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MAMCR_Val EQU 0x00000002
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MAMTIM_Val EQU 0x00000004
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| 152 |
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| 153 |
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; External Memory Controller (EMC) definitions
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EMC_BASE EQU 0xFFE00000 ; EMC Base Address
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BCFG0_OFS EQU 0x00 ; BCFG0 Offset
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BCFG1_OFS EQU 0x04 ; BCFG1 Offset
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BCFG2_OFS EQU 0x08 ; BCFG2 Offset
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BCFG3_OFS EQU 0x0C ; BCFG3 Offset
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| 159 |
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| 160 |
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;// <e> External Memory Controller (EMC)
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EMC_SETUP EQU 0
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;// <e> Bank Configuration 0 (BCFG0)
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;// <o1.0..3> IDCY: Idle Cycles <0-15>
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;// <o1.5..9> WST1: Wait States 1 <0-31>
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| 166 |
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;// <o1.11..15> WST2: Wait States 2 <0-31>
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| 167 |
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;// <o1.10> RBLE: Read Byte Lane Enable
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| 168 |
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;// <o1.26> WP: Write Protect
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| 169 |
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;// <o1.27> BM: Burst ROM
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| 170 |
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;// <o1.28..29> MW: Memory Width <0=> 8-bit <1=> 16-bit
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;// <2=> 32-bit <3=> Reserved
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;// </e>
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BCFG0_SETUP EQU 0
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BCFG0_Val EQU 0x0000FBEF
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;// <e> Bank Configuration 1 (BCFG1)
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;// <o1.0..3> IDCY: Idle Cycles <0-15>
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| 178 |
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;// <o1.5..9> WST1: Wait States 1 <0-31>
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| 179 |
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;// <o1.11..15> WST2: Wait States 2 <0-31>
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| 180 |
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;// <o1.10> RBLE: Read Byte Lane Enable
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| 181 |
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;// <o1.26> WP: Write Protect
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| 182 |
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;// <o1.27> BM: Burst ROM
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;// <o1.28..29> MW: Memory Width <0=> 8-bit <1=> 16-bit
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;// <2=> 32-bit <3=> Reserved
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;// </e>
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BCFG1_SETUP EQU 0
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BCFG1_Val EQU 0x0000FBEF
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| 189 |
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;// <e> Bank Configuration 2 (BCFG2)
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| 190 |
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;// <o1.0..3> IDCY: Idle Cycles <0-15>
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| 191 |
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;// <o1.5..9> WST1: Wait States 1 <0-31>
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| 192 |
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;// <o1.11..15> WST2: Wait States 2 <0-31>
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| 193 |
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;// <o1.10> RBLE: Read Byte Lane Enable
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| 194 |
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;// <o1.26> WP: Write Protect
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| 195 |
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;// <o1.27> BM: Burst ROM
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| 196 |
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;// <o1.28..29> MW: Memory Width <0=> 8-bit <1=> 16-bit
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;// <2=> 32-bit <3=> Reserved
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;// </e>
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BCFG2_SETUP EQU 0
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BCFG2_Val EQU 0x0000FBEF
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| 202 |
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;// <e> Bank Configuration 3 (BCFG3)
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| 203 |
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;// <o1.0..3> IDCY: Idle Cycles <0-15>
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| 204 |
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;// <o1.5..9> WST1: Wait States 1 <0-31>
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| 205 |
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;// <o1.11..15> WST2: Wait States 2 <0-31>
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| 206 |
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;// <o1.10> RBLE: Read Byte Lane Enable
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| 207 |
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;// <o1.26> WP: Write Protect
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| 208 |
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;// <o1.27> BM: Burst ROM
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| 209 |
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;// <o1.28..29> MW: Memory Width <0=> 8-bit <1=> 16-bit
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| 210 |
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;// <2=> 32-bit <3=> Reserved
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| 211 |
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;// </e>
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BCFG3_SETUP EQU 0
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BCFG3_Val EQU 0x0000FBEF
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| 214 |
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| 215 |
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;// </e> End of EMC
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| 216 |
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| 217 |
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| 218 |
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; External Memory Pins definitions
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| 219 |
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PINSEL2 EQU 0xE002C014 ; PINSEL2 Address
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| 220 |
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PINSEL2_Val EQU 0x0E6149E4 ; CS0..3, OE, WE, BLS0..3,
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| 221 |
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; D0..31, A2..23, JTAG Pins
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| 222 |
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| 223 |
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| 224 |
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PRESERVE8
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| 225 |
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| 226 |
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| 227 |
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; Area Definition and Entry Point
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| 228 |
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; Startup Code must be linked first at Address at which it expects to run.
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| 229 |
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| 230 |
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AREA RESET, CODE, READONLY
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| 231 |
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ARM
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| 232 |
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| 233 |
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| 234 |
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; Exception Vectors
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| 235 |
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; Mapped to Address 0.
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| 236 |
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; Absolute addressing mode must be used.
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| 237 |
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; Dummy Handlers are implemented as infinite loops which can be modified.
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| 238 |
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IMPORT vPortYieldProcessor
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| 239 |
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| 240 |
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Vectors LDR PC, Reset_Addr
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| 241 |
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LDR PC, Undef_Addr
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| 242 |
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LDR PC, SWI_Addr
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| 243 |
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LDR PC, PAbt_Addr
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| 244 |
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LDR PC, DAbt_Addr
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| 245 |
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NOP ; Reserved Vector
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| 246 |
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; LDR PC, IRQ_Addr
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| 247 |
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LDR PC, [PC, #-0x0FF0] ; Vector from VicVectAddr
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| 248 |
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LDR PC, FIQ_Addr
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| 249 |
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| 250 |
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Reset_Addr DCD Reset_Handler
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| 251 |
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Undef_Addr DCD Undef_Handler
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| 252 |
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SWI_Addr DCD vPortYieldProcessor
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| 253 |
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PAbt_Addr DCD PAbt_Handler
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| 254 |
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DAbt_Addr DCD DAbt_Handler
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| 255 |
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DCD 0 ; Reserved Address
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| 256 |
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IRQ_Addr DCD IRQ_Handler
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| 257 |
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FIQ_Addr DCD FIQ_Handler
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| 258 |
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| 259 |
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Undef_Handler B Undef_Handler
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| 260 |
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SWI_Handler B SWI_Handler
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| 261 |
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PAbt_Handler B PAbt_Handler
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| 262 |
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DAbt_Handler B DAbt_Handler
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| 263 |
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IRQ_Handler B IRQ_Handler
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| 264 |
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FIQ_Handler B FIQ_Handler
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| 265 |
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| 266 |
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| 267 |
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; Reset Handler
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| 268 |
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| 269 |
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EXPORT Reset_Handler
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| 270 |
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Reset_Handler
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| 271 |
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| 272 |
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| 273 |
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; Setup External Memory Pins
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| 274 |
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IF :DEF:EXTERNAL_MODE
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| 275 |
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LDR R0, =PINSEL2
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| 276 |
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LDR R1, =PINSEL2_Val
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| 277 |
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STR R1, [R0]
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| 278 |
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ENDIF
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| 279 |
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| 280 |
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| 281 |
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; Setup External Memory Controller
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| 282 |
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IF EMC_SETUP <> 0
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| 283 |
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LDR R0, =EMC_BASE
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| 284 |
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|
| 285 |
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IF BCFG0_SETUP <> 0
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| 286 |
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LDR R1, =BCFG0_Val
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| 287 |
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STR R1, [R0, #BCFG0_OFS]
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| 288 |
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ENDIF
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| 289 |
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| 290 |
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IF BCFG1_SETUP <> 0
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| 291 |
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LDR R1, =BCFG1_Val
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| 292 |
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STR R1, [R0, #BCFG1_OFS]
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| 293 |
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ENDIF
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| 294 |
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| 295 |
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IF BCFG2_SETUP <> 0
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| 296 |
|
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LDR R1, =BCFG2_Val
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| 297 |
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STR R1, [R0, #BCFG2_OFS]
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| 298 |
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ENDIF
|
| 299 |
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| 300 |
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IF BCFG3_SETUP <> 0
|
| 301 |
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LDR R1, =BCFG3_Val
|
| 302 |
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STR R1, [R0, #BCFG3_OFS]
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| 303 |
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ENDIF
|
| 304 |
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| 305 |
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ENDIF ; EMC_SETUP
|
| 306 |
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|
| 307 |
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| 308 |
|
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; Setup VPBDIV
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| 309 |
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IF VPBDIV_SETUP <> 0
|
| 310 |
|
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LDR R0, =VPBDIV
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| 311 |
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LDR R1, =VPBDIV_Val
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| 312 |
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STR R1, [R0]
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| 313 |
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ENDIF
|
| 314 |
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|
| 315 |
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|
| 316 |
|
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; Setup PLL
|
| 317 |
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IF PLL_SETUP <> 0
|
| 318 |
|
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LDR R0, =PLL_BASE
|
| 319 |
|
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MOV R1, #0xAA
|
| 320 |
|
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MOV R2, #0x55
|
| 321 |
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|
| 322 |
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; Configure and Enable PLL
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| 323 |
|
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MOV R3, #PLLCFG_Val
|
| 324 |
|
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STR R3, [R0, #PLLCFG_OFS]
|
| 325 |
|
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MOV R3, #PLLCON_PLLE
|
| 326 |
|
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STR R3, [R0, #PLLCON_OFS]
|
| 327 |
|
|
STR R1, [R0, #PLLFEED_OFS]
|
| 328 |
|
|
STR R2, [R0, #PLLFEED_OFS]
|
| 329 |
|
|
|
| 330 |
|
|
; Wait until PLL Locked
|
| 331 |
|
|
PLL_Loop LDR R3, [R0, #PLLSTAT_OFS]
|
| 332 |
|
|
ANDS R3, R3, #PLLSTAT_PLOCK
|
| 333 |
|
|
BEQ PLL_Loop
|
| 334 |
|
|
|
| 335 |
|
|
; Switch to PLL Clock
|
| 336 |
|
|
MOV R3, #(PLLCON_PLLE:OR:PLLCON_PLLC)
|
| 337 |
|
|
STR R3, [R0, #PLLCON_OFS]
|
| 338 |
|
|
STR R1, [R0, #PLLFEED_OFS]
|
| 339 |
|
|
STR R2, [R0, #PLLFEED_OFS]
|
| 340 |
|
|
ENDIF ; PLL_SETUP
|
| 341 |
|
|
|
| 342 |
|
|
|
| 343 |
|
|
; Setup MAM
|
| 344 |
|
|
IF MAM_SETUP <> 0
|
| 345 |
|
|
LDR R0, =MAM_BASE
|
| 346 |
|
|
MOV R1, #MAMTIM_Val
|
| 347 |
|
|
STR R1, [R0, #MAMTIM_OFS]
|
| 348 |
|
|
MOV R1, #MAMCR_Val
|
| 349 |
|
|
STR R1, [R0, #MAMCR_OFS]
|
| 350 |
|
|
ENDIF ; MAM_SETUP
|
| 351 |
|
|
|
| 352 |
|
|
|
| 353 |
|
|
; Memory Mapping (when Interrupt Vectors are in RAM)
|
| 354 |
|
|
MEMMAP EQU 0xE01FC040 ; Memory Mapping Control
|
| 355 |
|
|
IF :DEF:REMAP
|
| 356 |
|
|
LDR R0, =MEMMAP
|
| 357 |
|
|
IF :DEF:EXTMEM_MODE
|
| 358 |
|
|
MOV R1, #3
|
| 359 |
|
|
ELIF :DEF:RAM_MODE
|
| 360 |
|
|
MOV R1, #2
|
| 361 |
|
|
ELSE
|
| 362 |
|
|
MOV R1, #1
|
| 363 |
|
|
ENDIF
|
| 364 |
|
|
STR R1, [R0]
|
| 365 |
|
|
ENDIF
|
| 366 |
|
|
|
| 367 |
|
|
|
| 368 |
|
|
; Initialise Interrupt System
|
| 369 |
|
|
; ...
|
| 370 |
|
|
|
| 371 |
|
|
|
| 372 |
|
|
; Setup Stack for each mode
|
| 373 |
|
|
|
| 374 |
|
|
LDR R0, =Stack_Top
|
| 375 |
|
|
|
| 376 |
|
|
; Enter Undefined Instruction Mode and set its Stack Pointer
|
| 377 |
|
|
MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit
|
| 378 |
|
|
MOV SP, R0
|
| 379 |
|
|
SUB R0, R0, #UND_Stack_Size
|
| 380 |
|
|
|
| 381 |
|
|
; Enter Abort Mode and set its Stack Pointer
|
| 382 |
|
|
MSR CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit
|
| 383 |
|
|
MOV SP, R0
|
| 384 |
|
|
SUB R0, R0, #ABT_Stack_Size
|
| 385 |
|
|
|
| 386 |
|
|
; Enter FIQ Mode and set its Stack Pointer
|
| 387 |
|
|
MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit
|
| 388 |
|
|
MOV SP, R0
|
| 389 |
|
|
SUB R0, R0, #FIQ_Stack_Size
|
| 390 |
|
|
|
| 391 |
|
|
; Enter IRQ Mode and set its Stack Pointer
|
| 392 |
|
|
MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit
|
| 393 |
|
|
MOV SP, R0
|
| 394 |
|
|
SUB R0, R0, #IRQ_Stack_Size
|
| 395 |
|
|
|
| 396 |
|
|
; Enter Supervisor Mode and set its Stack Pointer
|
| 397 |
|
|
MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit
|
| 398 |
|
|
MOV SP, R0
|
| 399 |
|
|
SUB R0, R0, #SVC_Stack_Size
|
| 400 |
|
|
|
| 401 |
|
|
; Enter the C code
|
| 402 |
|
|
|
| 403 |
|
|
IMPORT __main
|
| 404 |
|
|
LDR R0, =__main
|
| 405 |
|
|
BX R0
|
| 406 |
|
|
|
| 407 |
|
|
|
| 408 |
|
|
IF :DEF:__MICROLIB
|
| 409 |
|
|
|
| 410 |
|
|
EXPORT __heap_base
|
| 411 |
|
|
EXPORT __heap_limit
|
| 412 |
|
|
|
| 413 |
|
|
ELSE
|
| 414 |
|
|
; User Initial Stack & Heap
|
| 415 |
|
|
AREA |.text|, CODE, READONLY
|
| 416 |
|
|
|
| 417 |
|
|
IMPORT __use_two_region_memory
|
| 418 |
|
|
EXPORT __user_initial_stackheap
|
| 419 |
|
|
__user_initial_stackheap
|
| 420 |
|
|
|
| 421 |
|
|
LDR R0, = Heap_Mem
|
| 422 |
|
|
LDR R1, = (Stack_Mem + IRQ_Stack_Size + USR_Stack_Size)
|
| 423 |
|
|
LDR R2, = (Heap_Mem + Heap_Size)
|
| 424 |
|
|
LDR R3, = Stack_Mem
|
| 425 |
|
|
BX LR
|
| 426 |
|
|
ENDIF
|
| 427 |
|
|
|
| 428 |
|
|
|
| 429 |
|
|
END
|
