OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [ARM7_LPC2138_Rowley/] [LPC21xx.h] - Blame information for rev 773

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 577 jeremybenn
// Copyright (c) 2009 Rowley Associates Limited.
2
//
3
// This file may be distributed under the terms of the License Agreement
4
// provided with this software.
5
//
6
// THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE
7
// WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
8
 
9
#ifndef LPC21xx_h
10
#define LPC21xx_h
11
 
12
#define FIO_BASE 0x3FFFC000
13
 
14
#define FIO0DIR (*(volatile unsigned long *)0x3FFFC000)
15
#define FIO0DIR_OFFSET 0x0
16
 
17
#define FIO0DIR0 (*(volatile unsigned char *)0x3FFFC000)
18
#define FIO0DIR0_OFFSET 0x0
19
 
20
#define FIO0DIR1 (*(volatile unsigned char *)0x3FFFC001)
21
#define FIO0DIR1_OFFSET 0x1
22
 
23
#define FIO0DIR2 (*(volatile unsigned char *)0x3FFFC002)
24
#define FIO0DIR2_OFFSET 0x2
25
 
26
#define FIO0DIR3 (*(volatile unsigned char *)0x3FFFC003)
27
#define FIO0DIR3_OFFSET 0x3
28
 
29
#define FIO0DIRL (*(volatile unsigned short *)0x3FFFC000)
30
#define FIO0DIRL_OFFSET 0x0
31
 
32
#define FIO0DIRH (*(volatile unsigned short *)0x3FFFC002)
33
#define FIO0DIRH_OFFSET 0x2
34
 
35
#define FIO0MASK (*(volatile unsigned long *)0x3FFFC010)
36
#define FIO0MASK_OFFSET 0x10
37
 
38
#define FIO0MASK0 (*(volatile unsigned char *)0x3FFFC010)
39
#define FIO0MASK0_OFFSET 0x10
40
 
41
#define FIO0MASK1 (*(volatile unsigned char *)0x3FFFC011)
42
#define FIO0MASK1_OFFSET 0x11
43
 
44
#define FIO0MASK2 (*(volatile unsigned char *)0x3FFFC012)
45
#define FIO0MASK2_OFFSET 0x12
46
 
47
#define FIO0MASK3 (*(volatile unsigned char *)0x3FFFC013)
48
#define FIO0MASK3_OFFSET 0x13
49
 
50
#define FIO0MASKL (*(volatile unsigned short *)0x3FFFC010)
51
#define FIO0MASKL_OFFSET 0x10
52
 
53
#define FIO0MASKH (*(volatile unsigned short *)0x3FFFC012)
54
#define FIO0MASKH_OFFSET 0x12
55
 
56
#define FIO0PIN (*(volatile unsigned long *)0x3FFFC014)
57
#define FIO0PIN_OFFSET 0x14
58
 
59
#define FIO0PIN0 (*(volatile unsigned char *)0x3FFFC014)
60
#define FIO0PIN0_OFFSET 0x14
61
 
62
#define FIO0PIN1 (*(volatile unsigned char *)0x3FFFC015)
63
#define FIO0PIN1_OFFSET 0x15
64
 
65
#define FIO0PIN2 (*(volatile unsigned char *)0x3FFFC016)
66
#define FIO0PIN2_OFFSET 0x16
67
 
68
#define FIO0PIN3 (*(volatile unsigned char *)0x3FFFC017)
69
#define FIO0PIN3_OFFSET 0x17
70
 
71
#define FIO0PINL (*(volatile unsigned short *)0x3FFFC014)
72
#define FIO0PINL_OFFSET 0x14
73
 
74
#define FIO0PINH (*(volatile unsigned short *)0x3FFFC016)
75
#define FIO0PINH_OFFSET 0x16
76
 
77
#define FIO0SET (*(volatile unsigned long *)0x3FFFC018)
78
#define FIO0SET_OFFSET 0x18
79
 
80
#define FIO0SET0 (*(volatile unsigned char *)0x3FFFC018)
81
#define FIO0SET0_OFFSET 0x18
82
 
83
#define FIO0SET1 (*(volatile unsigned char *)0x3FFFC019)
84
#define FIO0SET1_OFFSET 0x19
85
 
86
#define FIO0SET2 (*(volatile unsigned char *)0x3FFFC01A)
87
#define FIO0SET2_OFFSET 0x1A
88
 
89
#define FIO0SET3 (*(volatile unsigned char *)0x3FFFC01B)
90
#define FIO0SET3_OFFSET 0x1B
91
 
92
#define FIO0SETL (*(volatile unsigned short *)0x3FFFC018)
93
#define FIO0SETL_OFFSET 0x18
94
 
95
#define FIO0SETH (*(volatile unsigned short *)0x3FFFC01A)
96
#define FIO0SETH_OFFSET 0x1A
97
 
98
#define FIO0CLR (*(volatile unsigned long *)0x3FFFC01C)
99
#define FIO0CLR_OFFSET 0x1C
100
 
101
#define FIO0CLR0 (*(volatile unsigned char *)0x3FFFC01C)
102
#define FIO0CLR0_OFFSET 0x1C
103
 
104
#define FIO0CLR1 (*(volatile unsigned char *)0x3FFFC01D)
105
#define FIO0CLR1_OFFSET 0x1D
106
 
107
#define FIO0CLR2 (*(volatile unsigned char *)0x3FFFC01E)
108
#define FIO0CLR2_OFFSET 0x1E
109
 
110
#define FIO0CLR3 (*(volatile unsigned char *)0x3FFFC01F)
111
#define FIO0CLR3_OFFSET 0x1F
112
 
113
#define FIO0CLRL (*(volatile unsigned short *)0x3FFFC01C)
114
#define FIO0CLRL_OFFSET 0x1C
115
 
116
#define FIO0CLRH (*(volatile unsigned short *)0x3FFFC01E)
117
#define FIO0CLRH_OFFSET 0x1E
118
 
119
#define FIO1DIR (*(volatile unsigned long *)0x3FFFC020)
120
#define FIO1DIR_OFFSET 0x20
121
 
122
#define FIO1DIR0 (*(volatile unsigned char *)0x3FFFC020)
123
#define FIO1DIR0_OFFSET 0x20
124
 
125
#define FIO1DIR1 (*(volatile unsigned char *)0x3FFFC021)
126
#define FIO1DIR1_OFFSET 0x21
127
 
128
#define FIO1DIR2 (*(volatile unsigned char *)0x3FFFC022)
129
#define FIO1DIR2_OFFSET 0x22
130
 
131
#define FIO1DIR3 (*(volatile unsigned char *)0x3FFFC023)
132
#define FIO1DIR3_OFFSET 0x23
133
 
134
#define FIO1DIRL (*(volatile unsigned short *)0x3FFFC020)
135
#define FIO1DIRL_OFFSET 0x20
136
 
137
#define FIO1DIRH (*(volatile unsigned short *)0x3FFFC022)
138
#define FIO1DIRH_OFFSET 0x22
139
 
140
#define FIO1MASK (*(volatile unsigned long *)0x3FFFC030)
141
#define FIO1MASK_OFFSET 0x30
142
 
143
#define FIO1MASK0 (*(volatile unsigned char *)0x3FFFC030)
144
#define FIO1MASK0_OFFSET 0x30
145
 
146
#define FIO1MASK1 (*(volatile unsigned char *)0x3FFFC031)
147
#define FIO1MASK1_OFFSET 0x31
148
 
149
#define FIO1MASK2 (*(volatile unsigned char *)0x3FFFC032)
150
#define FIO1MASK2_OFFSET 0x32
151
 
152
#define FIO1MASK3 (*(volatile unsigned char *)0x3FFFC033)
153
#define FIO1MASK3_OFFSET 0x33
154
 
155
#define FIO1MASKL (*(volatile unsigned short *)0x3FFFC030)
156
#define FIO1MASKL_OFFSET 0x30
157
 
158
#define FIO1MASKH (*(volatile unsigned short *)0x3FFFC032)
159
#define FIO1MASKH_OFFSET 0x32
160
 
161
#define FIO1PIN (*(volatile unsigned long *)0x3FFFC034)
162
#define FIO1PIN_OFFSET 0x34
163
 
164
#define FIO1PIN0 (*(volatile unsigned char *)0x3FFFC034)
165
#define FIO1PIN0_OFFSET 0x34
166
 
167
#define FIO1PIN1 (*(volatile unsigned char *)0x3FFFC035)
168
#define FIO1PIN1_OFFSET 0x35
169
 
170
#define FIO1PIN2 (*(volatile unsigned char *)0x3FFFC036)
171
#define FIO1PIN2_OFFSET 0x36
172
 
173
#define FIO1PIN3 (*(volatile unsigned char *)0x3FFFC037)
174
#define FIO1PIN3_OFFSET 0x37
175
 
176
#define FIO1PINL (*(volatile unsigned short *)0x3FFFC034)
177
#define FIO1PINL_OFFSET 0x34
178
 
179
#define FIO1PINH (*(volatile unsigned short *)0x3FFFC036)
180
#define FIO1PINH_OFFSET 0x36
181
 
182
#define FIO1SET (*(volatile unsigned long *)0x3FFFC038)
183
#define FIO1SET_OFFSET 0x38
184
 
185
#define FIO1SET0 (*(volatile unsigned char *)0x3FFFC038)
186
#define FIO1SET0_OFFSET 0x38
187
 
188
#define FIO1SET1 (*(volatile unsigned char *)0x3FFFC039)
189
#define FIO1SET1_OFFSET 0x39
190
 
191
#define FIO1SET2 (*(volatile unsigned char *)0x3FFFC03A)
192
#define FIO1SET2_OFFSET 0x3A
193
 
194
#define FIO1SET3 (*(volatile unsigned char *)0x3FFFC03B)
195
#define FIO1SET3_OFFSET 0x3B
196
 
197
#define FIO1SETL (*(volatile unsigned short *)0x3FFFC038)
198
#define FIO1SETL_OFFSET 0x38
199
 
200
#define FIO1SETH (*(volatile unsigned short *)0x3FFFC03A)
201
#define FIO1SETH_OFFSET 0x3A
202
 
203
#define FIO1CLR (*(volatile unsigned long *)0x3FFFC03C)
204
#define FIO1CLR_OFFSET 0x3C
205
 
206
#define FIO1CLR0 (*(volatile unsigned char *)0x3FFFC03C)
207
#define FIO1CLR0_OFFSET 0x3C
208
 
209
#define FIO1CLR1 (*(volatile unsigned char *)0x3FFFC03D)
210
#define FIO1CLR1_OFFSET 0x3D
211
 
212
#define FIO1CLR2 (*(volatile unsigned char *)0x3FFFC03E)
213
#define FIO1CLR2_OFFSET 0x3E
214
 
215
#define FIO1CLR3 (*(volatile unsigned char *)0x3FFFC03F)
216
#define FIO1CLR3_OFFSET 0x3F
217
 
218
#define FIO1CLRL (*(volatile unsigned short *)0x3FFFC03C)
219
#define FIO1CLRL_OFFSET 0x3C
220
 
221
#define FIO1CLRH (*(volatile unsigned short *)0x3FFFC03E)
222
#define FIO1CLRH_OFFSET 0x3E
223
 
224
#define WDT_BASE 0xE0000000
225
 
226
#define WDMOD (*(volatile unsigned long *)0xE0000000)
227
#define WDMOD_OFFSET 0x0
228
#define WDMOD_WDEN_MASK 0x1
229
#define WDMOD_WDEN 0x1
230
#define WDMOD_WDEN_BIT 0
231
#define WDMOD_WDRESET_MASK 0x2
232
#define WDMOD_WDRESET 0x2
233
#define WDMOD_WDRESET_BIT 1
234
#define WDMOD_WDTOF_MASK 0x4
235
#define WDMOD_WDTOF 0x4
236
#define WDMOD_WDTOF_BIT 2
237
#define WDMOD_WDINT_MASK 0x8
238
#define WDMOD_WDINT 0x8
239
#define WDMOD_WDINT_BIT 3
240
 
241
#define WDTC (*(volatile unsigned long *)0xE0000004)
242
#define WDTC_OFFSET 0x4
243
 
244
#define WDFEED (*(volatile unsigned long *)0xE0000008)
245
#define WDFEED_OFFSET 0x8
246
 
247
#define WDTV (*(volatile unsigned long *)0xE000000C)
248
#define WDTV_OFFSET 0xC
249
 
250
#define TIMER0_BASE 0xE0004000
251
 
252
#define T0IR (*(volatile unsigned char *)0xE0004000)
253
#define T0IR_OFFSET 0x0
254
#define T0IR_MR0_MASK 0x1
255
#define T0IR_MR0 0x1
256
#define T0IR_MR0_BIT 0
257
#define T0IR_MR1_MASK 0x2
258
#define T0IR_MR1 0x2
259
#define T0IR_MR1_BIT 1
260
#define T0IR_MR2_MASK 0x4
261
#define T0IR_MR2 0x4
262
#define T0IR_MR2_BIT 2
263
#define T0IR_MR3_MASK 0x8
264
#define T0IR_MR3 0x8
265
#define T0IR_MR3_BIT 3
266
#define T0IR_CR0_MASK 0x10
267
#define T0IR_CR0 0x10
268
#define T0IR_CR0_BIT 4
269
#define T0IR_CR1_MASK 0x20
270
#define T0IR_CR1 0x20
271
#define T0IR_CR1_BIT 5
272
#define T0IR_CR2_MASK 0x40
273
#define T0IR_CR2 0x40
274
#define T0IR_CR2_BIT 6
275
#define T0IR_CR3_MASK 0x80
276
#define T0IR_CR3 0x80
277
#define T0IR_CR3_BIT 7
278
 
279
#define T0TCR (*(volatile unsigned char *)0xE0004004)
280
#define T0TCR_OFFSET 0x4
281
#define T0TCR_Counter_Enable_MASK 0x1
282
#define T0TCR_Counter_Enable 0x1
283
#define T0TCR_Counter_Enable_BIT 0
284
#define T0TCR_Counter_Reset_MASK 0x2
285
#define T0TCR_Counter_Reset 0x2
286
#define T0TCR_Counter_Reset_BIT 1
287
 
288
#define T0TC (*(volatile unsigned long *)0xE0004008)
289
#define T0TC_OFFSET 0x8
290
 
291
#define T0PR (*(volatile unsigned long *)0xE000400C)
292
#define T0PR_OFFSET 0xC
293
 
294
#define T0PC (*(volatile unsigned long *)0xE0004010)
295
#define T0PC_OFFSET 0x10
296
 
297
#define T0MCR (*(volatile unsigned short *)0xE0004014)
298
#define T0MCR_OFFSET 0x14
299
#define T0MCR_MR0I_MASK 0x1
300
#define T0MCR_MR0I 0x1
301
#define T0MCR_MR0I_BIT 0
302
#define T0MCR_MR0R_MASK 0x2
303
#define T0MCR_MR0R 0x2
304
#define T0MCR_MR0R_BIT 1
305
#define T0MCR_MR0S_MASK 0x4
306
#define T0MCR_MR0S 0x4
307
#define T0MCR_MR0S_BIT 2
308
#define T0MCR_MR1I_MASK 0x8
309
#define T0MCR_MR1I 0x8
310
#define T0MCR_MR1I_BIT 3
311
#define T0MCR_MR1R_MASK 0x10
312
#define T0MCR_MR1R 0x10
313
#define T0MCR_MR1R_BIT 4
314
#define T0MCR_MR1S_MASK 0x20
315
#define T0MCR_MR1S 0x20
316
#define T0MCR_MR1S_BIT 5
317
#define T0MCR_MR2I_MASK 0x40
318
#define T0MCR_MR2I 0x40
319
#define T0MCR_MR2I_BIT 6
320
#define T0MCR_MR2R_MASK 0x80
321
#define T0MCR_MR2R 0x80
322
#define T0MCR_MR2R_BIT 7
323
#define T0MCR_MR2S_MASK 0x100
324
#define T0MCR_MR2S 0x100
325
#define T0MCR_MR2S_BIT 8
326
#define T0MCR_MR3I_MASK 0x200
327
#define T0MCR_MR3I 0x200
328
#define T0MCR_MR3I_BIT 9
329
#define T0MCR_MR3R_MASK 0x400
330
#define T0MCR_MR3R 0x400
331
#define T0MCR_MR3R_BIT 10
332
#define T0MCR_MR3S_MASK 0x800
333
#define T0MCR_MR3S 0x800
334
#define T0MCR_MR3S_BIT 11
335
 
336
#define T0MR0 (*(volatile unsigned long *)0xE0004018)
337
#define T0MR0_OFFSET 0x18
338
 
339
#define T0MR1 (*(volatile unsigned long *)0xE000401C)
340
#define T0MR1_OFFSET 0x1C
341
 
342
#define T0MR2 (*(volatile unsigned long *)0xE0004020)
343
#define T0MR2_OFFSET 0x20
344
 
345
#define T0MR3 (*(volatile unsigned long *)0xE0004024)
346
#define T0MR3_OFFSET 0x24
347
 
348
#define T0CCR (*(volatile unsigned short *)0xE0004028)
349
#define T0CCR_OFFSET 0x28
350
#define T0CCR_CAP0RE_MASK 0x1
351
#define T0CCR_CAP0RE 0x1
352
#define T0CCR_CAP0RE_BIT 0
353
#define T0CCR_CAP0FE_MASK 0x2
354
#define T0CCR_CAP0FE 0x2
355
#define T0CCR_CAP0FE_BIT 1
356
#define T0CCR_CAP0I_MASK 0x4
357
#define T0CCR_CAP0I 0x4
358
#define T0CCR_CAP0I_BIT 2
359
#define T0CCR_CAP1RE_MASK 0x8
360
#define T0CCR_CAP1RE 0x8
361
#define T0CCR_CAP1RE_BIT 3
362
#define T0CCR_CAP1FE_MASK 0x10
363
#define T0CCR_CAP1FE 0x10
364
#define T0CCR_CAP1FE_BIT 4
365
#define T0CCR_CAP1I_MASK 0x20
366
#define T0CCR_CAP1I 0x20
367
#define T0CCR_CAP1I_BIT 5
368
#define T0CCR_CAP2RE_MASK 0x40
369
#define T0CCR_CAP2RE 0x40
370
#define T0CCR_CAP2RE_BIT 6
371
#define T0CCR_CAP2FE_MASK 0x80
372
#define T0CCR_CAP2FE 0x80
373
#define T0CCR_CAP2FE_BIT 7
374
#define T0CCR_CAP2I_MASK 0x100
375
#define T0CCR_CAP2I 0x100
376
#define T0CCR_CAP2I_BIT 8
377
#define T0CCR_CAP3RE_MASK 0x200
378
#define T0CCR_CAP3RE 0x200
379
#define T0CCR_CAP3RE_BIT 9
380
#define T0CCR_CAP3FE_MASK 0x400
381
#define T0CCR_CAP3FE 0x400
382
#define T0CCR_CAP3FE_BIT 10
383
#define T0CCR_CAP3I_MASK 0x800
384
#define T0CCR_CAP3I 0x800
385
#define T0CCR_CAP3I_BIT 11
386
 
387
#define T0CR0 (*(volatile unsigned long *)0xE000402C)
388
#define T0CR0_OFFSET 0x2C
389
 
390
#define T0CR1 (*(volatile unsigned long *)0xE0004030)
391
#define T0CR1_OFFSET 0x30
392
 
393
#define T0CR2 (*(volatile unsigned long *)0xE0004034)
394
#define T0CR2_OFFSET 0x34
395
 
396
#define T0CR3 (*(volatile unsigned long *)0xE0004038)
397
#define T0CR3_OFFSET 0x38
398
 
399
#define T0EMR (*(volatile unsigned short *)0xE000403C)
400
#define T0EMR_OFFSET 0x3C
401
#define T0EMR_EM0_MASK 0x1
402
#define T0EMR_EM0 0x1
403
#define T0EMR_EM0_BIT 0
404
#define T0EMR_EM1_MASK 0x2
405
#define T0EMR_EM1 0x2
406
#define T0EMR_EM1_BIT 1
407
#define T0EMR_EM2_MASK 0x4
408
#define T0EMR_EM2 0x4
409
#define T0EMR_EM2_BIT 2
410
#define T0EMR_EM3_MASK 0x8
411
#define T0EMR_EM3 0x8
412
#define T0EMR_EM3_BIT 3
413
#define T0EMR_EMC0_MASK 0x30
414
#define T0EMR_EMC0_BIT 4
415
#define T0EMR_EMC1_MASK 0xC0
416
#define T0EMR_EMC1_BIT 6
417
#define T0EMR_EMC2_MASK 0x300
418
#define T0EMR_EMC2_BIT 8
419
#define T0EMR_EMC3_MASK 0xC00
420
#define T0EMR_EMC3_BIT 10
421
 
422
#define T0CTCR (*(volatile unsigned long *)0xE0004070)
423
#define T0CTCR_OFFSET 0x70
424
#define T0CTCR_Counter_Timer_Mode_MASK 0x3
425
#define T0CTCR_Counter_Timer_Mode_BIT 0
426
#define T0CTCR_Count_Input_Select_MASK 0xC
427
#define T0CTCR_Count_Input_Select_BIT 2
428
 
429
#define TIMER1_BASE 0xE0008000
430
 
431
#define T1IR (*(volatile unsigned char *)0xE0008000)
432
#define T1IR_OFFSET 0x0
433
#define T1IR_MR0_MASK 0x1
434
#define T1IR_MR0 0x1
435
#define T1IR_MR0_BIT 0
436
#define T1IR_MR1_MASK 0x2
437
#define T1IR_MR1 0x2
438
#define T1IR_MR1_BIT 1
439
#define T1IR_MR2_MASK 0x4
440
#define T1IR_MR2 0x4
441
#define T1IR_MR2_BIT 2
442
#define T1IR_MR3_MASK 0x8
443
#define T1IR_MR3 0x8
444
#define T1IR_MR3_BIT 3
445
#define T1IR_CR0_MASK 0x10
446
#define T1IR_CR0 0x10
447
#define T1IR_CR0_BIT 4
448
#define T1IR_CR1_MASK 0x20
449
#define T1IR_CR1 0x20
450
#define T1IR_CR1_BIT 5
451
#define T1IR_CR2_MASK 0x40
452
#define T1IR_CR2 0x40
453
#define T1IR_CR2_BIT 6
454
#define T1IR_CR3_MASK 0x80
455
#define T1IR_CR3 0x80
456
#define T1IR_CR3_BIT 7
457
 
458
#define T1TCR (*(volatile unsigned char *)0xE0008004)
459
#define T1TCR_OFFSET 0x4
460
#define T1TCR_Counter_Enable_MASK 0x1
461
#define T1TCR_Counter_Enable 0x1
462
#define T1TCR_Counter_Enable_BIT 0
463
#define T1TCR_Counter_Reset_MASK 0x2
464
#define T1TCR_Counter_Reset 0x2
465
#define T1TCR_Counter_Reset_BIT 1
466
 
467
#define T1TC (*(volatile unsigned long *)0xE0008008)
468
#define T1TC_OFFSET 0x8
469
 
470
#define T1PR (*(volatile unsigned long *)0xE000800C)
471
#define T1PR_OFFSET 0xC
472
 
473
#define T1PC (*(volatile unsigned long *)0xE0008010)
474
#define T1PC_OFFSET 0x10
475
 
476
#define T1MCR (*(volatile unsigned short *)0xE0008014)
477
#define T1MCR_OFFSET 0x14
478
#define T1MCR_MR0I_MASK 0x1
479
#define T1MCR_MR0I 0x1
480
#define T1MCR_MR0I_BIT 0
481
#define T1MCR_MR0R_MASK 0x2
482
#define T1MCR_MR0R 0x2
483
#define T1MCR_MR0R_BIT 1
484
#define T1MCR_MR0S_MASK 0x4
485
#define T1MCR_MR0S 0x4
486
#define T1MCR_MR0S_BIT 2
487
#define T1MCR_MR1I_MASK 0x8
488
#define T1MCR_MR1I 0x8
489
#define T1MCR_MR1I_BIT 3
490
#define T1MCR_MR1R_MASK 0x10
491
#define T1MCR_MR1R 0x10
492
#define T1MCR_MR1R_BIT 4
493
#define T1MCR_MR1S_MASK 0x20
494
#define T1MCR_MR1S 0x20
495
#define T1MCR_MR1S_BIT 5
496
#define T1MCR_MR2I_MASK 0x40
497
#define T1MCR_MR2I 0x40
498
#define T1MCR_MR2I_BIT 6
499
#define T1MCR_MR2R_MASK 0x80
500
#define T1MCR_MR2R 0x80
501
#define T1MCR_MR2R_BIT 7
502
#define T1MCR_MR2S_MASK 0x100
503
#define T1MCR_MR2S 0x100
504
#define T1MCR_MR2S_BIT 8
505
#define T1MCR_MR3I_MASK 0x200
506
#define T1MCR_MR3I 0x200
507
#define T1MCR_MR3I_BIT 9
508
#define T1MCR_MR3R_MASK 0x400
509
#define T1MCR_MR3R 0x400
510
#define T1MCR_MR3R_BIT 10
511
#define T1MCR_MR3S_MASK 0x800
512
#define T1MCR_MR3S 0x800
513
#define T1MCR_MR3S_BIT 11
514
 
515
#define T1MR0 (*(volatile unsigned long *)0xE0008018)
516
#define T1MR0_OFFSET 0x18
517
 
518
#define T1MR1 (*(volatile unsigned long *)0xE000801C)
519
#define T1MR1_OFFSET 0x1C
520
 
521
#define T1MR2 (*(volatile unsigned long *)0xE0008020)
522
#define T1MR2_OFFSET 0x20
523
 
524
#define T1MR3 (*(volatile unsigned long *)0xE0008024)
525
#define T1MR3_OFFSET 0x24
526
 
527
#define T1CCR (*(volatile unsigned short *)0xE0008028)
528
#define T1CCR_OFFSET 0x28
529
#define T1CCR_CAP0RE_MASK 0x1
530
#define T1CCR_CAP0RE 0x1
531
#define T1CCR_CAP0RE_BIT 0
532
#define T1CCR_CAP0FE_MASK 0x2
533
#define T1CCR_CAP0FE 0x2
534
#define T1CCR_CAP0FE_BIT 1
535
#define T1CCR_CAP0I_MASK 0x4
536
#define T1CCR_CAP0I 0x4
537
#define T1CCR_CAP0I_BIT 2
538
#define T1CCR_CAP1RE_MASK 0x8
539
#define T1CCR_CAP1RE 0x8
540
#define T1CCR_CAP1RE_BIT 3
541
#define T1CCR_CAP1FE_MASK 0x10
542
#define T1CCR_CAP1FE 0x10
543
#define T1CCR_CAP1FE_BIT 4
544
#define T1CCR_CAP1I_MASK 0x20
545
#define T1CCR_CAP1I 0x20
546
#define T1CCR_CAP1I_BIT 5
547
#define T1CCR_CAP2RE_MASK 0x40
548
#define T1CCR_CAP2RE 0x40
549
#define T1CCR_CAP2RE_BIT 6
550
#define T1CCR_CAP2FE_MASK 0x80
551
#define T1CCR_CAP2FE 0x80
552
#define T1CCR_CAP2FE_BIT 7
553
#define T1CCR_CAP2I_MASK 0x100
554
#define T1CCR_CAP2I 0x100
555
#define T1CCR_CAP2I_BIT 8
556
#define T1CCR_CAP3RE_MASK 0x200
557
#define T1CCR_CAP3RE 0x200
558
#define T1CCR_CAP3RE_BIT 9
559
#define T1CCR_CAP3FE_MASK 0x400
560
#define T1CCR_CAP3FE 0x400
561
#define T1CCR_CAP3FE_BIT 10
562
#define T1CCR_CAP3I_MASK 0x800
563
#define T1CCR_CAP3I 0x800
564
#define T1CCR_CAP3I_BIT 11
565
 
566
#define T1CR0 (*(volatile unsigned long *)0xE000802C)
567
#define T1CR0_OFFSET 0x2C
568
 
569
#define T1CR1 (*(volatile unsigned long *)0xE0008030)
570
#define T1CR1_OFFSET 0x30
571
 
572
#define T1CR2 (*(volatile unsigned long *)0xE0008034)
573
#define T1CR2_OFFSET 0x34
574
 
575
#define T1CR3 (*(volatile unsigned long *)0xE0008038)
576
#define T1CR3_OFFSET 0x38
577
 
578
#define T1EMR (*(volatile unsigned short *)0xE000803C)
579
#define T1EMR_OFFSET 0x3C
580
#define T1EMR_EM0_MASK 0x1
581
#define T1EMR_EM0 0x1
582
#define T1EMR_EM0_BIT 0
583
#define T1EMR_EM1_MASK 0x2
584
#define T1EMR_EM1 0x2
585
#define T1EMR_EM1_BIT 1
586
#define T1EMR_EM2_MASK 0x4
587
#define T1EMR_EM2 0x4
588
#define T1EMR_EM2_BIT 2
589
#define T1EMR_EM3_MASK 0x8
590
#define T1EMR_EM3 0x8
591
#define T1EMR_EM3_BIT 3
592
#define T1EMR_EMC0_MASK 0x30
593
#define T1EMR_EMC0_BIT 4
594
#define T1EMR_EMC1_MASK 0xC0
595
#define T1EMR_EMC1_BIT 6
596
#define T1EMR_EMC2_MASK 0x300
597
#define T1EMR_EMC2_BIT 8
598
#define T1EMR_EMC3_MASK 0xC00
599
#define T1EMR_EMC3_BIT 10
600
 
601
#define T1CTCR (*(volatile unsigned long *)0xE0008070)
602
#define T1CTCR_OFFSET 0x70
603
#define T1CTCR_Counter_Timer_Mode_MASK 0x3
604
#define T1CTCR_Counter_Timer_Mode_BIT 0
605
#define T1CTCR_Count_Input_Select_MASK 0xC
606
#define T1CTCR_Count_Input_Select_BIT 2
607
 
608
#define UART0_BASE 0xE000C000
609
 
610
#define U0RBR (*(volatile unsigned char *)0xE000C000)
611
#define U0RBR_OFFSET 0x0
612
 
613
#define U0THR (*(volatile unsigned char *)0xE000C000)
614
#define U0THR_OFFSET 0x0
615
 
616
#define U0DLL (*(volatile unsigned char *)0xE000C000)
617
#define U0DLL_OFFSET 0x0
618
 
619
#define U0DLM (*(volatile unsigned char *)0xE000C004)
620
#define U0DLM_OFFSET 0x4
621
 
622
#define U0IER (*(volatile unsigned long *)0xE000C004)
623
#define U0IER_OFFSET 0x4
624
#define U0IER_RBR_Interrupt_Enable_MASK 0x1
625
#define U0IER_RBR_Interrupt_Enable 0x1
626
#define U0IER_RBR_Interrupt_Enable_BIT 0
627
#define U0IER_THRE_Interrupt_Enable_MASK 0x2
628
#define U0IER_THRE_Interrupt_Enable 0x2
629
#define U0IER_THRE_Interrupt_Enable_BIT 1
630
#define U0IER_Rx_Line_Status_Interrupt_Enable_MASK 0x4
631
#define U0IER_Rx_Line_Status_Interrupt_Enable 0x4
632
#define U0IER_Rx_Line_Status_Interrupt_Enable_BIT 2
633
#define U0IER_ABTOIntEn_MASK 0x100
634
#define U0IER_ABTOIntEn 0x100
635
#define U0IER_ABTOIntEn_BIT 8
636
#define U0IER_ABEOIntEn_MASK 0x200
637
#define U0IER_ABEOIntEn 0x200
638
#define U0IER_ABEOIntEn_BIT 9
639
 
640
#define U0IIR (*(volatile unsigned long *)0xE000C008)
641
#define U0IIR_OFFSET 0x8
642
#define U0IIR_Interrupt_Pending_MASK 0x1
643
#define U0IIR_Interrupt_Pending 0x1
644
#define U0IIR_Interrupt_Pending_BIT 0
645
#define U0IIR_Interrupt_Identification_MASK 0xE
646
#define U0IIR_Interrupt_Identification_BIT 1
647
#define U0IIR_FIFO_Enable_MASK 0xC0
648
#define U0IIR_FIFO_Enable_BIT 6
649
#define U0IIR_ABTOInt_MASK 0x100
650
#define U0IIR_ABTOInt 0x100
651
#define U0IIR_ABTOInt_BIT 8
652
#define U0IIR_ABEOInt_MASK 0x200
653
#define U0IIR_ABEOInt 0x200
654
#define U0IIR_ABEOInt_BIT 9
655
 
656
#define U0FCR (*(volatile unsigned char *)0xE000C008)
657
#define U0FCR_OFFSET 0x8
658
#define U0FCR_FIFO_Enable_MASK 0x1
659
#define U0FCR_FIFO_Enable 0x1
660
#define U0FCR_FIFO_Enable_BIT 0
661
#define U0FCR_Rx_FIFO_Reset_MASK 0x2
662
#define U0FCR_Rx_FIFO_Reset 0x2
663
#define U0FCR_Rx_FIFO_Reset_BIT 1
664
#define U0FCR_Tx_FIFO_Reset_MASK 0x4
665
#define U0FCR_Tx_FIFO_Reset 0x4
666
#define U0FCR_Tx_FIFO_Reset_BIT 2
667
#define U0FCR_Rx_Trigger_Level_Select_MASK 0xC0
668
#define U0FCR_Rx_Trigger_Level_Select_BIT 6
669
 
670
#define U0LCR (*(volatile unsigned char *)0xE000C00C)
671
#define U0LCR_OFFSET 0xC
672
#define U0LCR_Word_Length_Select_MASK 0x3
673
#define U0LCR_Word_Length_Select_BIT 0
674
#define U0LCR_Stop_Bit_Select_MASK 0x4
675
#define U0LCR_Stop_Bit_Select 0x4
676
#define U0LCR_Stop_Bit_Select_BIT 2
677
#define U0LCR_Parity_Enable_MASK 0x8
678
#define U0LCR_Parity_Enable 0x8
679
#define U0LCR_Parity_Enable_BIT 3
680
#define U0LCR_Parity_Select_MASK 0x30
681
#define U0LCR_Parity_Select_BIT 4
682
#define U0LCR_Break_Control_MASK 0x40
683
#define U0LCR_Break_Control 0x40
684
#define U0LCR_Break_Control_BIT 6
685
#define U0LCR_Divisor_Latch_Access_Bit_MASK 0x80
686
#define U0LCR_Divisor_Latch_Access_Bit 0x80
687
#define U0LCR_Divisor_Latch_Access_Bit_BIT 7
688
 
689
#define U0LSR (*(volatile unsigned char *)0xE000C014)
690
#define U0LSR_OFFSET 0x14
691
#define U0LSR_RDR_MASK 0x1
692
#define U0LSR_RDR 0x1
693
#define U0LSR_RDR_BIT 0
694
#define U0LSR_OE_MASK 0x2
695
#define U0LSR_OE 0x2
696
#define U0LSR_OE_BIT 1
697
#define U0LSR_PE_MASK 0x4
698
#define U0LSR_PE 0x4
699
#define U0LSR_PE_BIT 2
700
#define U0LSR_FE_MASK 0x8
701
#define U0LSR_FE 0x8
702
#define U0LSR_FE_BIT 3
703
#define U0LSR_BI_MASK 0x10
704
#define U0LSR_BI 0x10
705
#define U0LSR_BI_BIT 4
706
#define U0LSR_THRE_MASK 0x20
707
#define U0LSR_THRE 0x20
708
#define U0LSR_THRE_BIT 5
709
#define U0LSR_TEMT_MASK 0x40
710
#define U0LSR_TEMT 0x40
711
#define U0LSR_TEMT_BIT 6
712
#define U0LSR_RXFE_MASK 0x80
713
#define U0LSR_RXFE 0x80
714
#define U0LSR_RXFE_BIT 7
715
 
716
#define U0SCR (*(volatile unsigned char *)0xE000C01C)
717
#define U0SCR_OFFSET 0x1C
718
 
719
#define U0ACR (*(volatile unsigned long *)0xE000C020)
720
#define U0ACR_OFFSET 0x20
721
#define U0ACR_Start_MASK 0x1
722
#define U0ACR_Start 0x1
723
#define U0ACR_Start_BIT 0
724
#define U0ACR_Mode_MASK 0x2
725
#define U0ACR_Mode 0x2
726
#define U0ACR_Mode_BIT 1
727
#define U0ACR_AutoRestart_MASK 0x4
728
#define U0ACR_AutoRestart 0x4
729
#define U0ACR_AutoRestart_BIT 2
730
#define U0ACR_ABEOIntClr_MASK 0x100
731
#define U0ACR_ABEOIntClr 0x100
732
#define U0ACR_ABEOIntClr_BIT 8
733
#define U0ACR_ABTOIntClr_MASK 0x200
734
#define U0ACR_ABTOIntClr 0x200
735
#define U0ACR_ABTOIntClr_BIT 9
736
 
737
#define U0FDR (*(volatile unsigned long *)0xE000C028)
738
#define U0FDR_OFFSET 0x28
739
#define U0FDR_DIVADDVAL_MASK 0xF
740
#define U0FDR_DIVADDVAL_BIT 0
741
#define U0FDR_MULVAL_MASK 0xF0
742
#define U0FDR_MULVAL_BIT 4
743
 
744
#define U0TER (*(volatile unsigned char *)0xE000C030)
745
#define U0TER_OFFSET 0x30
746
#define U0TER_TXEN_MASK 0x80
747
#define U0TER_TXEN 0x80
748
#define U0TER_TXEN_BIT 7
749
 
750
#define UART1_BASE 0xE0010000
751
 
752
#define U1RBR (*(volatile unsigned char *)0xE0010000)
753
#define U1RBR_OFFSET 0x0
754
 
755
#define U1THR (*(volatile unsigned char *)0xE0010000)
756
#define U1THR_OFFSET 0x0
757
 
758
#define U1DLL (*(volatile unsigned char *)0xE0010000)
759
#define U1DLL_OFFSET 0x0
760
 
761
#define U1DLM (*(volatile unsigned char *)0xE0010004)
762
#define U1DLM_OFFSET 0x4
763
 
764
#define U1IER (*(volatile unsigned long *)0xE0010004)
765
#define U1IER_OFFSET 0x4
766
#define U1IER_RBR_Interrupt_Enable_MASK 0x1
767
#define U1IER_RBR_Interrupt_Enable 0x1
768
#define U1IER_RBR_Interrupt_Enable_BIT 0
769
#define U1IER_THRE_Interrupt_Enable_MASK 0x2
770
#define U1IER_THRE_Interrupt_Enable 0x2
771
#define U1IER_THRE_Interrupt_Enable_BIT 1
772
#define U1IER_Rx_Line_Status_Interrupt_Enable_MASK 0x4
773
#define U1IER_Rx_Line_Status_Interrupt_Enable 0x4
774
#define U1IER_Rx_Line_Status_Interrupt_Enable_BIT 2
775
#define U1IER_Modem_Status_Interrupt_Enable_MASK 0x8
776
#define U1IER_Modem_Status_Interrupt_Enable 0x8
777
#define U1IER_Modem_Status_Interrupt_Enable_BIT 3
778
#define U1IER_CTS_Interrupt_Enable_MASK 0x80
779
#define U1IER_CTS_Interrupt_Enable 0x80
780
#define U1IER_CTS_Interrupt_Enable_BIT 7
781
#define U1IER_ABTOIntEn_MASK 0x100
782
#define U1IER_ABTOIntEn 0x100
783
#define U1IER_ABTOIntEn_BIT 8
784
#define U1IER_ABEOIntEn_MASK 0x200
785
#define U1IER_ABEOIntEn 0x200
786
#define U1IER_ABEOIntEn_BIT 9
787
 
788
#define U1IIR (*(volatile unsigned long *)0xE0010008)
789
#define U1IIR_OFFSET 0x8
790
#define U1IIR_Interrupt_Pending_MASK 0x1
791
#define U1IIR_Interrupt_Pending 0x1
792
#define U1IIR_Interrupt_Pending_BIT 0
793
#define U1IIR_Interrupt_Identification_MASK 0xE
794
#define U1IIR_Interrupt_Identification_BIT 1
795
#define U1IIR_FIFO_Enable_MASK 0xC0
796
#define U1IIR_FIFO_Enable_BIT 6
797
#define U1IIR_ABEOInt_MASK 0x100
798
#define U1IIR_ABEOInt 0x100
799
#define U1IIR_ABEOInt_BIT 8
800
#define U1IIR_ABTOInt_MASK 0x200
801
#define U1IIR_ABTOInt 0x200
802
#define U1IIR_ABTOInt_BIT 9
803
 
804
#define U1FCR (*(volatile unsigned char *)0xE0010008)
805
#define U1FCR_OFFSET 0x8
806
#define U1FCR_FIFO_Enable_MASK 0x1
807
#define U1FCR_FIFO_Enable 0x1
808
#define U1FCR_FIFO_Enable_BIT 0
809
#define U1FCR_Rx_FIFO_Reset_MASK 0x2
810
#define U1FCR_Rx_FIFO_Reset 0x2
811
#define U1FCR_Rx_FIFO_Reset_BIT 1
812
#define U1FCR_Tx_FIFO_Reset_MASK 0x4
813
#define U1FCR_Tx_FIFO_Reset 0x4
814
#define U1FCR_Tx_FIFO_Reset_BIT 2
815
#define U1FCR_Rx_Trigger_Level_Select_MASK 0xC0
816
#define U1FCR_Rx_Trigger_Level_Select_BIT 6
817
 
818
#define U1LCR (*(volatile unsigned char *)0xE001000C)
819
#define U1LCR_OFFSET 0xC
820
#define U1LCR_Word_Length_Select_MASK 0x3
821
#define U1LCR_Word_Length_Select_BIT 0
822
#define U1LCR_Stop_Bit_Select_MASK 0x4
823
#define U1LCR_Stop_Bit_Select 0x4
824
#define U1LCR_Stop_Bit_Select_BIT 2
825
#define U1LCR_Parity_Enable_MASK 0x8
826
#define U1LCR_Parity_Enable 0x8
827
#define U1LCR_Parity_Enable_BIT 3
828
#define U1LCR_Parity_Select_MASK 0x30
829
#define U1LCR_Parity_Select_BIT 4
830
#define U1LCR_Break_Control_MASK 0x40
831
#define U1LCR_Break_Control 0x40
832
#define U1LCR_Break_Control_BIT 6
833
#define U1LCR_Divisor_Latch_Access_Bit_MASK 0x80
834
#define U1LCR_Divisor_Latch_Access_Bit 0x80
835
#define U1LCR_Divisor_Latch_Access_Bit_BIT 7
836
 
837
#define U1MCR (*(volatile unsigned char *)0xE0010010)
838
#define U1MCR_OFFSET 0x10
839
#define U1MCR_DTR_Control_MASK 0x1
840
#define U1MCR_DTR_Control 0x1
841
#define U1MCR_DTR_Control_BIT 0
842
#define U1MCR_RTS_Control_MASK 0x2
843
#define U1MCR_RTS_Control 0x2
844
#define U1MCR_RTS_Control_BIT 1
845
#define U1MCR_Loopback_Mode_Select_MASK 0x10
846
#define U1MCR_Loopback_Mode_Select 0x10
847
#define U1MCR_Loopback_Mode_Select_BIT 4
848
#define U1MCR_RTSen_MASK 0x40
849
#define U1MCR_RTSen 0x40
850
#define U1MCR_RTSen_BIT 6
851
#define U1MCR_CTSen_MASK 0x80
852
#define U1MCR_CTSen 0x80
853
#define U1MCR_CTSen_BIT 7
854
 
855
#define U1LSR (*(volatile unsigned char *)0xE0010014)
856
#define U1LSR_OFFSET 0x14
857
#define U1LSR_RDR_MASK 0x1
858
#define U1LSR_RDR 0x1
859
#define U1LSR_RDR_BIT 0
860
#define U1LSR_OE_MASK 0x2
861
#define U1LSR_OE 0x2
862
#define U1LSR_OE_BIT 1
863
#define U1LSR_PE_MASK 0x4
864
#define U1LSR_PE 0x4
865
#define U1LSR_PE_BIT 2
866
#define U1LSR_FE_MASK 0x8
867
#define U1LSR_FE 0x8
868
#define U1LSR_FE_BIT 3
869
#define U1LSR_BI_MASK 0x10
870
#define U1LSR_BI 0x10
871
#define U1LSR_BI_BIT 4
872
#define U1LSR_THRE_MASK 0x20
873
#define U1LSR_THRE 0x20
874
#define U1LSR_THRE_BIT 5
875
#define U1LSR_TEMT_MASK 0x40
876
#define U1LSR_TEMT 0x40
877
#define U1LSR_TEMT_BIT 6
878
#define U1LSR_RXFE_MASK 0x80
879
#define U1LSR_RXFE 0x80
880
#define U1LSR_RXFE_BIT 7
881
 
882
#define U1MSR (*(volatile unsigned char *)0xE0010018)
883
#define U1MSR_OFFSET 0x18
884
#define U1MSR_Delta_CTS_MASK 0x1
885
#define U1MSR_Delta_CTS 0x1
886
#define U1MSR_Delta_CTS_BIT 0
887
#define U1MSR_Delta_DSR_MASK 0x2
888
#define U1MSR_Delta_DSR 0x2
889
#define U1MSR_Delta_DSR_BIT 1
890
#define U1MSR_Trailing_Edge_RI_MASK 0x4
891
#define U1MSR_Trailing_Edge_RI 0x4
892
#define U1MSR_Trailing_Edge_RI_BIT 2
893
#define U1MSR_Delta_DCD_MASK 0x8
894
#define U1MSR_Delta_DCD 0x8
895
#define U1MSR_Delta_DCD_BIT 3
896
#define U1MSR_CTS_MASK 0x10
897
#define U1MSR_CTS 0x10
898
#define U1MSR_CTS_BIT 4
899
#define U1MSR_DSR_MASK 0x20
900
#define U1MSR_DSR 0x20
901
#define U1MSR_DSR_BIT 5
902
#define U1MSR_RI_MASK 0x40
903
#define U1MSR_RI 0x40
904
#define U1MSR_RI_BIT 6
905
#define U1MSR_DCD_MASK 0x80
906
#define U1MSR_DCD 0x80
907
#define U1MSR_DCD_BIT 7
908
 
909
#define U1SCR (*(volatile unsigned char *)0xE001001C)
910
#define U1SCR_OFFSET 0x1C
911
 
912
#define U1ACR (*(volatile unsigned long *)0xE0010020)
913
#define U1ACR_OFFSET 0x20
914
#define U1ACR_Start_MASK 0x1
915
#define U1ACR_Start 0x1
916
#define U1ACR_Start_BIT 0
917
#define U1ACR_Mode_MASK 0x2
918
#define U1ACR_Mode 0x2
919
#define U1ACR_Mode_BIT 1
920
#define U1ACR_AutoRestart_MASK 0x4
921
#define U1ACR_AutoRestart 0x4
922
#define U1ACR_AutoRestart_BIT 2
923
#define U1ACR_ABEOIntClr_MASK 0x100
924
#define U1ACR_ABEOIntClr 0x100
925
#define U1ACR_ABEOIntClr_BIT 8
926
#define U1ACR_ABTOIntClr_MASK 0x200
927
#define U1ACR_ABTOIntClr 0x200
928
#define U1ACR_ABTOIntClr_BIT 9
929
 
930
#define U1FDR (*(volatile unsigned long *)0xE0010028)
931
#define U1FDR_OFFSET 0x28
932
#define U1FDR_DIVADDVAL_MASK 0xF
933
#define U1FDR_DIVADDVAL_BIT 0
934
#define U1FDR_MULVAL_MASK 0xF0
935
#define U1FDR_MULVAL_BIT 4
936
 
937
#define U1TER (*(volatile unsigned char *)0xE0010030)
938
#define U1TER_OFFSET 0x30
939
#define U1TER_TXEN_MASK 0x80
940
#define U1TER_TXEN 0x80
941
#define U1TER_TXEN_BIT 7
942
 
943
#define PWM_BASE 0xE0014000
944
 
945
#define PWMIR (*(volatile unsigned long *)0xE0014000)
946
#define PWMIR_OFFSET 0x0
947
#define PWMIR_PWMMR0_Interrupt_MASK 0x1
948
#define PWMIR_PWMMR0_Interrupt 0x1
949
#define PWMIR_PWMMR0_Interrupt_BIT 0
950
#define PWMIR_PWMMR1_Interrupt_MASK 0x2
951
#define PWMIR_PWMMR1_Interrupt 0x2
952
#define PWMIR_PWMMR1_Interrupt_BIT 1
953
#define PWMIR_PWMMR2_Interrupt_MASK 0x4
954
#define PWMIR_PWMMR2_Interrupt 0x4
955
#define PWMIR_PWMMR2_Interrupt_BIT 2
956
#define PWMIR_PWMMR3_Interrupt_MASK 0x8
957
#define PWMIR_PWMMR3_Interrupt 0x8
958
#define PWMIR_PWMMR3_Interrupt_BIT 3
959
#define PWMIR_PWMMR4_Interrupt_MASK 0x100
960
#define PWMIR_PWMMR4_Interrupt 0x100
961
#define PWMIR_PWMMR4_Interrupt_BIT 8
962
#define PWMIR_PWMMR5_Interrupt_MASK 0x200
963
#define PWMIR_PWMMR5_Interrupt 0x200
964
#define PWMIR_PWMMR5_Interrupt_BIT 9
965
#define PWMIR_PWMMR6_Interrupt_MASK 0x400
966
#define PWMIR_PWMMR6_Interrupt 0x400
967
#define PWMIR_PWMMR6_Interrupt_BIT 10
968
 
969
#define PWMTCR (*(volatile unsigned long *)0xE0014004)
970
#define PWMTCR_OFFSET 0x4
971
#define PWMTCR_Counter_Enable_MASK 0x1
972
#define PWMTCR_Counter_Enable 0x1
973
#define PWMTCR_Counter_Enable_BIT 0
974
#define PWMTCR_Counter_Reset_MASK 0x2
975
#define PWMTCR_Counter_Reset 0x2
976
#define PWMTCR_Counter_Reset_BIT 1
977
#define PWMTCR_PWM_Enable_MASK 0x8
978
#define PWMTCR_PWM_Enable 0x8
979
#define PWMTCR_PWM_Enable_BIT 3
980
 
981
#define PWMTC (*(volatile unsigned long *)0xE0014008)
982
#define PWMTC_OFFSET 0x8
983
 
984
#define PWMPR (*(volatile unsigned long *)0xE001400C)
985
#define PWMPR_OFFSET 0xC
986
 
987
#define PWMPC (*(volatile unsigned long *)0xE0014010)
988
#define PWMPC_OFFSET 0x10
989
 
990
#define PWMMCR (*(volatile unsigned long *)0xE0014014)
991
#define PWMMCR_OFFSET 0x14
992
#define PWMMCR_PWMMR0I_MASK 0x1
993
#define PWMMCR_PWMMR0I 0x1
994
#define PWMMCR_PWMMR0I_BIT 0
995
#define PWMMCR_PWMMR0R_MASK 0x2
996
#define PWMMCR_PWMMR0R 0x2
997
#define PWMMCR_PWMMR0R_BIT 1
998
#define PWMMCR_PWMMR0S_MASK 0x4
999
#define PWMMCR_PWMMR0S 0x4
1000
#define PWMMCR_PWMMR0S_BIT 2
1001
#define PWMMCR_PWMMR1I_MASK 0x8
1002
#define PWMMCR_PWMMR1I 0x8
1003
#define PWMMCR_PWMMR1I_BIT 3
1004
#define PWMMCR_PWMMR1R_MASK 0x10
1005
#define PWMMCR_PWMMR1R 0x10
1006
#define PWMMCR_PWMMR1R_BIT 4
1007
#define PWMMCR_PWMMR1S_MASK 0x20
1008
#define PWMMCR_PWMMR1S 0x20
1009
#define PWMMCR_PWMMR1S_BIT 5
1010
#define PWMMCR_PWMMR2I_MASK 0x40
1011
#define PWMMCR_PWMMR2I 0x40
1012
#define PWMMCR_PWMMR2I_BIT 6
1013
#define PWMMCR_PWMMR2R_MASK 0x80
1014
#define PWMMCR_PWMMR2R 0x80
1015
#define PWMMCR_PWMMR2R_BIT 7
1016
#define PWMMCR_PWMMR2S_MASK 0x100
1017
#define PWMMCR_PWMMR2S 0x100
1018
#define PWMMCR_PWMMR2S_BIT 8
1019
#define PWMMCR_PWMMR3I_MASK 0x200
1020
#define PWMMCR_PWMMR3I 0x200
1021
#define PWMMCR_PWMMR3I_BIT 9
1022
#define PWMMCR_PWMMR3R_MASK 0x400
1023
#define PWMMCR_PWMMR3R 0x400
1024
#define PWMMCR_PWMMR3R_BIT 10
1025
#define PWMMCR_PWMMR3S_MASK 0x800
1026
#define PWMMCR_PWMMR3S 0x800
1027
#define PWMMCR_PWMMR3S_BIT 11
1028
#define PWMMCR_PWMMR4I_MASK 0x1000
1029
#define PWMMCR_PWMMR4I 0x1000
1030
#define PWMMCR_PWMMR4I_BIT 12
1031
#define PWMMCR_PWMMR4R_MASK 0x2000
1032
#define PWMMCR_PWMMR4R 0x2000
1033
#define PWMMCR_PWMMR4R_BIT 13
1034
#define PWMMCR_PWMMR4S_MASK 0x4000
1035
#define PWMMCR_PWMMR4S 0x4000
1036
#define PWMMCR_PWMMR4S_BIT 14
1037
#define PWMMCR_PWMMR5I_MASK 0x8000
1038
#define PWMMCR_PWMMR5I 0x8000
1039
#define PWMMCR_PWMMR5I_BIT 15
1040
#define PWMMCR_PWMMR5R_MASK 0x10000
1041
#define PWMMCR_PWMMR5R 0x10000
1042
#define PWMMCR_PWMMR5R_BIT 16
1043
#define PWMMCR_PWMMR5S_MASK 0x20000
1044
#define PWMMCR_PWMMR5S 0x20000
1045
#define PWMMCR_PWMMR5S_BIT 17
1046
#define PWMMCR_PWMMR6I_MASK 0x40000
1047
#define PWMMCR_PWMMR6I 0x40000
1048
#define PWMMCR_PWMMR6I_BIT 18
1049
#define PWMMCR_PWMMR6R_MASK 0x80000
1050
#define PWMMCR_PWMMR6R 0x80000
1051
#define PWMMCR_PWMMR6R_BIT 19
1052
#define PWMMCR_PWMMR6S_MASK 0x100000
1053
#define PWMMCR_PWMMR6S 0x100000
1054
#define PWMMCR_PWMMR6S_BIT 20
1055
 
1056
#define PWMMR0 (*(volatile unsigned long *)0xE0014018)
1057
#define PWMMR0_OFFSET 0x18
1058
 
1059
#define PWMMR1 (*(volatile unsigned long *)0xE001401C)
1060
#define PWMMR1_OFFSET 0x1C
1061
 
1062
#define PWMMR2 (*(volatile unsigned long *)0xE0014020)
1063
#define PWMMR2_OFFSET 0x20
1064
 
1065
#define PWMMR3 (*(volatile unsigned long *)0xE0014024)
1066
#define PWMMR3_OFFSET 0x24
1067
 
1068
#define PWMMR4 (*(volatile unsigned long *)0xE0014040)
1069
#define PWMMR4_OFFSET 0x40
1070
 
1071
#define PWMMR5 (*(volatile unsigned long *)0xE0014044)
1072
#define PWMMR5_OFFSET 0x44
1073
 
1074
#define PWMMR6 (*(volatile unsigned long *)0xE0014048)
1075
#define PWMMR6_OFFSET 0x48
1076
 
1077
#define PWMPCR (*(volatile unsigned long *)0xE001404C)
1078
#define PWMPCR_OFFSET 0x4C
1079
#define PWMPCR_PWMSEL2_MASK 0x4
1080
#define PWMPCR_PWMSEL2 0x4
1081
#define PWMPCR_PWMSEL2_BIT 2
1082
#define PWMPCR_PWMSEL3_MASK 0x8
1083
#define PWMPCR_PWMSEL3 0x8
1084
#define PWMPCR_PWMSEL3_BIT 3
1085
#define PWMPCR_PWMSEL4_MASK 0x10
1086
#define PWMPCR_PWMSEL4 0x10
1087
#define PWMPCR_PWMSEL4_BIT 4
1088
#define PWMPCR_PWMSEL5_MASK 0x20
1089
#define PWMPCR_PWMSEL5 0x20
1090
#define PWMPCR_PWMSEL5_BIT 5
1091
#define PWMPCR_PWMSEL6_MASK 0x40
1092
#define PWMPCR_PWMSEL6 0x40
1093
#define PWMPCR_PWMSEL6_BIT 6
1094
#define PWMPCR_PWMENA1_MASK 0x200
1095
#define PWMPCR_PWMENA1 0x200
1096
#define PWMPCR_PWMENA1_BIT 9
1097
#define PWMPCR_PWMENA2_MASK 0x400
1098
#define PWMPCR_PWMENA2 0x400
1099
#define PWMPCR_PWMENA2_BIT 10
1100
#define PWMPCR_PWMENA3_MASK 0x800
1101
#define PWMPCR_PWMENA3 0x800
1102
#define PWMPCR_PWMENA3_BIT 11
1103
#define PWMPCR_PWMENA4_MASK 0x1000
1104
#define PWMPCR_PWMENA4 0x1000
1105
#define PWMPCR_PWMENA4_BIT 12
1106
#define PWMPCR_PWMENA5_MASK 0x2000
1107
#define PWMPCR_PWMENA5 0x2000
1108
#define PWMPCR_PWMENA5_BIT 13
1109
#define PWMPCR_PWMENA6_MASK 0x4000
1110
#define PWMPCR_PWMENA6 0x4000
1111
#define PWMPCR_PWMENA6_BIT 14
1112
 
1113
#define PWMLER (*(volatile unsigned long *)0xE0014050)
1114
#define PWMLER_OFFSET 0x50
1115
#define PWMLER_Enable_PWM_Match_0_Latch_MASK 0x1
1116
#define PWMLER_Enable_PWM_Match_0_Latch 0x1
1117
#define PWMLER_Enable_PWM_Match_0_Latch_BIT 0
1118
#define PWMLER_Enable_PWM_Match_1_Latch_MASK 0x2
1119
#define PWMLER_Enable_PWM_Match_1_Latch 0x2
1120
#define PWMLER_Enable_PWM_Match_1_Latch_BIT 1
1121
#define PWMLER_Enable_PWM_Match_2_Latch_MASK 0x4
1122
#define PWMLER_Enable_PWM_Match_2_Latch 0x4
1123
#define PWMLER_Enable_PWM_Match_2_Latch_BIT 2
1124
#define PWMLER_Enable_PWM_Match_3_Latch_MASK 0x8
1125
#define PWMLER_Enable_PWM_Match_3_Latch 0x8
1126
#define PWMLER_Enable_PWM_Match_3_Latch_BIT 3
1127
#define PWMLER_Enable_PWM_Match_4_Latch_MASK 0x10
1128
#define PWMLER_Enable_PWM_Match_4_Latch 0x10
1129
#define PWMLER_Enable_PWM_Match_4_Latch_BIT 4
1130
#define PWMLER_Enable_PWM_Match_5_Latch_MASK 0x20
1131
#define PWMLER_Enable_PWM_Match_5_Latch 0x20
1132
#define PWMLER_Enable_PWM_Match_5_Latch_BIT 5
1133
#define PWMLER_Enable_PWM_Match_6_Latch_MASK 0x40
1134
#define PWMLER_Enable_PWM_Match_6_Latch 0x40
1135
#define PWMLER_Enable_PWM_Match_6_Latch_BIT 6
1136
 
1137
#define I2C_BASE 0xE001C000
1138
 
1139
#define I2CONSET (*(volatile unsigned char *)0xE001C000)
1140
#define I2CONSET_OFFSET 0x0
1141
#define I2CONSET_AA_MASK 0x4
1142
#define I2CONSET_AA 0x4
1143
#define I2CONSET_AA_BIT 2
1144
#define I2CONSET_SI_MASK 0x8
1145
#define I2CONSET_SI 0x8
1146
#define I2CONSET_SI_BIT 3
1147
#define I2CONSET_STO_MASK 0x10
1148
#define I2CONSET_STO 0x10
1149
#define I2CONSET_STO_BIT 4
1150
#define I2CONSET_STA_MASK 0x20
1151
#define I2CONSET_STA 0x20
1152
#define I2CONSET_STA_BIT 5
1153
#define I2CONSET_I2EN_MASK 0x40
1154
#define I2CONSET_I2EN 0x40
1155
#define I2CONSET_I2EN_BIT 6
1156
 
1157
#define I2STAT (*(volatile unsigned char *)0xE001C004)
1158
#define I2STAT_OFFSET 0x4
1159
#define I2STAT_Status_MASK 0xF8
1160
#define I2STAT_Status_BIT 3
1161
 
1162
#define I2DAT (*(volatile unsigned char *)0xE001C008)
1163
#define I2DAT_OFFSET 0x8
1164
 
1165
#define I2ADR (*(volatile unsigned char *)0xE001C00C)
1166
#define I2ADR_OFFSET 0xC
1167
#define I2ADR_GC_MASK 0x1
1168
#define I2ADR_GC 0x1
1169
#define I2ADR_GC_BIT 0
1170
#define I2ADR_Address_MASK 0x7E
1171
#define I2ADR_Address_BIT 1
1172
 
1173
#define I2SCLH (*(volatile unsigned short *)0xE001C010)
1174
#define I2SCLH_OFFSET 0x10
1175
 
1176
#define I2SCLL (*(volatile unsigned short *)0xE001C014)
1177
#define I2SCLL_OFFSET 0x14
1178
 
1179
#define I2CONCLR (*(volatile unsigned char *)0xE001C018)
1180
#define I2CONCLR_OFFSET 0x18
1181
#define I2CONCLR_AAC_MASK 0x4
1182
#define I2CONCLR_AAC 0x4
1183
#define I2CONCLR_AAC_BIT 2
1184
#define I2CONCLR_SIC_MASK 0x8
1185
#define I2CONCLR_SIC 0x8
1186
#define I2CONCLR_SIC_BIT 3
1187
#define I2CONCLR_STAC_MASK 0x20
1188
#define I2CONCLR_STAC 0x20
1189
#define I2CONCLR_STAC_BIT 5
1190
#define I2CONCLR_I2ENC_MASK 0x40
1191
#define I2CONCLR_I2ENC 0x40
1192
#define I2CONCLR_I2ENC_BIT 6
1193
 
1194
#define SPI0_BASE 0xE0020000
1195
 
1196
#define S0SPCR (*(volatile unsigned short *)0xE0020000)
1197
#define S0SPCR_OFFSET 0x0
1198
#define S0SPCR_BitEnable_MASK 0x4
1199
#define S0SPCR_BitEnable 0x4
1200
#define S0SPCR_BitEnable_BIT 2
1201
#define S0SPCR_CPHA_MASK 0x8
1202
#define S0SPCR_CPHA 0x8
1203
#define S0SPCR_CPHA_BIT 3
1204
#define S0SPCR_CPOL_MASK 0x10
1205
#define S0SPCR_CPOL 0x10
1206
#define S0SPCR_CPOL_BIT 4
1207
#define S0SPCR_MSTR_MASK 0x20
1208
#define S0SPCR_MSTR 0x20
1209
#define S0SPCR_MSTR_BIT 5
1210
#define S0SPCR_LSBF_MASK 0x40
1211
#define S0SPCR_LSBF 0x40
1212
#define S0SPCR_LSBF_BIT 6
1213
#define S0SPCR_SPIE_MASK 0x80
1214
#define S0SPCR_SPIE 0x80
1215
#define S0SPCR_SPIE_BIT 7
1216
#define S0SPCR_BITS_MASK 0xF00
1217
#define S0SPCR_BITS_BIT 8
1218
 
1219
#define S0SPSR (*(volatile unsigned char *)0xE0020004)
1220
#define S0SPSR_OFFSET 0x4
1221
#define S0SPSR_ABRT_MASK 0x8
1222
#define S0SPSR_ABRT 0x8
1223
#define S0SPSR_ABRT_BIT 3
1224
#define S0SPSR_MODF_MASK 0x10
1225
#define S0SPSR_MODF 0x10
1226
#define S0SPSR_MODF_BIT 4
1227
#define S0SPSR_ROVR_MASK 0x20
1228
#define S0SPSR_ROVR 0x20
1229
#define S0SPSR_ROVR_BIT 5
1230
#define S0SPSR_WCOL_MASK 0x40
1231
#define S0SPSR_WCOL 0x40
1232
#define S0SPSR_WCOL_BIT 6
1233
#define S0SPSR_SPIF_MASK 0x80
1234
#define S0SPSR_SPIF 0x80
1235
#define S0SPSR_SPIF_BIT 7
1236
 
1237
#define S0SPDR (*(volatile unsigned short *)0xE0020008)
1238
#define S0SPDR_OFFSET 0x8
1239
 
1240
#define S0SPCCR (*(volatile unsigned char *)0xE002000C)
1241
#define S0SPCCR_OFFSET 0xC
1242
 
1243
#define S0SPINT (*(volatile unsigned char *)0xE002001C)
1244
#define S0SPINT_OFFSET 0x1C
1245
 
1246
#define RTC_BASE 0xE0024000
1247
 
1248
#define ILR (*(volatile unsigned long *)0xE0024000)
1249
#define ILR_OFFSET 0x0
1250
#define ILR_RTCCIF_MASK 0x1
1251
#define ILR_RTCCIF 0x1
1252
#define ILR_RTCCIF_BIT 0
1253
#define ILR_RTCALF_MASK 0x2
1254
#define ILR_RTCALF 0x2
1255
#define ILR_RTCALF_BIT 1
1256
 
1257
#define CTC (*(volatile unsigned long *)0xE0024004)
1258
#define CTC_OFFSET 0x4
1259
#define CTC_Clock_Tick_Counter_MASK 0xFFFE
1260
#define CTC_Clock_Tick_Counter_BIT 1
1261
 
1262
#define CCR (*(volatile unsigned long *)0xE0024008)
1263
#define CCR_OFFSET 0x8
1264
#define CCR_CLKEN_MASK 0x1
1265
#define CCR_CLKEN 0x1
1266
#define CCR_CLKEN_BIT 0
1267
#define CCR_CTCRST_MASK 0x2
1268
#define CCR_CTCRST 0x2
1269
#define CCR_CTCRST_BIT 1
1270
#define CCR_CTTEST_MASK 0xC
1271
#define CCR_CTTEST_BIT 2
1272
 
1273
#define CIIR (*(volatile unsigned long *)0xE002400C)
1274
#define CIIR_OFFSET 0xC
1275
#define CIIR_IMSEC_MASK 0x1
1276
#define CIIR_IMSEC 0x1
1277
#define CIIR_IMSEC_BIT 0
1278
#define CIIR_IMMIN_MASK 0x2
1279
#define CIIR_IMMIN 0x2
1280
#define CIIR_IMMIN_BIT 1
1281
#define CIIR_IMHOUR_MASK 0x4
1282
#define CIIR_IMHOUR 0x4
1283
#define CIIR_IMHOUR_BIT 2
1284
#define CIIR_IMDOM_MASK 0x8
1285
#define CIIR_IMDOM 0x8
1286
#define CIIR_IMDOM_BIT 3
1287
#define CIIR_IMDOW_MASK 0x10
1288
#define CIIR_IMDOW 0x10
1289
#define CIIR_IMDOW_BIT 4
1290
#define CIIR_IMDOY_MASK 0x20
1291
#define CIIR_IMDOY 0x20
1292
#define CIIR_IMDOY_BIT 5
1293
#define CIIR_IMMON_MASK 0x40
1294
#define CIIR_IMMON 0x40
1295
#define CIIR_IMMON_BIT 6
1296
#define CIIR_IMYEAR_MASK 0x80
1297
#define CIIR_IMYEAR 0x80
1298
#define CIIR_IMYEAR_BIT 7
1299
 
1300
#define AMR (*(volatile unsigned long *)0xE0024010)
1301
#define AMR_OFFSET 0x10
1302
#define AMR_AMRSEC_MASK 0x1
1303
#define AMR_AMRSEC 0x1
1304
#define AMR_AMRSEC_BIT 0
1305
#define AMR_AMRMIN_MASK 0x2
1306
#define AMR_AMRMIN 0x2
1307
#define AMR_AMRMIN_BIT 1
1308
#define AMR_AMRHOUR_MASK 0x4
1309
#define AMR_AMRHOUR 0x4
1310
#define AMR_AMRHOUR_BIT 2
1311
#define AMR_AMRDOM_MASK 0x8
1312
#define AMR_AMRDOM 0x8
1313
#define AMR_AMRDOM_BIT 3
1314
#define AMR_AMRDOW_MASK 0x10
1315
#define AMR_AMRDOW 0x10
1316
#define AMR_AMRDOW_BIT 4
1317
#define AMR_AMRDOY_MASK 0x20
1318
#define AMR_AMRDOY 0x20
1319
#define AMR_AMRDOY_BIT 5
1320
#define AMR_AMRMON_MASK 0x40
1321
#define AMR_AMRMON 0x40
1322
#define AMR_AMRMON_BIT 6
1323
#define AMR_AMRYEAR_MASK 0x80
1324
#define AMR_AMRYEAR 0x80
1325
#define AMR_AMRYEAR_BIT 7
1326
 
1327
#define CTIME0 (*(volatile unsigned long *)0xE0024014)
1328
#define CTIME0_OFFSET 0x14
1329
#define CTIME0_Seconds_MASK 0x3F
1330
#define CTIME0_Seconds_BIT 0
1331
#define CTIME0_Minutes_MASK 0x3F00
1332
#define CTIME0_Minutes_BIT 8
1333
#define CTIME0_Hours_MASK 0x1F0000
1334
#define CTIME0_Hours_BIT 16
1335
#define CTIME0_Day_of_Week_MASK 0x7000000
1336
#define CTIME0_Day_of_Week_BIT 24
1337
 
1338
#define CTIME1 (*(volatile unsigned long *)0xE0024018)
1339
#define CTIME1_OFFSET 0x18
1340
#define CTIME1_Day_of_Month_MASK 0x1F
1341
#define CTIME1_Day_of_Month_BIT 0
1342
#define CTIME1_Month_MASK 0xF00
1343
#define CTIME1_Month_BIT 8
1344
#define CTIME1_Year_MASK 0xFFF0000
1345
#define CTIME1_Year_BIT 16
1346
 
1347
#define CTIME2 (*(volatile unsigned long *)0xE002401C)
1348
#define CTIME2_OFFSET 0x1C
1349
#define CTIME2_Day_of_Year_MASK 0xFFF
1350
#define CTIME2_Day_of_Year_BIT 0
1351
 
1352
#define SEC (*(volatile unsigned long *)0xE0024020)
1353
#define SEC_OFFSET 0x20
1354
 
1355
#define MIN (*(volatile unsigned long *)0xE0024024)
1356
#define MIN_OFFSET 0x24
1357
 
1358
#define HOUR (*(volatile unsigned long *)0xE0024028)
1359
#define HOUR_OFFSET 0x28
1360
 
1361
#define DOM (*(volatile unsigned long *)0xE002402C)
1362
#define DOM_OFFSET 0x2C
1363
 
1364
#define DOW (*(volatile unsigned long *)0xE0024030)
1365
#define DOW_OFFSET 0x30
1366
 
1367
#define DOY (*(volatile unsigned long *)0xE0024034)
1368
#define DOY_OFFSET 0x34
1369
 
1370
#define MONTH (*(volatile unsigned long *)0xE0024038)
1371
#define MONTH_OFFSET 0x38
1372
 
1373
#define YEAR (*(volatile unsigned long *)0xE002403C)
1374
#define YEAR_OFFSET 0x3C
1375
 
1376
#define ALSEC (*(volatile unsigned long *)0xE0024060)
1377
#define ALSEC_OFFSET 0x60
1378
 
1379
#define ALMIN (*(volatile unsigned long *)0xE0024064)
1380
#define ALMIN_OFFSET 0x64
1381
 
1382
#define ALHOUR (*(volatile unsigned long *)0xE0024068)
1383
#define ALHOUR_OFFSET 0x68
1384
 
1385
#define ALDOM (*(volatile unsigned long *)0xE002406C)
1386
#define ALDOM_OFFSET 0x6C
1387
 
1388
#define ALDOW (*(volatile unsigned long *)0xE0024070)
1389
#define ALDOW_OFFSET 0x70
1390
 
1391
#define ALDOY (*(volatile unsigned long *)0xE0024074)
1392
#define ALDOY_OFFSET 0x74
1393
 
1394
#define ALMON (*(volatile unsigned long *)0xE0024078)
1395
#define ALMON_OFFSET 0x78
1396
 
1397
#define ALYEAR (*(volatile unsigned long *)0xE002407C)
1398
#define ALYEAR_OFFSET 0x7C
1399
 
1400
#define PREINT (*(volatile unsigned long *)0xE0024080)
1401
#define PREINT_OFFSET 0x80
1402
 
1403
#define PREFRAC (*(volatile unsigned long *)0xE0024084)
1404
#define PREFRAC_OFFSET 0x84
1405
 
1406
#define GPIO_BASE 0xE0028000
1407
 
1408
#define IO0PIN (*(volatile unsigned long *)0xE0028000)
1409
#define IO0PIN_OFFSET 0x0
1410
 
1411
#define IO0SET (*(volatile unsigned long *)0xE0028004)
1412
#define IO0SET_OFFSET 0x4
1413
 
1414
#define IO0DIR (*(volatile unsigned long *)0xE0028008)
1415
#define IO0DIR_OFFSET 0x8
1416
 
1417
#define IO0CLR (*(volatile unsigned long *)0xE002800C)
1418
#define IO0CLR_OFFSET 0xC
1419
 
1420
#define IO1PIN (*(volatile unsigned long *)0xE0028010)
1421
#define IO1PIN_OFFSET 0x10
1422
 
1423
#define IO1SET (*(volatile unsigned long *)0xE0028014)
1424
#define IO1SET_OFFSET 0x14
1425
 
1426
#define IO1DIR (*(volatile unsigned long *)0xE0028018)
1427
#define IO1DIR_OFFSET 0x18
1428
 
1429
#define IO1CLR (*(volatile unsigned long *)0xE002801C)
1430
#define IO1CLR_OFFSET 0x1C
1431
 
1432
#define PCB_BASE 0xE002C000
1433
 
1434
#define PINSEL0 (*(volatile unsigned long *)0xE002C000)
1435
#define PINSEL0_OFFSET 0x0
1436
#define PINSEL0_P0_0_MASK 0x3
1437
#define PINSEL0_P0_0_BIT 0
1438
#define PINSEL0_P0_1_MASK 0xC
1439
#define PINSEL0_P0_1_BIT 2
1440
#define PINSEL0_P0_2_MASK 0x30
1441
#define PINSEL0_P0_2_BIT 4
1442
#define PINSEL0_P0_3_MASK 0xC0
1443
#define PINSEL0_P0_3_BIT 6
1444
#define PINSEL0_P0_4_MASK 0x300
1445
#define PINSEL0_P0_4_BIT 8
1446
#define PINSEL0_P0_5_MASK 0xC00
1447
#define PINSEL0_P0_5_BIT 10
1448
#define PINSEL0_P0_6_MASK 0x3000
1449
#define PINSEL0_P0_6_BIT 12
1450
#define PINSEL0_P0_7_MASK 0xC000
1451
#define PINSEL0_P0_7_BIT 14
1452
#define PINSEL0_P0_8_MASK 0x30000
1453
#define PINSEL0_P0_8_BIT 16
1454
#define PINSEL0_P0_9_MASK 0xC0000
1455
#define PINSEL0_P0_9_BIT 18
1456
#define PINSEL0_P0_10_MASK 0x300000
1457
#define PINSEL0_P0_10_BIT 20
1458
#define PINSEL0_P0_11_MASK 0xC00000
1459
#define PINSEL0_P0_11_BIT 22
1460
#define PINSEL0_P0_12_MASK 0x3000000
1461
#define PINSEL0_P0_12_BIT 24
1462
#define PINSEL0_P0_13_MASK 0xC000000
1463
#define PINSEL0_P0_13_BIT 26
1464
#define PINSEL0_P0_14_MASK 0x30000000
1465
#define PINSEL0_P0_14_BIT 28
1466
#define PINSEL0_P0_15_MASK 0xC0000000
1467
#define PINSEL0_P0_15_BIT 30
1468
 
1469
#define PINSEL1 (*(volatile unsigned long *)0xE002C004)
1470
#define PINSEL1_OFFSET 0x4
1471
#define PINSEL1_P0_16_MASK 0x3
1472
#define PINSEL1_P0_16_BIT 0
1473
#define PINSEL1_P0_17_MASK 0xC
1474
#define PINSEL1_P0_17_BIT 2
1475
#define PINSEL1_P0_18_MASK 0x30
1476
#define PINSEL1_P0_18_BIT 4
1477
#define PINSEL1_P0_19_MASK 0xC0
1478
#define PINSEL1_P0_19_BIT 6
1479
#define PINSEL1_P0_20_MASK 0x300
1480
#define PINSEL1_P0_20_BIT 8
1481
#define PINSEL1_P0_21_MASK 0xC00
1482
#define PINSEL1_P0_21_BIT 10
1483
#define PINSEL1_P0_22_MASK 0x3000
1484
#define PINSEL1_P0_22_BIT 12
1485
#define PINSEL1_P0_23_MASK 0xC000
1486
#define PINSEL1_P0_23_BIT 14
1487
#define PINSEL1_P0_24_MASK 0x30000
1488
#define PINSEL1_P0_24_BIT 16
1489
#define PINSEL1_P0_25_MASK 0xC0000
1490
#define PINSEL1_P0_25_BIT 18
1491
#define PINSEL1_P0_26_MASK 0x300000
1492
#define PINSEL1_P0_26_BIT 20
1493
#define PINSEL1_P0_27_MASK 0xC00000
1494
#define PINSEL1_P0_27_BIT 22
1495
#define PINSEL1_P0_28_MASK 0x3000000
1496
#define PINSEL1_P0_28_BIT 24
1497
#define PINSEL1_P0_29_MASK 0xC000000
1498
#define PINSEL1_P0_29_BIT 26
1499
#define PINSEL1_P0_30_MASK 0x30000000
1500
#define PINSEL1_P0_30_BIT 28
1501
#define PINSEL1_P0_31_MASK 0xC0000000
1502
#define PINSEL1_P0_31_BIT 30
1503
 
1504
#define PINSEL2 (*(volatile unsigned long *)0xE002C014)
1505
#define PINSEL2_OFFSET 0x14
1506
#define PINSEL2_GPIO_DEBUG_MASK 0x4
1507
#define PINSEL2_GPIO_DEBUG 0x4
1508
#define PINSEL2_GPIO_DEBUG_BIT 2
1509
#define PINSEL2_GPIO_TRACE_MASK 0x8
1510
#define PINSEL2_GPIO_TRACE 0x8
1511
#define PINSEL2_GPIO_TRACE_BIT 3
1512
 
1513
#define SPI1_BASE 0xE0030000
1514
 
1515
#define S1SPCR (*(volatile unsigned short *)0xE0030000)
1516
#define S1SPCR_OFFSET 0x0
1517
#define S1SPCR_BitEnable_MASK 0x4
1518
#define S1SPCR_BitEnable 0x4
1519
#define S1SPCR_BitEnable_BIT 2
1520
#define S1SPCR_CPHA_MASK 0x8
1521
#define S1SPCR_CPHA 0x8
1522
#define S1SPCR_CPHA_BIT 3
1523
#define S1SPCR_CPOL_MASK 0x10
1524
#define S1SPCR_CPOL 0x10
1525
#define S1SPCR_CPOL_BIT 4
1526
#define S1SPCR_MSTR_MASK 0x20
1527
#define S1SPCR_MSTR 0x20
1528
#define S1SPCR_MSTR_BIT 5
1529
#define S1SPCR_LSBF_MASK 0x40
1530
#define S1SPCR_LSBF 0x40
1531
#define S1SPCR_LSBF_BIT 6
1532
#define S1SPCR_SPIE_MASK 0x80
1533
#define S1SPCR_SPIE 0x80
1534
#define S1SPCR_SPIE_BIT 7
1535
#define S1SPCR_BITS_MASK 0xF00
1536
#define S1SPCR_BITS_BIT 8
1537
 
1538
#define S1SPSR (*(volatile unsigned char *)0xE0030004)
1539
#define S1SPSR_OFFSET 0x4
1540
#define S1SPSR_ABRT_MASK 0x8
1541
#define S1SPSR_ABRT 0x8
1542
#define S1SPSR_ABRT_BIT 3
1543
#define S1SPSR_MODF_MASK 0x10
1544
#define S1SPSR_MODF 0x10
1545
#define S1SPSR_MODF_BIT 4
1546
#define S1SPSR_ROVR_MASK 0x20
1547
#define S1SPSR_ROVR 0x20
1548
#define S1SPSR_ROVR_BIT 5
1549
#define S1SPSR_WCOL_MASK 0x40
1550
#define S1SPSR_WCOL 0x40
1551
#define S1SPSR_WCOL_BIT 6
1552
#define S1SPSR_SPIF_MASK 0x80
1553
#define S1SPSR_SPIF 0x80
1554
#define S1SPSR_SPIF_BIT 7
1555
 
1556
#define S1SPDR (*(volatile unsigned short *)0xE0030008)
1557
#define S1SPDR_OFFSET 0x8
1558
 
1559
#define S1SPCCR (*(volatile unsigned char *)0xE003000C)
1560
#define S1SPCCR_OFFSET 0xC
1561
 
1562
#define S1SPINT (*(volatile unsigned char *)0xE003001C)
1563
#define S1SPINT_OFFSET 0x1C
1564
 
1565
#define AD_BASE 0xE0034000
1566
 
1567
#define ADCR (*(volatile unsigned *)0xE0034000)
1568
#define ADCR_OFFSET 0x0
1569
#define ADCR_SEL_MASK 0xFF
1570
#define ADCR_SEL_BIT 0
1571
#define ADCR_CLKDIV_MASK 0xFF00
1572
#define ADCR_CLKDIV_BIT 8
1573
#define ADCR_BURST_MASK 0x10000
1574
#define ADCR_BURST 0x10000
1575
#define ADCR_BURST_BIT 16
1576
#define ADCR_CLKS_MASK 0xE0000
1577
#define ADCR_CLKS_BIT 17
1578
#define ADCR_PDN_MASK 0x200000
1579
#define ADCR_PDN 0x200000
1580
#define ADCR_PDN_BIT 21
1581
#define ADCR_START_MASK 0x7000000
1582
#define ADCR_START_BIT 24
1583
#define ADCR_EDGE_MASK 0x8000000
1584
#define ADCR_EDGE 0x8000000
1585
#define ADCR_EDGE_BIT 27
1586
 
1587
#define ADGDR (*(volatile unsigned *)0xE0034004)
1588
#define ADGDR_OFFSET 0x4
1589
#define ADGDR_RESULT_MASK 0xFFC0
1590
#define ADGDR_RESULT_BIT 6
1591
#define ADGDR_CHN_MASK 0x7000000
1592
#define ADGDR_CHN_BIT 24
1593
#define ADGDR_OVERUN_MASK 0x40000000
1594
#define ADGDR_OVERUN 0x40000000
1595
#define ADGDR_OVERUN_BIT 30
1596
#define ADGDR_DONE_MASK 0x80000000
1597
#define ADGDR_DONE 0x80000000
1598
#define ADGDR_DONE_BIT 31
1599
 
1600
#define ADINTEN (*(volatile unsigned *)0xE003400C)
1601
#define ADINTEN_OFFSET 0xC
1602
#define ADINTEN_ADINTEN0_MASK 0x1
1603
#define ADINTEN_ADINTEN0 0x1
1604
#define ADINTEN_ADINTEN0_BIT 0
1605
#define ADINTEN_ADINTEN1_MASK 0x2
1606
#define ADINTEN_ADINTEN1 0x2
1607
#define ADINTEN_ADINTEN1_BIT 1
1608
#define ADINTEN_ADINTEN2_MASK 0x4
1609
#define ADINTEN_ADINTEN2 0x4
1610
#define ADINTEN_ADINTEN2_BIT 2
1611
#define ADINTEN_ADINTEN3_MASK 0x8
1612
#define ADINTEN_ADINTEN3 0x8
1613
#define ADINTEN_ADINTEN3_BIT 3
1614
#define ADINTEN_ADINTEN4_MASK 0x10
1615
#define ADINTEN_ADINTEN4 0x10
1616
#define ADINTEN_ADINTEN4_BIT 4
1617
#define ADINTEN_ADINTEN5_MASK 0x20
1618
#define ADINTEN_ADINTEN5 0x20
1619
#define ADINTEN_ADINTEN5_BIT 5
1620
#define ADINTEN_ADINTEN6_MASK 0x40
1621
#define ADINTEN_ADINTEN6 0x40
1622
#define ADINTEN_ADINTEN6_BIT 6
1623
#define ADINTEN_ADINTEN7_MASK 0x80
1624
#define ADINTEN_ADINTEN7 0x80
1625
#define ADINTEN_ADINTEN7_BIT 7
1626
#define ADINTEN_ADGINTEN_MASK 0x100
1627
#define ADINTEN_ADGINTEN 0x100
1628
#define ADINTEN_ADGINTEN_BIT 8
1629
 
1630
#define ADDR0 (*(volatile unsigned *)0xE0034010)
1631
#define ADDR0_OFFSET 0x10
1632
#define ADDR0_RESULT_MASK 0xFFC0
1633
#define ADDR0_RESULT_BIT 6
1634
#define ADDR0_OVERRUN_MASK 0x40000000
1635
#define ADDR0_OVERRUN 0x40000000
1636
#define ADDR0_OVERRUN_BIT 30
1637
#define ADDR0_DONE_MASK 0x80000000
1638
#define ADDR0_DONE 0x80000000
1639
#define ADDR0_DONE_BIT 31
1640
 
1641
#define ADDR1 (*(volatile unsigned *)0xE0034014)
1642
#define ADDR1_OFFSET 0x14
1643
#define ADDR1_RESULT_MASK 0xFFC0
1644
#define ADDR1_RESULT_BIT 6
1645
#define ADDR1_OVERRUN_MASK 0x40000000
1646
#define ADDR1_OVERRUN 0x40000000
1647
#define ADDR1_OVERRUN_BIT 30
1648
#define ADDR1_DONE_MASK 0x80000000
1649
#define ADDR1_DONE 0x80000000
1650
#define ADDR1_DONE_BIT 31
1651
 
1652
#define ADDR2 (*(volatile unsigned *)0xE0034018)
1653
#define ADDR2_OFFSET 0x18
1654
#define ADDR2_RESULT_MASK 0xFFC0
1655
#define ADDR2_RESULT_BIT 6
1656
#define ADDR2_OVERRUN_MASK 0x40000000
1657
#define ADDR2_OVERRUN 0x40000000
1658
#define ADDR2_OVERRUN_BIT 30
1659
#define ADDR2_DONE_MASK 0x80000000
1660
#define ADDR2_DONE 0x80000000
1661
#define ADDR2_DONE_BIT 31
1662
 
1663
#define ADDR3 (*(volatile unsigned *)0xE003401C)
1664
#define ADDR3_OFFSET 0x1C
1665
#define ADDR3_RESULT_MASK 0xFFC0
1666
#define ADDR3_RESULT_BIT 6
1667
#define ADDR3_OVERRUN_MASK 0x40000000
1668
#define ADDR3_OVERRUN 0x40000000
1669
#define ADDR3_OVERRUN_BIT 30
1670
#define ADDR3_DONE_MASK 0x80000000
1671
#define ADDR3_DONE 0x80000000
1672
#define ADDR3_DONE_BIT 31
1673
 
1674
#define ADDR4 (*(volatile unsigned *)0xE0034020)
1675
#define ADDR4_OFFSET 0x20
1676
#define ADDR4_RESULT_MASK 0xFFC0
1677
#define ADDR4_RESULT_BIT 6
1678
#define ADDR4_OVERRUN_MASK 0x40000000
1679
#define ADDR4_OVERRUN 0x40000000
1680
#define ADDR4_OVERRUN_BIT 30
1681
#define ADDR4_DONE_MASK 0x80000000
1682
#define ADDR4_DONE 0x80000000
1683
#define ADDR4_DONE_BIT 31
1684
 
1685
#define ADDR5 (*(volatile unsigned *)0xE0034024)
1686
#define ADDR5_OFFSET 0x24
1687
#define ADDR5_RESULT_MASK 0xFFC0
1688
#define ADDR5_RESULT_BIT 6
1689
#define ADDR5_OVERRUN_MASK 0x40000000
1690
#define ADDR5_OVERRUN 0x40000000
1691
#define ADDR5_OVERRUN_BIT 30
1692
#define ADDR5_DONE_MASK 0x80000000
1693
#define ADDR5_DONE 0x80000000
1694
#define ADDR5_DONE_BIT 31
1695
 
1696
#define ADDR6 (*(volatile unsigned *)0xE0034028)
1697
#define ADDR6_OFFSET 0x28
1698
#define ADDR6_RESULT_MASK 0xFFC0
1699
#define ADDR6_RESULT_BIT 6
1700
#define ADDR6_OVERRUN_MASK 0x40000000
1701
#define ADDR6_OVERRUN 0x40000000
1702
#define ADDR6_OVERRUN_BIT 30
1703
#define ADDR6_DONE_MASK 0x80000000
1704
#define ADDR6_DONE 0x80000000
1705
#define ADDR6_DONE_BIT 31
1706
 
1707
#define ADDR7 (*(volatile unsigned *)0xE003402C)
1708
#define ADDR7_OFFSET 0x2C
1709
#define ADDR7_RESULT_MASK 0xFFC0
1710
#define ADDR7_RESULT_BIT 6
1711
#define ADDR7_OVERRUN_MASK 0x40000000
1712
#define ADDR7_OVERRUN 0x40000000
1713
#define ADDR7_OVERRUN_BIT 30
1714
#define ADDR7_DONE_MASK 0x80000000
1715
#define ADDR7_DONE 0x80000000
1716
#define ADDR7_DONE_BIT 31
1717
 
1718
#define ADSTAT (*(volatile unsigned *)0xE0034030)
1719
#define ADSTAT_OFFSET 0x30
1720
#define ADSTAT_DONE0_MASK 0x1
1721
#define ADSTAT_DONE0 0x1
1722
#define ADSTAT_DONE0_BIT 0
1723
#define ADSTAT_DONE1_MASK 0x2
1724
#define ADSTAT_DONE1 0x2
1725
#define ADSTAT_DONE1_BIT 1
1726
#define ADSTAT_DONE2_MASK 0x4
1727
#define ADSTAT_DONE2 0x4
1728
#define ADSTAT_DONE2_BIT 2
1729
#define ADSTAT_DONE3_MASK 0x8
1730
#define ADSTAT_DONE3 0x8
1731
#define ADSTAT_DONE3_BIT 3
1732
#define ADSTAT_DONE4_MASK 0x10
1733
#define ADSTAT_DONE4 0x10
1734
#define ADSTAT_DONE4_BIT 4
1735
#define ADSTAT_DONE5_MASK 0x20
1736
#define ADSTAT_DONE5 0x20
1737
#define ADSTAT_DONE5_BIT 5
1738
#define ADSTAT_DONE6_MASK 0x40
1739
#define ADSTAT_DONE6 0x40
1740
#define ADSTAT_DONE6_BIT 6
1741
#define ADSTAT_DONE7_MASK 0x80
1742
#define ADSTAT_DONE7 0x80
1743
#define ADSTAT_DONE7_BIT 7
1744
#define ADSTAT_OVERRUN0_MASK 0x100
1745
#define ADSTAT_OVERRUN0 0x100
1746
#define ADSTAT_OVERRUN0_BIT 8
1747
#define ADSTAT_OVERRUN1_MASK 0x200
1748
#define ADSTAT_OVERRUN1 0x200
1749
#define ADSTAT_OVERRUN1_BIT 9
1750
#define ADSTAT_OVERRUN2_MASK 0x400
1751
#define ADSTAT_OVERRUN2 0x400
1752
#define ADSTAT_OVERRUN2_BIT 10
1753
#define ADSTAT_OVERRUN3_MASK 0x800
1754
#define ADSTAT_OVERRUN3 0x800
1755
#define ADSTAT_OVERRUN3_BIT 11
1756
#define ADSTAT_OVERRUN4_MASK 0x1000
1757
#define ADSTAT_OVERRUN4 0x1000
1758
#define ADSTAT_OVERRUN4_BIT 12
1759
#define ADSTAT_OVERRUN5_MASK 0x2000
1760
#define ADSTAT_OVERRUN5 0x2000
1761
#define ADSTAT_OVERRUN5_BIT 13
1762
#define ADSTAT_OVERRUN6_MASK 0x4000
1763
#define ADSTAT_OVERRUN6 0x4000
1764
#define ADSTAT_OVERRUN6_BIT 14
1765
#define ADSTAT_OVERRUN7_MASK 0x8000
1766
#define ADSTAT_OVERRUN7 0x8000
1767
#define ADSTAT_OVERRUN7_BIT 15
1768
#define ADSTAT_ADINT_MASK 0x10000
1769
#define ADSTAT_ADINT 0x10000
1770
#define ADSTAT_ADINT_BIT 16
1771
 
1772
#define CAN_BASE 0xE0038000
1773
 
1774
#define AFMR (*(volatile unsigned long *)0xE003C000)
1775
#define AFMR_OFFSET 0x4000
1776
#define AFMR_AccOff_MASK 0x1
1777
#define AFMR_AccOff 0x1
1778
#define AFMR_AccOff_BIT 0
1779
#define AFMR_AccBP_MASK 0x2
1780
#define AFMR_AccBP 0x2
1781
#define AFMR_AccBP_BIT 1
1782
#define AFMR_eFCAN_MASK 0x4
1783
#define AFMR_eFCAN 0x4
1784
#define AFMR_eFCAN_BIT 2
1785
 
1786
#define SFF_sa (*(volatile unsigned long *)0xE003C004)
1787
#define SFF_sa_OFFSET 0x4004
1788
 
1789
#define SFF_GRP_sa (*(volatile unsigned long *)0xE003C008)
1790
#define SFF_GRP_sa_OFFSET 0x4008
1791
 
1792
#define EFF_sa (*(volatile unsigned long *)0xE003C00C)
1793
#define EFF_sa_OFFSET 0x400C
1794
 
1795
#define EFF_GRP_sa (*(volatile unsigned long *)0xE003C010)
1796
#define EFF_GRP_sa_OFFSET 0x4010
1797
 
1798
#define ENDofTable (*(volatile unsigned long *)0xE003C014)
1799
#define ENDofTable_OFFSET 0x4014
1800
 
1801
#define LUTerrAd (*(volatile unsigned long *)0xE003C018)
1802
#define LUTerrAd_OFFSET 0x4018
1803
 
1804
#define LUTerr (*(volatile unsigned long *)0xE003C01C)
1805
#define LUTerr_OFFSET 0x401C
1806
 
1807
#define CANTxSR (*(volatile unsigned long *)0xE0040000)
1808
#define CANTxSR_OFFSET 0x8000
1809
#define CANTxSR_TS1_MASK 0x1
1810
#define CANTxSR_TS1 0x1
1811
#define CANTxSR_TS1_BIT 0
1812
#define CANTxSR_TS2_MASK 0x2
1813
#define CANTxSR_TS2 0x2
1814
#define CANTxSR_TS2_BIT 1
1815
#define CANTxSR_TS3_MASK 0x4
1816
#define CANTxSR_TS3 0x4
1817
#define CANTxSR_TS3_BIT 2
1818
#define CANTxSR_TS4_MASK 0x8
1819
#define CANTxSR_TS4 0x8
1820
#define CANTxSR_TS4_BIT 3
1821
#define CANTxSR_TBS1_MASK 0x100
1822
#define CANTxSR_TBS1 0x100
1823
#define CANTxSR_TBS1_BIT 8
1824
#define CANTxSR_TBS2_MASK 0x200
1825
#define CANTxSR_TBS2 0x200
1826
#define CANTxSR_TBS2_BIT 9
1827
#define CANTxSR_TBS3_MASK 0x400
1828
#define CANTxSR_TBS3 0x400
1829
#define CANTxSR_TBS3_BIT 10
1830
#define CANTxSR_TBS4_MASK 0x800
1831
#define CANTxSR_TBS4 0x800
1832
#define CANTxSR_TBS4_BIT 11
1833
#define CANTxSR_TCS1_MASK 0x10000
1834
#define CANTxSR_TCS1 0x10000
1835
#define CANTxSR_TCS1_BIT 16
1836
#define CANTxSR_TCS2_MASK 0x20000
1837
#define CANTxSR_TCS2 0x20000
1838
#define CANTxSR_TCS2_BIT 17
1839
#define CANTxSR_TCS3_MASK 0x40000
1840
#define CANTxSR_TCS3 0x40000
1841
#define CANTxSR_TCS3_BIT 18
1842
#define CANTxSR_TCS4_MASK 0x80000
1843
#define CANTxSR_TCS4 0x80000
1844
#define CANTxSR_TCS4_BIT 19
1845
 
1846
#define CANRxSR (*(volatile unsigned long *)0xE0040004)
1847
#define CANRxSR_OFFSET 0x8004
1848
#define CANRxSR_RS1_MASK 0x1
1849
#define CANRxSR_RS1 0x1
1850
#define CANRxSR_RS1_BIT 0
1851
#define CANRxSR_RS2_MASK 0x2
1852
#define CANRxSR_RS2 0x2
1853
#define CANRxSR_RS2_BIT 1
1854
#define CANRxSR_RS3_MASK 0x4
1855
#define CANRxSR_RS3 0x4
1856
#define CANRxSR_RS3_BIT 2
1857
#define CANRxSR_RS4_MASK 0x8
1858
#define CANRxSR_RS4 0x8
1859
#define CANRxSR_RS4_BIT 3
1860
#define CANRxSR_RB1_MASK 0x100
1861
#define CANRxSR_RB1 0x100
1862
#define CANRxSR_RB1_BIT 8
1863
#define CANRxSR_RB2_MASK 0x200
1864
#define CANRxSR_RB2 0x200
1865
#define CANRxSR_RB2_BIT 9
1866
#define CANRxSR_RB3_MASK 0x400
1867
#define CANRxSR_RB3 0x400
1868
#define CANRxSR_RB3_BIT 10
1869
#define CANRxSR_RB4_MASK 0x800
1870
#define CANRxSR_RB4 0x800
1871
#define CANRxSR_RB4_BIT 11
1872
#define CANRxSR_DOS1_MASK 0x10000
1873
#define CANRxSR_DOS1 0x10000
1874
#define CANRxSR_DOS1_BIT 16
1875
#define CANRxSR_DOS2_MASK 0x20000
1876
#define CANRxSR_DOS2 0x20000
1877
#define CANRxSR_DOS2_BIT 17
1878
#define CANRxSR_DOS3_MASK 0x40000
1879
#define CANRxSR_DOS3 0x40000
1880
#define CANRxSR_DOS3_BIT 18
1881
#define CANRxSR_DOS4_MASK 0x80000
1882
#define CANRxSR_DOS4 0x80000
1883
#define CANRxSR_DOS4_BIT 19
1884
 
1885
#define CANMSR (*(volatile unsigned long *)0xE0040008)
1886
#define CANMSR_OFFSET 0x8008
1887
#define CANMSR_ES1_MASK 0x1
1888
#define CANMSR_ES1 0x1
1889
#define CANMSR_ES1_BIT 0
1890
#define CANMSR_ES2_MASK 0x2
1891
#define CANMSR_ES2 0x2
1892
#define CANMSR_ES2_BIT 1
1893
#define CANMSR_ES3_MASK 0x4
1894
#define CANMSR_ES3 0x4
1895
#define CANMSR_ES3_BIT 2
1896
#define CANMSR_ES4_MASK 0x8
1897
#define CANMSR_ES4 0x8
1898
#define CANMSR_ES4_BIT 3
1899
#define CANMSR_BS1_MASK 0x100
1900
#define CANMSR_BS1 0x100
1901
#define CANMSR_BS1_BIT 8
1902
#define CANMSR_BS2_MASK 0x200
1903
#define CANMSR_BS2 0x200
1904
#define CANMSR_BS2_BIT 9
1905
#define CANMSR_BS3_MASK 0x400
1906
#define CANMSR_BS3 0x400
1907
#define CANMSR_BS3_BIT 10
1908
#define CANMSR_BS4_MASK 0x800
1909
#define CANMSR_BS4 0x800
1910
#define CANMSR_BS4_BIT 11
1911
 
1912
#define CAN1_BASE 0xE0044000
1913
 
1914
#define C1MOD (*(volatile unsigned long *)0xE0044000)
1915
#define CAN1MOD C1MOD
1916
#define C1MOD_OFFSET 0x0
1917
#define CAN1MOD_OFFSET C1MOD_OFFSET
1918
#define C1MOD_RM_MASK 0x1
1919
#define CAN1MOD_RM_MASK C1MOD_RM_MASK
1920
#define C1MOD_RM 0x1
1921
#define CAN1MOD_RM C1MOD_RM
1922
#define C1MOD_RM_BIT 0
1923
#define CAN1MOD_RM_BIT C1MOD_RM_BIT
1924
#define C1MOD_LOM_MASK 0x2
1925
#define CAN1MOD_LOM_MASK C1MOD_LOM_MASK
1926
#define C1MOD_LOM 0x2
1927
#define CAN1MOD_LOM C1MOD_LOM
1928
#define C1MOD_LOM_BIT 1
1929
#define CAN1MOD_LOM_BIT C1MOD_LOM_BIT
1930
#define C1MOD_STM_MASK 0x4
1931
#define CAN1MOD_STM_MASK C1MOD_STM_MASK
1932
#define C1MOD_STM 0x4
1933
#define CAN1MOD_STM C1MOD_STM
1934
#define C1MOD_STM_BIT 2
1935
#define CAN1MOD_STM_BIT C1MOD_STM_BIT
1936
#define C1MOD_TPM_MASK 0x8
1937
#define CAN1MOD_TPM_MASK C1MOD_TPM_MASK
1938
#define C1MOD_TPM 0x8
1939
#define CAN1MOD_TPM C1MOD_TPM
1940
#define C1MOD_TPM_BIT 3
1941
#define CAN1MOD_TPM_BIT C1MOD_TPM_BIT
1942
#define C1MOD_SM_MASK 0x10
1943
#define CAN1MOD_SM_MASK C1MOD_SM_MASK
1944
#define C1MOD_SM 0x10
1945
#define CAN1MOD_SM C1MOD_SM
1946
#define C1MOD_SM_BIT 4
1947
#define CAN1MOD_SM_BIT C1MOD_SM_BIT
1948
#define C1MOD_RPM_MASK 0x20
1949
#define CAN1MOD_RPM_MASK C1MOD_RPM_MASK
1950
#define C1MOD_RPM 0x20
1951
#define CAN1MOD_RPM C1MOD_RPM
1952
#define C1MOD_RPM_BIT 5
1953
#define CAN1MOD_RPM_BIT C1MOD_RPM_BIT
1954
#define C1MOD_TM_MASK 0x80
1955
#define CAN1MOD_TM_MASK C1MOD_TM_MASK
1956
#define C1MOD_TM 0x80
1957
#define CAN1MOD_TM C1MOD_TM
1958
#define C1MOD_TM_BIT 7
1959
#define CAN1MOD_TM_BIT C1MOD_TM_BIT
1960
 
1961
#define C1CMR (*(volatile unsigned long *)0xE0044004)
1962
#define CAN1CMR C1CMR
1963
#define C1CMR_OFFSET 0x4
1964
#define CAN1CMR_OFFSET C1CMR_OFFSET
1965
#define C1CMR_TR_MASK 0x1
1966
#define CAN1CMR_TR_MASK C1CMR_TR_MASK
1967
#define C1CMR_TR 0x1
1968
#define CAN1CMR_TR C1CMR_TR
1969
#define C1CMR_TR_BIT 0
1970
#define CAN1CMR_TR_BIT C1CMR_TR_BIT
1971
#define C1CMR_AT_MASK 0x2
1972
#define CAN1CMR_AT_MASK C1CMR_AT_MASK
1973
#define C1CMR_AT 0x2
1974
#define CAN1CMR_AT C1CMR_AT
1975
#define C1CMR_AT_BIT 1
1976
#define CAN1CMR_AT_BIT C1CMR_AT_BIT
1977
#define C1CMR_RRB_MASK 0x4
1978
#define CAN1CMR_RRB_MASK C1CMR_RRB_MASK
1979
#define C1CMR_RRB 0x4
1980
#define CAN1CMR_RRB C1CMR_RRB
1981
#define C1CMR_RRB_BIT 2
1982
#define CAN1CMR_RRB_BIT C1CMR_RRB_BIT
1983
#define C1CMR_CDO_MASK 0x8
1984
#define CAN1CMR_CDO_MASK C1CMR_CDO_MASK
1985
#define C1CMR_CDO 0x8
1986
#define CAN1CMR_CDO C1CMR_CDO
1987
#define C1CMR_CDO_BIT 3
1988
#define CAN1CMR_CDO_BIT C1CMR_CDO_BIT
1989
#define C1CMR_SRR_MASK 0x10
1990
#define CAN1CMR_SRR_MASK C1CMR_SRR_MASK
1991
#define C1CMR_SRR 0x10
1992
#define CAN1CMR_SRR C1CMR_SRR
1993
#define C1CMR_SRR_BIT 4
1994
#define CAN1CMR_SRR_BIT C1CMR_SRR_BIT
1995
#define C1CMR_STB1_MASK 0x20
1996
#define CAN1CMR_STB1_MASK C1CMR_STB1_MASK
1997
#define C1CMR_STB1 0x20
1998
#define CAN1CMR_STB1 C1CMR_STB1
1999
#define C1CMR_STB1_BIT 5
2000
#define CAN1CMR_STB1_BIT C1CMR_STB1_BIT
2001
#define C1CMR_STB2_MASK 0x40
2002
#define CAN1CMR_STB2_MASK C1CMR_STB2_MASK
2003
#define C1CMR_STB2 0x40
2004
#define CAN1CMR_STB2 C1CMR_STB2
2005
#define C1CMR_STB2_BIT 6
2006
#define CAN1CMR_STB2_BIT C1CMR_STB2_BIT
2007
#define C1CMR_STB3_MASK 0x80
2008
#define CAN1CMR_STB3_MASK C1CMR_STB3_MASK
2009
#define C1CMR_STB3 0x80
2010
#define CAN1CMR_STB3 C1CMR_STB3
2011
#define C1CMR_STB3_BIT 7
2012
#define CAN1CMR_STB3_BIT C1CMR_STB3_BIT
2013
 
2014
#define C1GSR (*(volatile unsigned long *)0xE0044008)
2015
#define CAN1GSR C1GSR
2016
#define C1GSR_OFFSET 0x8
2017
#define CAN1GSR_OFFSET C1GSR_OFFSET
2018
#define C1GSR_RBS_MASK 0x1
2019
#define CAN1GSR_RBS_MASK C1GSR_RBS_MASK
2020
#define C1GSR_RBS 0x1
2021
#define CAN1GSR_RBS C1GSR_RBS
2022
#define C1GSR_RBS_BIT 0
2023
#define CAN1GSR_RBS_BIT C1GSR_RBS_BIT
2024
#define C1GSR_DOS_MASK 0x2
2025
#define CAN1GSR_DOS_MASK C1GSR_DOS_MASK
2026
#define C1GSR_DOS 0x2
2027
#define CAN1GSR_DOS C1GSR_DOS
2028
#define C1GSR_DOS_BIT 1
2029
#define CAN1GSR_DOS_BIT C1GSR_DOS_BIT
2030
#define C1GSR_TBS_MASK 0x4
2031
#define CAN1GSR_TBS_MASK C1GSR_TBS_MASK
2032
#define C1GSR_TBS 0x4
2033
#define CAN1GSR_TBS C1GSR_TBS
2034
#define C1GSR_TBS_BIT 2
2035
#define CAN1GSR_TBS_BIT C1GSR_TBS_BIT
2036
#define C1GSR_TCS_MASK 0x8
2037
#define CAN1GSR_TCS_MASK C1GSR_TCS_MASK
2038
#define C1GSR_TCS 0x8
2039
#define CAN1GSR_TCS C1GSR_TCS
2040
#define C1GSR_TCS_BIT 3
2041
#define CAN1GSR_TCS_BIT C1GSR_TCS_BIT
2042
#define C1GSR_RS_MASK 0x10
2043
#define CAN1GSR_RS_MASK C1GSR_RS_MASK
2044
#define C1GSR_RS 0x10
2045
#define CAN1GSR_RS C1GSR_RS
2046
#define C1GSR_RS_BIT 4
2047
#define CAN1GSR_RS_BIT C1GSR_RS_BIT
2048
#define C1GSR_TS_MASK 0x20
2049
#define CAN1GSR_TS_MASK C1GSR_TS_MASK
2050
#define C1GSR_TS 0x20
2051
#define CAN1GSR_TS C1GSR_TS
2052
#define C1GSR_TS_BIT 5
2053
#define CAN1GSR_TS_BIT C1GSR_TS_BIT
2054
#define C1GSR_ES_MASK 0x40
2055
#define CAN1GSR_ES_MASK C1GSR_ES_MASK
2056
#define C1GSR_ES 0x40
2057
#define CAN1GSR_ES C1GSR_ES
2058
#define C1GSR_ES_BIT 6
2059
#define CAN1GSR_ES_BIT C1GSR_ES_BIT
2060
#define C1GSR_BS_MASK 0x80
2061
#define CAN1GSR_BS_MASK C1GSR_BS_MASK
2062
#define C1GSR_BS 0x80
2063
#define CAN1GSR_BS C1GSR_BS
2064
#define C1GSR_BS_BIT 7
2065
#define CAN1GSR_BS_BIT C1GSR_BS_BIT
2066
#define C1GSR_RXERR_MASK 0xFF0000
2067
#define CAN1GSR_RXERR_MASK C1GSR_RXERR_MASK
2068
#define C1GSR_RXERR_BIT 16
2069
#define CAN1GSR_RXERR_BIT C1GSR_RXERR_BIT
2070
#define C1GSR_TXERR_MASK 0xFF000000
2071
#define CAN1GSR_TXERR_MASK C1GSR_TXERR_MASK
2072
#define C1GSR_TXERR_BIT 24
2073
#define CAN1GSR_TXERR_BIT C1GSR_TXERR_BIT
2074
 
2075
#define C1ICR (*(volatile unsigned long *)0xE004400C)
2076
#define CAN1ICR C1ICR
2077
#define C1ICR_OFFSET 0xC
2078
#define CAN1ICR_OFFSET C1ICR_OFFSET
2079
#define C1ICR_RI_MASK 0x1
2080
#define CAN1ICR_RI_MASK C1ICR_RI_MASK
2081
#define C1ICR_RI 0x1
2082
#define CAN1ICR_RI C1ICR_RI
2083
#define C1ICR_RI_BIT 0
2084
#define CAN1ICR_RI_BIT C1ICR_RI_BIT
2085
#define C1ICR_TI1_MASK 0x2
2086
#define CAN1ICR_TI1_MASK C1ICR_TI1_MASK
2087
#define C1ICR_TI1 0x2
2088
#define CAN1ICR_TI1 C1ICR_TI1
2089
#define C1ICR_TI1_BIT 1
2090
#define CAN1ICR_TI1_BIT C1ICR_TI1_BIT
2091
#define C1ICR_EI_MASK 0x4
2092
#define CAN1ICR_EI_MASK C1ICR_EI_MASK
2093
#define C1ICR_EI 0x4
2094
#define CAN1ICR_EI C1ICR_EI
2095
#define C1ICR_EI_BIT 2
2096
#define CAN1ICR_EI_BIT C1ICR_EI_BIT
2097
#define C1ICR_DOI_MASK 0x8
2098
#define CAN1ICR_DOI_MASK C1ICR_DOI_MASK
2099
#define C1ICR_DOI 0x8
2100
#define CAN1ICR_DOI C1ICR_DOI
2101
#define C1ICR_DOI_BIT 3
2102
#define CAN1ICR_DOI_BIT C1ICR_DOI_BIT
2103
#define C1ICR_WUI_MASK 0x10
2104
#define CAN1ICR_WUI_MASK C1ICR_WUI_MASK
2105
#define C1ICR_WUI 0x10
2106
#define CAN1ICR_WUI C1ICR_WUI
2107
#define C1ICR_WUI_BIT 4
2108
#define CAN1ICR_WUI_BIT C1ICR_WUI_BIT
2109
#define C1ICR_EPI_MASK 0x20
2110
#define CAN1ICR_EPI_MASK C1ICR_EPI_MASK
2111
#define C1ICR_EPI 0x20
2112
#define CAN1ICR_EPI C1ICR_EPI
2113
#define C1ICR_EPI_BIT 5
2114
#define CAN1ICR_EPI_BIT C1ICR_EPI_BIT
2115
#define C1ICR_ALI_MASK 0x40
2116
#define CAN1ICR_ALI_MASK C1ICR_ALI_MASK
2117
#define C1ICR_ALI 0x40
2118
#define CAN1ICR_ALI C1ICR_ALI
2119
#define C1ICR_ALI_BIT 6
2120
#define CAN1ICR_ALI_BIT C1ICR_ALI_BIT
2121
#define C1ICR_BEI_MASK 0x80
2122
#define CAN1ICR_BEI_MASK C1ICR_BEI_MASK
2123
#define C1ICR_BEI 0x80
2124
#define CAN1ICR_BEI C1ICR_BEI
2125
#define C1ICR_BEI_BIT 7
2126
#define CAN1ICR_BEI_BIT C1ICR_BEI_BIT
2127
#define C1ICR_IDI_MASK 0x100
2128
#define CAN1ICR_IDI_MASK C1ICR_IDI_MASK
2129
#define C1ICR_IDI 0x100
2130
#define CAN1ICR_IDI C1ICR_IDI
2131
#define C1ICR_IDI_BIT 8
2132
#define CAN1ICR_IDI_BIT C1ICR_IDI_BIT
2133
#define C1ICR_TI2_MASK 0x200
2134
#define CAN1ICR_TI2_MASK C1ICR_TI2_MASK
2135
#define C1ICR_TI2 0x200
2136
#define CAN1ICR_TI2 C1ICR_TI2
2137
#define C1ICR_TI2_BIT 9
2138
#define CAN1ICR_TI2_BIT C1ICR_TI2_BIT
2139
#define C1ICR_TI3_MASK 0x400
2140
#define CAN1ICR_TI3_MASK C1ICR_TI3_MASK
2141
#define C1ICR_TI3 0x400
2142
#define CAN1ICR_TI3 C1ICR_TI3
2143
#define C1ICR_TI3_BIT 10
2144
#define CAN1ICR_TI3_BIT C1ICR_TI3_BIT
2145
#define C1ICR_ERRBIT_MASK 0x1F0000
2146
#define CAN1ICR_ERRBIT_MASK C1ICR_ERRBIT_MASK
2147
#define C1ICR_ERRBIT_BIT 16
2148
#define CAN1ICR_ERRBIT_BIT C1ICR_ERRBIT_BIT
2149
#define C1ICR_ERRDIR_MASK 0x200000
2150
#define CAN1ICR_ERRDIR_MASK C1ICR_ERRDIR_MASK
2151
#define C1ICR_ERRDIR 0x200000
2152
#define CAN1ICR_ERRDIR C1ICR_ERRDIR
2153
#define C1ICR_ERRDIR_BIT 21
2154
#define CAN1ICR_ERRDIR_BIT C1ICR_ERRDIR_BIT
2155
#define C1ICR_ERRC_MASK 0xC00000
2156
#define CAN1ICR_ERRC_MASK C1ICR_ERRC_MASK
2157
#define C1ICR_ERRC_BIT 22
2158
#define CAN1ICR_ERRC_BIT C1ICR_ERRC_BIT
2159
#define C1ICR_ALCBIT_MASK 0x1F000000
2160
#define CAN1ICR_ALCBIT_MASK C1ICR_ALCBIT_MASK
2161
#define C1ICR_ALCBIT_BIT 24
2162
#define CAN1ICR_ALCBIT_BIT C1ICR_ALCBIT_BIT
2163
 
2164
#define C1IER (*(volatile unsigned long *)0xE0044010)
2165
#define CAN1IER C1IER
2166
#define C1IER_OFFSET 0x10
2167
#define CAN1IER_OFFSET C1IER_OFFSET
2168
#define C1IER_RIE_MASK 0x1
2169
#define CAN1IER_RIE_MASK C1IER_RIE_MASK
2170
#define C1IER_RIE 0x1
2171
#define CAN1IER_RIE C1IER_RIE
2172
#define C1IER_RIE_BIT 0
2173
#define CAN1IER_RIE_BIT C1IER_RIE_BIT
2174
#define C1IER_TIE1_MASK 0x2
2175
#define CAN1IER_TIE1_MASK C1IER_TIE1_MASK
2176
#define C1IER_TIE1 0x2
2177
#define CAN1IER_TIE1 C1IER_TIE1
2178
#define C1IER_TIE1_BIT 1
2179
#define CAN1IER_TIE1_BIT C1IER_TIE1_BIT
2180
#define C1IER_EIE_MASK 0x4
2181
#define CAN1IER_EIE_MASK C1IER_EIE_MASK
2182
#define C1IER_EIE 0x4
2183
#define CAN1IER_EIE C1IER_EIE
2184
#define C1IER_EIE_BIT 2
2185
#define CAN1IER_EIE_BIT C1IER_EIE_BIT
2186
#define C1IER_DOIE_MASK 0x8
2187
#define CAN1IER_DOIE_MASK C1IER_DOIE_MASK
2188
#define C1IER_DOIE 0x8
2189
#define CAN1IER_DOIE C1IER_DOIE
2190
#define C1IER_DOIE_BIT 3
2191
#define CAN1IER_DOIE_BIT C1IER_DOIE_BIT
2192
#define C1IER_WUIE_MASK 0x10
2193
#define CAN1IER_WUIE_MASK C1IER_WUIE_MASK
2194
#define C1IER_WUIE 0x10
2195
#define CAN1IER_WUIE C1IER_WUIE
2196
#define C1IER_WUIE_BIT 4
2197
#define CAN1IER_WUIE_BIT C1IER_WUIE_BIT
2198
#define C1IER_EPIE_MASK 0x20
2199
#define CAN1IER_EPIE_MASK C1IER_EPIE_MASK
2200
#define C1IER_EPIE 0x20
2201
#define CAN1IER_EPIE C1IER_EPIE
2202
#define C1IER_EPIE_BIT 5
2203
#define CAN1IER_EPIE_BIT C1IER_EPIE_BIT
2204
#define C1IER_ALIE_MASK 0x40
2205
#define CAN1IER_ALIE_MASK C1IER_ALIE_MASK
2206
#define C1IER_ALIE 0x40
2207
#define CAN1IER_ALIE C1IER_ALIE
2208
#define C1IER_ALIE_BIT 6
2209
#define CAN1IER_ALIE_BIT C1IER_ALIE_BIT
2210
#define C1IER_BEIE_MASK 0x80
2211
#define CAN1IER_BEIE_MASK C1IER_BEIE_MASK
2212
#define C1IER_BEIE 0x80
2213
#define CAN1IER_BEIE C1IER_BEIE
2214
#define C1IER_BEIE_BIT 7
2215
#define CAN1IER_BEIE_BIT C1IER_BEIE_BIT
2216
#define C1IER_IDIE_MASK 0x100
2217
#define CAN1IER_IDIE_MASK C1IER_IDIE_MASK
2218
#define C1IER_IDIE 0x100
2219
#define CAN1IER_IDIE C1IER_IDIE
2220
#define C1IER_IDIE_BIT 8
2221
#define CAN1IER_IDIE_BIT C1IER_IDIE_BIT
2222
#define C1IER_TIE2_MASK 0x200
2223
#define CAN1IER_TIE2_MASK C1IER_TIE2_MASK
2224
#define C1IER_TIE2 0x200
2225
#define CAN1IER_TIE2 C1IER_TIE2
2226
#define C1IER_TIE2_BIT 9
2227
#define CAN1IER_TIE2_BIT C1IER_TIE2_BIT
2228
#define C1IER_TIE3_MASK 0x400
2229
#define CAN1IER_TIE3_MASK C1IER_TIE3_MASK
2230
#define C1IER_TIE3 0x400
2231
#define CAN1IER_TIE3 C1IER_TIE3
2232
#define C1IER_TIE3_BIT 10
2233
#define CAN1IER_TIE3_BIT C1IER_TIE3_BIT
2234
 
2235
#define C1BTR (*(volatile unsigned long *)0xE0044014)
2236
#define CAN1BTR C1BTR
2237
#define C1BTR_OFFSET 0x14
2238
#define CAN1BTR_OFFSET C1BTR_OFFSET
2239
#define C1BTR_BRP_MASK 0x3FF
2240
#define CAN1BTR_BRP_MASK C1BTR_BRP_MASK
2241
#define C1BTR_BRP_BIT 0
2242
#define CAN1BTR_BRP_BIT C1BTR_BRP_BIT
2243
#define C1BTR_SJW_MASK 0xC000
2244
#define CAN1BTR_SJW_MASK C1BTR_SJW_MASK
2245
#define C1BTR_SJW_BIT 14
2246
#define CAN1BTR_SJW_BIT C1BTR_SJW_BIT
2247
#define C1BTR_TSEG1_MASK 0xF0000
2248
#define CAN1BTR_TSEG1_MASK C1BTR_TSEG1_MASK
2249
#define C1BTR_TSEG1_BIT 16
2250
#define CAN1BTR_TSEG1_BIT C1BTR_TSEG1_BIT
2251
#define C1BTR_TSEG2_MASK 0x700000
2252
#define CAN1BTR_TSEG2_MASK C1BTR_TSEG2_MASK
2253
#define C1BTR_TSEG2_BIT 20
2254
#define CAN1BTR_TSEG2_BIT C1BTR_TSEG2_BIT
2255
#define C1BTR_SAM_MASK 0x800000
2256
#define CAN1BTR_SAM_MASK C1BTR_SAM_MASK
2257
#define C1BTR_SAM 0x800000
2258
#define CAN1BTR_SAM C1BTR_SAM
2259
#define C1BTR_SAM_BIT 23
2260
#define CAN1BTR_SAM_BIT C1BTR_SAM_BIT
2261
 
2262
#define C1EWL (*(volatile unsigned long *)0xE0044018)
2263
#define CAN1EWL C1EWL
2264
#define C1EWL_OFFSET 0x18
2265
#define CAN1EWL_OFFSET C1EWL_OFFSET
2266
#define C1EWL_EWL_MASK 0xFF
2267
#define CAN1EWL_EWL_MASK C1EWL_EWL_MASK
2268
#define C1EWL_EWL_BIT 0
2269
#define CAN1EWL_EWL_BIT C1EWL_EWL_BIT
2270
 
2271
#define C1SR (*(volatile unsigned long *)0xE004401C)
2272
#define CAN1SR C1SR
2273
#define C1SR_OFFSET 0x1C
2274
#define CAN1SR_OFFSET C1SR_OFFSET
2275
#define C1SR_RBS_MASK 0x1
2276
#define CAN1SR_RBS_MASK C1SR_RBS_MASK
2277
#define C1SR_RBS 0x1
2278
#define CAN1SR_RBS C1SR_RBS
2279
#define C1SR_RBS_BIT 0
2280
#define CAN1SR_RBS_BIT C1SR_RBS_BIT
2281
#define C1SR_DOS_MASK 0x2
2282
#define CAN1SR_DOS_MASK C1SR_DOS_MASK
2283
#define C1SR_DOS 0x2
2284
#define CAN1SR_DOS C1SR_DOS
2285
#define C1SR_DOS_BIT 1
2286
#define CAN1SR_DOS_BIT C1SR_DOS_BIT
2287
#define C1SR_TBS1_MASK 0x4
2288
#define CAN1SR_TBS1_MASK C1SR_TBS1_MASK
2289
#define C1SR_TBS1 0x4
2290
#define CAN1SR_TBS1 C1SR_TBS1
2291
#define C1SR_TBS1_BIT 2
2292
#define CAN1SR_TBS1_BIT C1SR_TBS1_BIT
2293
#define C1SR_TCS1_MASK 0x8
2294
#define CAN1SR_TCS1_MASK C1SR_TCS1_MASK
2295
#define C1SR_TCS1 0x8
2296
#define CAN1SR_TCS1 C1SR_TCS1
2297
#define C1SR_TCS1_BIT 3
2298
#define CAN1SR_TCS1_BIT C1SR_TCS1_BIT
2299
#define C1SR_RS_MASK 0x10
2300
#define CAN1SR_RS_MASK C1SR_RS_MASK
2301
#define C1SR_RS 0x10
2302
#define CAN1SR_RS C1SR_RS
2303
#define C1SR_RS_BIT 4
2304
#define CAN1SR_RS_BIT C1SR_RS_BIT
2305
#define C1SR_TS1_MASK 0x20
2306
#define CAN1SR_TS1_MASK C1SR_TS1_MASK
2307
#define C1SR_TS1 0x20
2308
#define CAN1SR_TS1 C1SR_TS1
2309
#define C1SR_TS1_BIT 5
2310
#define CAN1SR_TS1_BIT C1SR_TS1_BIT
2311
#define C1SR_ES_MASK 0x40
2312
#define CAN1SR_ES_MASK C1SR_ES_MASK
2313
#define C1SR_ES 0x40
2314
#define CAN1SR_ES C1SR_ES
2315
#define C1SR_ES_BIT 6
2316
#define CAN1SR_ES_BIT C1SR_ES_BIT
2317
#define C1SR_BS_MASK 0x80
2318
#define CAN1SR_BS_MASK C1SR_BS_MASK
2319
#define C1SR_BS 0x80
2320
#define CAN1SR_BS C1SR_BS
2321
#define C1SR_BS_BIT 7
2322
#define CAN1SR_BS_BIT C1SR_BS_BIT
2323
#define C1SR_RBS2_MASK 0x100
2324
#define CAN1SR_RBS2_MASK C1SR_RBS2_MASK
2325
#define C1SR_RBS2 0x100
2326
#define CAN1SR_RBS2 C1SR_RBS2
2327
#define C1SR_RBS2_BIT 8
2328
#define CAN1SR_RBS2_BIT C1SR_RBS2_BIT
2329
#define C1SR_DOS2_MASK 0x200
2330
#define CAN1SR_DOS2_MASK C1SR_DOS2_MASK
2331
#define C1SR_DOS2 0x200
2332
#define CAN1SR_DOS2 C1SR_DOS2
2333
#define C1SR_DOS2_BIT 9
2334
#define CAN1SR_DOS2_BIT C1SR_DOS2_BIT
2335
#define C1SR_TBS2_MASK 0x400
2336
#define CAN1SR_TBS2_MASK C1SR_TBS2_MASK
2337
#define C1SR_TBS2 0x400
2338
#define CAN1SR_TBS2 C1SR_TBS2
2339
#define C1SR_TBS2_BIT 10
2340
#define CAN1SR_TBS2_BIT C1SR_TBS2_BIT
2341
#define C1SR_TCS2_MASK 0x800
2342
#define CAN1SR_TCS2_MASK C1SR_TCS2_MASK
2343
#define C1SR_TCS2 0x800
2344
#define CAN1SR_TCS2 C1SR_TCS2
2345
#define C1SR_TCS2_BIT 11
2346
#define CAN1SR_TCS2_BIT C1SR_TCS2_BIT
2347
#define C1SR_RS2_MASK 0x1000
2348
#define CAN1SR_RS2_MASK C1SR_RS2_MASK
2349
#define C1SR_RS2 0x1000
2350
#define CAN1SR_RS2 C1SR_RS2
2351
#define C1SR_RS2_BIT 12
2352
#define CAN1SR_RS2_BIT C1SR_RS2_BIT
2353
#define C1SR_TS2_MASK 0x2000
2354
#define CAN1SR_TS2_MASK C1SR_TS2_MASK
2355
#define C1SR_TS2 0x2000
2356
#define CAN1SR_TS2 C1SR_TS2
2357
#define C1SR_TS2_BIT 13
2358
#define CAN1SR_TS2_BIT C1SR_TS2_BIT
2359
#define C1SR_ES2_MASK 0x4000
2360
#define CAN1SR_ES2_MASK C1SR_ES2_MASK
2361
#define C1SR_ES2 0x4000
2362
#define CAN1SR_ES2 C1SR_ES2
2363
#define C1SR_ES2_BIT 14
2364
#define CAN1SR_ES2_BIT C1SR_ES2_BIT
2365
#define C1SR_BS2_MASK 0x8000
2366
#define CAN1SR_BS2_MASK C1SR_BS2_MASK
2367
#define C1SR_BS2 0x8000
2368
#define CAN1SR_BS2 C1SR_BS2
2369
#define C1SR_BS2_BIT 15
2370
#define CAN1SR_BS2_BIT C1SR_BS2_BIT
2371
#define C1SR_RBS3_MASK 0x10000
2372
#define CAN1SR_RBS3_MASK C1SR_RBS3_MASK
2373
#define C1SR_RBS3 0x10000
2374
#define CAN1SR_RBS3 C1SR_RBS3
2375
#define C1SR_RBS3_BIT 16
2376
#define CAN1SR_RBS3_BIT C1SR_RBS3_BIT
2377
#define C1SR_DOS3_MASK 0x20000
2378
#define CAN1SR_DOS3_MASK C1SR_DOS3_MASK
2379
#define C1SR_DOS3 0x20000
2380
#define CAN1SR_DOS3 C1SR_DOS3
2381
#define C1SR_DOS3_BIT 17
2382
#define CAN1SR_DOS3_BIT C1SR_DOS3_BIT
2383
#define C1SR_TBS3_MASK 0x40000
2384
#define CAN1SR_TBS3_MASK C1SR_TBS3_MASK
2385
#define C1SR_TBS3 0x40000
2386
#define CAN1SR_TBS3 C1SR_TBS3
2387
#define C1SR_TBS3_BIT 18
2388
#define CAN1SR_TBS3_BIT C1SR_TBS3_BIT
2389
#define C1SR_TCS3_MASK 0x80000
2390
#define CAN1SR_TCS3_MASK C1SR_TCS3_MASK
2391
#define C1SR_TCS3 0x80000
2392
#define CAN1SR_TCS3 C1SR_TCS3
2393
#define C1SR_TCS3_BIT 19
2394
#define CAN1SR_TCS3_BIT C1SR_TCS3_BIT
2395
#define C1SR_RS3_MASK 0x100000
2396
#define CAN1SR_RS3_MASK C1SR_RS3_MASK
2397
#define C1SR_RS3 0x100000
2398
#define CAN1SR_RS3 C1SR_RS3
2399
#define C1SR_RS3_BIT 20
2400
#define CAN1SR_RS3_BIT C1SR_RS3_BIT
2401
#define C1SR_TS3_MASK 0x200000
2402
#define CAN1SR_TS3_MASK C1SR_TS3_MASK
2403
#define C1SR_TS3 0x200000
2404
#define CAN1SR_TS3 C1SR_TS3
2405
#define C1SR_TS3_BIT 21
2406
#define CAN1SR_TS3_BIT C1SR_TS3_BIT
2407
#define C1SR_ES3_MASK 0x400000
2408
#define CAN1SR_ES3_MASK C1SR_ES3_MASK
2409
#define C1SR_ES3 0x400000
2410
#define CAN1SR_ES3 C1SR_ES3
2411
#define C1SR_ES3_BIT 22
2412
#define CAN1SR_ES3_BIT C1SR_ES3_BIT
2413
#define C1SR_BS3_MASK 0x800000
2414
#define CAN1SR_BS3_MASK C1SR_BS3_MASK
2415
#define C1SR_BS3 0x800000
2416
#define CAN1SR_BS3 C1SR_BS3
2417
#define C1SR_BS3_BIT 23
2418
#define CAN1SR_BS3_BIT C1SR_BS3_BIT
2419
 
2420
#define C1RFS (*(volatile unsigned long *)0xE0044020)
2421
#define CAN1RFS C1RFS
2422
#define C1RFS_OFFSET 0x20
2423
#define CAN1RFS_OFFSET C1RFS_OFFSET
2424
#define C1RFS_ID_Index_MASK 0x3FF
2425
#define CAN1RFS_ID_Index_MASK C1RFS_ID_Index_MASK
2426
#define C1RFS_ID_Index_BIT 0
2427
#define CAN1RFS_ID_Index_BIT C1RFS_ID_Index_BIT
2428
#define C1RFS_BP_MASK 0x400
2429
#define CAN1RFS_BP_MASK C1RFS_BP_MASK
2430
#define C1RFS_BP 0x400
2431
#define CAN1RFS_BP C1RFS_BP
2432
#define C1RFS_BP_BIT 10
2433
#define CAN1RFS_BP_BIT C1RFS_BP_BIT
2434
#define C1RFS_DLC_MASK 0xF0000
2435
#define CAN1RFS_DLC_MASK C1RFS_DLC_MASK
2436
#define C1RFS_DLC_BIT 16
2437
#define CAN1RFS_DLC_BIT C1RFS_DLC_BIT
2438
#define C1RFS_RTR_MASK 0x40000000
2439
#define CAN1RFS_RTR_MASK C1RFS_RTR_MASK
2440
#define C1RFS_RTR 0x40000000
2441
#define CAN1RFS_RTR C1RFS_RTR
2442
#define C1RFS_RTR_BIT 30
2443
#define CAN1RFS_RTR_BIT C1RFS_RTR_BIT
2444
#define C1RFS_FF_MASK 0x80000000
2445
#define CAN1RFS_FF_MASK C1RFS_FF_MASK
2446
#define C1RFS_FF 0x80000000
2447
#define CAN1RFS_FF C1RFS_FF
2448
#define C1RFS_FF_BIT 31
2449
#define CAN1RFS_FF_BIT C1RFS_FF_BIT
2450
 
2451
#define C1RID (*(volatile unsigned long *)0xE0044024)
2452
#define CAN1RID C1RID
2453
#define C1RID_OFFSET 0x24
2454
#define CAN1RID_OFFSET C1RID_OFFSET
2455
#define C1RID_ID_MASK 0x7FF
2456
#define CAN1RID_ID_MASK C1RID_ID_MASK
2457
#define C1RID_ID_BIT 0
2458
#define CAN1RID_ID_BIT C1RID_ID_BIT
2459
 
2460
#define C1RDA (*(volatile unsigned long *)0xE0044028)
2461
#define CAN1RDA C1RDA
2462
#define C1RDA_OFFSET 0x28
2463
#define CAN1RDA_OFFSET C1RDA_OFFSET
2464
#define C1RDA_Data_1_MASK 0xFF
2465
#define CAN1RDA_Data_1_MASK C1RDA_Data_1_MASK
2466
#define C1RDA_Data_1_BIT 0
2467
#define CAN1RDA_Data_1_BIT C1RDA_Data_1_BIT
2468
#define C1RDA_Data_2_MASK 0xFF00
2469
#define CAN1RDA_Data_2_MASK C1RDA_Data_2_MASK
2470
#define C1RDA_Data_2_BIT 8
2471
#define CAN1RDA_Data_2_BIT C1RDA_Data_2_BIT
2472
#define C1RDA_Data_3_MASK 0xFF0000
2473
#define CAN1RDA_Data_3_MASK C1RDA_Data_3_MASK
2474
#define C1RDA_Data_3_BIT 16
2475
#define CAN1RDA_Data_3_BIT C1RDA_Data_3_BIT
2476
#define C1RDA_Data_4_MASK 0xFF000000
2477
#define CAN1RDA_Data_4_MASK C1RDA_Data_4_MASK
2478
#define C1RDA_Data_4_BIT 24
2479
#define CAN1RDA_Data_4_BIT C1RDA_Data_4_BIT
2480
 
2481
#define C1RDB (*(volatile unsigned long *)0xE004402C)
2482
#define CAN1RDB C1RDB
2483
#define C1RDB_OFFSET 0x2C
2484
#define CAN1RDB_OFFSET C1RDB_OFFSET
2485
#define C1RDB_Data_5_MASK 0xFF
2486
#define CAN1RDB_Data_5_MASK C1RDB_Data_5_MASK
2487
#define C1RDB_Data_5_BIT 0
2488
#define CAN1RDB_Data_5_BIT C1RDB_Data_5_BIT
2489
#define C1RDB_Data_6_MASK 0xFF00
2490
#define CAN1RDB_Data_6_MASK C1RDB_Data_6_MASK
2491
#define C1RDB_Data_6_BIT 8
2492
#define CAN1RDB_Data_6_BIT C1RDB_Data_6_BIT
2493
#define C1RDB_Data_7_MASK 0xFF0000
2494
#define CAN1RDB_Data_7_MASK C1RDB_Data_7_MASK
2495
#define C1RDB_Data_7_BIT 16
2496
#define CAN1RDB_Data_7_BIT C1RDB_Data_7_BIT
2497
#define C1RDB_Data_8_MASK 0xFF000000
2498
#define CAN1RDB_Data_8_MASK C1RDB_Data_8_MASK
2499
#define C1RDB_Data_8_BIT 24
2500
#define CAN1RDB_Data_8_BIT C1RDB_Data_8_BIT
2501
 
2502
#define C1TFI1 (*(volatile unsigned long *)0xE0044030)
2503
#define CAN1TFI1 C1TFI1
2504
#define C1TFI1_OFFSET 0x30
2505
#define CAN1TFI1_OFFSET C1TFI1_OFFSET
2506
#define C1TFI1_PRIO_MASK 0xFF
2507
#define CAN1TFI1_PRIO_MASK C1TFI1_PRIO_MASK
2508
#define C1TFI1_PRIO_BIT 0
2509
#define CAN1TFI1_PRIO_BIT C1TFI1_PRIO_BIT
2510
#define C1TFI1_DLC_MASK 0xF0000
2511
#define CAN1TFI1_DLC_MASK C1TFI1_DLC_MASK
2512
#define C1TFI1_DLC_BIT 16
2513
#define CAN1TFI1_DLC_BIT C1TFI1_DLC_BIT
2514
#define C1TFI1_RTR_MASK 0x40000000
2515
#define CAN1TFI1_RTR_MASK C1TFI1_RTR_MASK
2516
#define C1TFI1_RTR 0x40000000
2517
#define CAN1TFI1_RTR C1TFI1_RTR
2518
#define C1TFI1_RTR_BIT 30
2519
#define CAN1TFI1_RTR_BIT C1TFI1_RTR_BIT
2520
#define C1TFI1_FF_MASK 0x80000000
2521
#define CAN1TFI1_FF_MASK C1TFI1_FF_MASK
2522
#define C1TFI1_FF 0x80000000
2523
#define CAN1TFI1_FF C1TFI1_FF
2524
#define C1TFI1_FF_BIT 31
2525
#define CAN1TFI1_FF_BIT C1TFI1_FF_BIT
2526
 
2527
#define C1TID1 (*(volatile unsigned long *)0xE0044034)
2528
#define CAN1TID1 C1TID1
2529
#define C1TID1_OFFSET 0x34
2530
#define CAN1TID1_OFFSET C1TID1_OFFSET
2531
#define C1TID1_ID_MASK 0x7FF
2532
#define CAN1TID1_ID_MASK C1TID1_ID_MASK
2533
#define C1TID1_ID_BIT 0
2534
#define CAN1TID1_ID_BIT C1TID1_ID_BIT
2535
 
2536
#define C1TDA1 (*(volatile unsigned long *)0xE0044038)
2537
#define CAN1TDA1 C1TDA1
2538
#define C1TDA1_OFFSET 0x38
2539
#define CAN1TDA1_OFFSET C1TDA1_OFFSET
2540
#define C1TDA1_Data_1_MASK 0xFF
2541
#define CAN1TDA1_Data_1_MASK C1TDA1_Data_1_MASK
2542
#define C1TDA1_Data_1_BIT 0
2543
#define CAN1TDA1_Data_1_BIT C1TDA1_Data_1_BIT
2544
#define C1TDA1_Data_2_MASK 0xFF00
2545
#define CAN1TDA1_Data_2_MASK C1TDA1_Data_2_MASK
2546
#define C1TDA1_Data_2_BIT 8
2547
#define CAN1TDA1_Data_2_BIT C1TDA1_Data_2_BIT
2548
#define C1TDA1_Data_3_MASK 0xFF0000
2549
#define CAN1TDA1_Data_3_MASK C1TDA1_Data_3_MASK
2550
#define C1TDA1_Data_3_BIT 16
2551
#define CAN1TDA1_Data_3_BIT C1TDA1_Data_3_BIT
2552
#define C1TDA1_Data_4_MASK 0xFF000000
2553
#define CAN1TDA1_Data_4_MASK C1TDA1_Data_4_MASK
2554
#define C1TDA1_Data_4_BIT 24
2555
#define CAN1TDA1_Data_4_BIT C1TDA1_Data_4_BIT
2556
 
2557
#define C1TDB1 (*(volatile unsigned long *)0xE004403C)
2558
#define CAN1TDB1 C1TDB1
2559
#define C1TDB1_OFFSET 0x3C
2560
#define CAN1TDB1_OFFSET C1TDB1_OFFSET
2561
#define C1TDB1_Data_5_MASK 0xFF
2562
#define CAN1TDB1_Data_5_MASK C1TDB1_Data_5_MASK
2563
#define C1TDB1_Data_5_BIT 0
2564
#define CAN1TDB1_Data_5_BIT C1TDB1_Data_5_BIT
2565
#define C1TDB1_Data_6_MASK 0xFF00
2566
#define CAN1TDB1_Data_6_MASK C1TDB1_Data_6_MASK
2567
#define C1TDB1_Data_6_BIT 8
2568
#define CAN1TDB1_Data_6_BIT C1TDB1_Data_6_BIT
2569
#define C1TDB1_Data_7_MASK 0xFF0000
2570
#define CAN1TDB1_Data_7_MASK C1TDB1_Data_7_MASK
2571
#define C1TDB1_Data_7_BIT 16
2572
#define CAN1TDB1_Data_7_BIT C1TDB1_Data_7_BIT
2573
#define C1TDB1_Data_8_MASK 0xFF000000
2574
#define CAN1TDB1_Data_8_MASK C1TDB1_Data_8_MASK
2575
#define C1TDB1_Data_8_BIT 24
2576
#define CAN1TDB1_Data_8_BIT C1TDB1_Data_8_BIT
2577
 
2578
#define C1TFI2 (*(volatile unsigned long *)0xE0044040)
2579
#define CAN1TFI2 C1TFI2
2580
#define C1TFI2_OFFSET 0x40
2581
#define CAN1TFI2_OFFSET C1TFI2_OFFSET
2582
#define C1TFI2_PRIO_MASK 0xFF
2583
#define CAN1TFI2_PRIO_MASK C1TFI2_PRIO_MASK
2584
#define C1TFI2_PRIO_BIT 0
2585
#define CAN1TFI2_PRIO_BIT C1TFI2_PRIO_BIT
2586
#define C1TFI2_DLC_MASK 0xF0000
2587
#define CAN1TFI2_DLC_MASK C1TFI2_DLC_MASK
2588
#define C1TFI2_DLC_BIT 16
2589
#define CAN1TFI2_DLC_BIT C1TFI2_DLC_BIT
2590
#define C1TFI2_RTR_MASK 0x40000000
2591
#define CAN1TFI2_RTR_MASK C1TFI2_RTR_MASK
2592
#define C1TFI2_RTR 0x40000000
2593
#define CAN1TFI2_RTR C1TFI2_RTR
2594
#define C1TFI2_RTR_BIT 30
2595
#define CAN1TFI2_RTR_BIT C1TFI2_RTR_BIT
2596
#define C1TFI2_FF_MASK 0x80000000
2597
#define CAN1TFI2_FF_MASK C1TFI2_FF_MASK
2598
#define C1TFI2_FF 0x80000000
2599
#define CAN1TFI2_FF C1TFI2_FF
2600
#define C1TFI2_FF_BIT 31
2601
#define CAN1TFI2_FF_BIT C1TFI2_FF_BIT
2602
 
2603
#define C1TID2 (*(volatile unsigned long *)0xE0044044)
2604
#define CAN1TID2 C1TID2
2605
#define C1TID2_OFFSET 0x44
2606
#define CAN1TID2_OFFSET C1TID2_OFFSET
2607
#define C1TID2_ID_MASK 0x7FF
2608
#define CAN1TID2_ID_MASK C1TID2_ID_MASK
2609
#define C1TID2_ID_BIT 0
2610
#define CAN1TID2_ID_BIT C1TID2_ID_BIT
2611
 
2612
#define C1TDA2 (*(volatile unsigned long *)0xE0044048)
2613
#define CAN1TDA2 C1TDA2
2614
#define C1TDA2_OFFSET 0x48
2615
#define CAN1TDA2_OFFSET C1TDA2_OFFSET
2616
#define C1TDA2_Data_1_MASK 0xFF
2617
#define CAN1TDA2_Data_1_MASK C1TDA2_Data_1_MASK
2618
#define C1TDA2_Data_1_BIT 0
2619
#define CAN1TDA2_Data_1_BIT C1TDA2_Data_1_BIT
2620
#define C1TDA2_Data_2_MASK 0xFF00
2621
#define CAN1TDA2_Data_2_MASK C1TDA2_Data_2_MASK
2622
#define C1TDA2_Data_2_BIT 8
2623
#define CAN1TDA2_Data_2_BIT C1TDA2_Data_2_BIT
2624
#define C1TDA2_Data_3_MASK 0xFF0000
2625
#define CAN1TDA2_Data_3_MASK C1TDA2_Data_3_MASK
2626
#define C1TDA2_Data_3_BIT 16
2627
#define CAN1TDA2_Data_3_BIT C1TDA2_Data_3_BIT
2628
#define C1TDA2_Data_4_MASK 0xFF000000
2629
#define CAN1TDA2_Data_4_MASK C1TDA2_Data_4_MASK
2630
#define C1TDA2_Data_4_BIT 24
2631
#define CAN1TDA2_Data_4_BIT C1TDA2_Data_4_BIT
2632
 
2633
#define C1TDB2 (*(volatile unsigned long *)0xE004404C)
2634
#define CAN1TDB2 C1TDB2
2635
#define C1TDB2_OFFSET 0x4C
2636
#define CAN1TDB2_OFFSET C1TDB2_OFFSET
2637
#define C1TDB2_Data_5_MASK 0xFF
2638
#define CAN1TDB2_Data_5_MASK C1TDB2_Data_5_MASK
2639
#define C1TDB2_Data_5_BIT 0
2640
#define CAN1TDB2_Data_5_BIT C1TDB2_Data_5_BIT
2641
#define C1TDB2_Data_6_MASK 0xFF00
2642
#define CAN1TDB2_Data_6_MASK C1TDB2_Data_6_MASK
2643
#define C1TDB2_Data_6_BIT 8
2644
#define CAN1TDB2_Data_6_BIT C1TDB2_Data_6_BIT
2645
#define C1TDB2_Data_7_MASK 0xFF0000
2646
#define CAN1TDB2_Data_7_MASK C1TDB2_Data_7_MASK
2647
#define C1TDB2_Data_7_BIT 16
2648
#define CAN1TDB2_Data_7_BIT C1TDB2_Data_7_BIT
2649
#define C1TDB2_Data_8_MASK 0xFF000000
2650
#define CAN1TDB2_Data_8_MASK C1TDB2_Data_8_MASK
2651
#define C1TDB2_Data_8_BIT 24
2652
#define CAN1TDB2_Data_8_BIT C1TDB2_Data_8_BIT
2653
 
2654
#define C1TFI3 (*(volatile unsigned long *)0xE0044050)
2655
#define CAN1TFI3 C1TFI3
2656
#define C1TFI3_OFFSET 0x50
2657
#define CAN1TFI3_OFFSET C1TFI3_OFFSET
2658
#define C1TFI3_PRIO_MASK 0xFF
2659
#define CAN1TFI3_PRIO_MASK C1TFI3_PRIO_MASK
2660
#define C1TFI3_PRIO_BIT 0
2661
#define CAN1TFI3_PRIO_BIT C1TFI3_PRIO_BIT
2662
#define C1TFI3_DLC_MASK 0xF0000
2663
#define CAN1TFI3_DLC_MASK C1TFI3_DLC_MASK
2664
#define C1TFI3_DLC_BIT 16
2665
#define CAN1TFI3_DLC_BIT C1TFI3_DLC_BIT
2666
#define C1TFI3_RTR_MASK 0x40000000
2667
#define CAN1TFI3_RTR_MASK C1TFI3_RTR_MASK
2668
#define C1TFI3_RTR 0x40000000
2669
#define CAN1TFI3_RTR C1TFI3_RTR
2670
#define C1TFI3_RTR_BIT 30
2671
#define CAN1TFI3_RTR_BIT C1TFI3_RTR_BIT
2672
#define C1TFI3_FF_MASK 0x80000000
2673
#define CAN1TFI3_FF_MASK C1TFI3_FF_MASK
2674
#define C1TFI3_FF 0x80000000
2675
#define CAN1TFI3_FF C1TFI3_FF
2676
#define C1TFI3_FF_BIT 31
2677
#define CAN1TFI3_FF_BIT C1TFI3_FF_BIT
2678
 
2679
#define C1TID3 (*(volatile unsigned long *)0xE0044054)
2680
#define CAN1TID3 C1TID3
2681
#define C1TID3_OFFSET 0x54
2682
#define CAN1TID3_OFFSET C1TID3_OFFSET
2683
#define C1TID3_ID_MASK 0x7FF
2684
#define CAN1TID3_ID_MASK C1TID3_ID_MASK
2685
#define C1TID3_ID_BIT 0
2686
#define CAN1TID3_ID_BIT C1TID3_ID_BIT
2687
 
2688
#define C1TDA3 (*(volatile unsigned long *)0xE0044058)
2689
#define CAN1TDA3 C1TDA3
2690
#define C1TDA3_OFFSET 0x58
2691
#define CAN1TDA3_OFFSET C1TDA3_OFFSET
2692
#define C1TDA3_Data_1_MASK 0xFF
2693
#define CAN1TDA3_Data_1_MASK C1TDA3_Data_1_MASK
2694
#define C1TDA3_Data_1_BIT 0
2695
#define CAN1TDA3_Data_1_BIT C1TDA3_Data_1_BIT
2696
#define C1TDA3_Data_2_MASK 0xFF00
2697
#define CAN1TDA3_Data_2_MASK C1TDA3_Data_2_MASK
2698
#define C1TDA3_Data_2_BIT 8
2699
#define CAN1TDA3_Data_2_BIT C1TDA3_Data_2_BIT
2700
#define C1TDA3_Data_3_MASK 0xFF0000
2701
#define CAN1TDA3_Data_3_MASK C1TDA3_Data_3_MASK
2702
#define C1TDA3_Data_3_BIT 16
2703
#define CAN1TDA3_Data_3_BIT C1TDA3_Data_3_BIT
2704
#define C1TDA3_Data_4_MASK 0xFF000000
2705
#define CAN1TDA3_Data_4_MASK C1TDA3_Data_4_MASK
2706
#define C1TDA3_Data_4_BIT 24
2707
#define CAN1TDA3_Data_4_BIT C1TDA3_Data_4_BIT
2708
 
2709
#define C1TDB3 (*(volatile unsigned long *)0xE004405C)
2710
#define CAN1TDB3 C1TDB3
2711
#define C1TDB3_OFFSET 0x5C
2712
#define CAN1TDB3_OFFSET C1TDB3_OFFSET
2713
#define C1TDB3_Data_5_MASK 0xFF
2714
#define CAN1TDB3_Data_5_MASK C1TDB3_Data_5_MASK
2715
#define C1TDB3_Data_5_BIT 0
2716
#define CAN1TDB3_Data_5_BIT C1TDB3_Data_5_BIT
2717
#define C1TDB3_Data_6_MASK 0xFF00
2718
#define CAN1TDB3_Data_6_MASK C1TDB3_Data_6_MASK
2719
#define C1TDB3_Data_6_BIT 8
2720
#define CAN1TDB3_Data_6_BIT C1TDB3_Data_6_BIT
2721
#define C1TDB3_Data_7_MASK 0xFF0000
2722
#define CAN1TDB3_Data_7_MASK C1TDB3_Data_7_MASK
2723
#define C1TDB3_Data_7_BIT 16
2724
#define CAN1TDB3_Data_7_BIT C1TDB3_Data_7_BIT
2725
#define C1TDB3_Data_8_MASK 0xFF000000
2726
#define CAN1TDB3_Data_8_MASK C1TDB3_Data_8_MASK
2727
#define C1TDB3_Data_8_BIT 24
2728
#define CAN1TDB3_Data_8_BIT C1TDB3_Data_8_BIT
2729
 
2730
#define CAN2_BASE 0xE0048000
2731
 
2732
#define C2MOD (*(volatile unsigned long *)0xE0048000)
2733
#define CAN2MOD C2MOD
2734
#define C2MOD_OFFSET 0x0
2735
#define CAN2MOD_OFFSET C2MOD_OFFSET
2736
#define C2MOD_RM_MASK 0x1
2737
#define CAN2MOD_RM_MASK C2MOD_RM_MASK
2738
#define C2MOD_RM 0x1
2739
#define CAN2MOD_RM C2MOD_RM
2740
#define C2MOD_RM_BIT 0
2741
#define CAN2MOD_RM_BIT C2MOD_RM_BIT
2742
#define C2MOD_LOM_MASK 0x2
2743
#define CAN2MOD_LOM_MASK C2MOD_LOM_MASK
2744
#define C2MOD_LOM 0x2
2745
#define CAN2MOD_LOM C2MOD_LOM
2746
#define C2MOD_LOM_BIT 1
2747
#define CAN2MOD_LOM_BIT C2MOD_LOM_BIT
2748
#define C2MOD_STM_MASK 0x4
2749
#define CAN2MOD_STM_MASK C2MOD_STM_MASK
2750
#define C2MOD_STM 0x4
2751
#define CAN2MOD_STM C2MOD_STM
2752
#define C2MOD_STM_BIT 2
2753
#define CAN2MOD_STM_BIT C2MOD_STM_BIT
2754
#define C2MOD_TPM_MASK 0x8
2755
#define CAN2MOD_TPM_MASK C2MOD_TPM_MASK
2756
#define C2MOD_TPM 0x8
2757
#define CAN2MOD_TPM C2MOD_TPM
2758
#define C2MOD_TPM_BIT 3
2759
#define CAN2MOD_TPM_BIT C2MOD_TPM_BIT
2760
#define C2MOD_SM_MASK 0x10
2761
#define CAN2MOD_SM_MASK C2MOD_SM_MASK
2762
#define C2MOD_SM 0x10
2763
#define CAN2MOD_SM C2MOD_SM
2764
#define C2MOD_SM_BIT 4
2765
#define CAN2MOD_SM_BIT C2MOD_SM_BIT
2766
#define C2MOD_RPM_MASK 0x20
2767
#define CAN2MOD_RPM_MASK C2MOD_RPM_MASK
2768
#define C2MOD_RPM 0x20
2769
#define CAN2MOD_RPM C2MOD_RPM
2770
#define C2MOD_RPM_BIT 5
2771
#define CAN2MOD_RPM_BIT C2MOD_RPM_BIT
2772
#define C2MOD_TM_MASK 0x80
2773
#define CAN2MOD_TM_MASK C2MOD_TM_MASK
2774
#define C2MOD_TM 0x80
2775
#define CAN2MOD_TM C2MOD_TM
2776
#define C2MOD_TM_BIT 7
2777
#define CAN2MOD_TM_BIT C2MOD_TM_BIT
2778
 
2779
#define C2CMR (*(volatile unsigned long *)0xE0048004)
2780
#define CAN2CMR C2CMR
2781
#define C2CMR_OFFSET 0x4
2782
#define CAN2CMR_OFFSET C2CMR_OFFSET
2783
#define C2CMR_TR_MASK 0x1
2784
#define CAN2CMR_TR_MASK C2CMR_TR_MASK
2785
#define C2CMR_TR 0x1
2786
#define CAN2CMR_TR C2CMR_TR
2787
#define C2CMR_TR_BIT 0
2788
#define CAN2CMR_TR_BIT C2CMR_TR_BIT
2789
#define C2CMR_AT_MASK 0x2
2790
#define CAN2CMR_AT_MASK C2CMR_AT_MASK
2791
#define C2CMR_AT 0x2
2792
#define CAN2CMR_AT C2CMR_AT
2793
#define C2CMR_AT_BIT 1
2794
#define CAN2CMR_AT_BIT C2CMR_AT_BIT
2795
#define C2CMR_RRB_MASK 0x4
2796
#define CAN2CMR_RRB_MASK C2CMR_RRB_MASK
2797
#define C2CMR_RRB 0x4
2798
#define CAN2CMR_RRB C2CMR_RRB
2799
#define C2CMR_RRB_BIT 2
2800
#define CAN2CMR_RRB_BIT C2CMR_RRB_BIT
2801
#define C2CMR_CDO_MASK 0x8
2802
#define CAN2CMR_CDO_MASK C2CMR_CDO_MASK
2803
#define C2CMR_CDO 0x8
2804
#define CAN2CMR_CDO C2CMR_CDO
2805
#define C2CMR_CDO_BIT 3
2806
#define CAN2CMR_CDO_BIT C2CMR_CDO_BIT
2807
#define C2CMR_SRR_MASK 0x10
2808
#define CAN2CMR_SRR_MASK C2CMR_SRR_MASK
2809
#define C2CMR_SRR 0x10
2810
#define CAN2CMR_SRR C2CMR_SRR
2811
#define C2CMR_SRR_BIT 4
2812
#define CAN2CMR_SRR_BIT C2CMR_SRR_BIT
2813
#define C2CMR_STB1_MASK 0x20
2814
#define CAN2CMR_STB1_MASK C2CMR_STB1_MASK
2815
#define C2CMR_STB1 0x20
2816
#define CAN2CMR_STB1 C2CMR_STB1
2817
#define C2CMR_STB1_BIT 5
2818
#define CAN2CMR_STB1_BIT C2CMR_STB1_BIT
2819
#define C2CMR_STB2_MASK 0x40
2820
#define CAN2CMR_STB2_MASK C2CMR_STB2_MASK
2821
#define C2CMR_STB2 0x40
2822
#define CAN2CMR_STB2 C2CMR_STB2
2823
#define C2CMR_STB2_BIT 6
2824
#define CAN2CMR_STB2_BIT C2CMR_STB2_BIT
2825
#define C2CMR_STB3_MASK 0x80
2826
#define CAN2CMR_STB3_MASK C2CMR_STB3_MASK
2827
#define C2CMR_STB3 0x80
2828
#define CAN2CMR_STB3 C2CMR_STB3
2829
#define C2CMR_STB3_BIT 7
2830
#define CAN2CMR_STB3_BIT C2CMR_STB3_BIT
2831
 
2832
#define C2GSR (*(volatile unsigned long *)0xE0048008)
2833
#define CAN2GSR C2GSR
2834
#define C2GSR_OFFSET 0x8
2835
#define CAN2GSR_OFFSET C2GSR_OFFSET
2836
#define C2GSR_RBS_MASK 0x1
2837
#define CAN2GSR_RBS_MASK C2GSR_RBS_MASK
2838
#define C2GSR_RBS 0x1
2839
#define CAN2GSR_RBS C2GSR_RBS
2840
#define C2GSR_RBS_BIT 0
2841
#define CAN2GSR_RBS_BIT C2GSR_RBS_BIT
2842
#define C2GSR_DOS_MASK 0x2
2843
#define CAN2GSR_DOS_MASK C2GSR_DOS_MASK
2844
#define C2GSR_DOS 0x2
2845
#define CAN2GSR_DOS C2GSR_DOS
2846
#define C2GSR_DOS_BIT 1
2847
#define CAN2GSR_DOS_BIT C2GSR_DOS_BIT
2848
#define C2GSR_TBS_MASK 0x4
2849
#define CAN2GSR_TBS_MASK C2GSR_TBS_MASK
2850
#define C2GSR_TBS 0x4
2851
#define CAN2GSR_TBS C2GSR_TBS
2852
#define C2GSR_TBS_BIT 2
2853
#define CAN2GSR_TBS_BIT C2GSR_TBS_BIT
2854
#define C2GSR_TCS_MASK 0x8
2855
#define CAN2GSR_TCS_MASK C2GSR_TCS_MASK
2856
#define C2GSR_TCS 0x8
2857
#define CAN2GSR_TCS C2GSR_TCS
2858
#define C2GSR_TCS_BIT 3
2859
#define CAN2GSR_TCS_BIT C2GSR_TCS_BIT
2860
#define C2GSR_RS_MASK 0x10
2861
#define CAN2GSR_RS_MASK C2GSR_RS_MASK
2862
#define C2GSR_RS 0x10
2863
#define CAN2GSR_RS C2GSR_RS
2864
#define C2GSR_RS_BIT 4
2865
#define CAN2GSR_RS_BIT C2GSR_RS_BIT
2866
#define C2GSR_TS_MASK 0x20
2867
#define CAN2GSR_TS_MASK C2GSR_TS_MASK
2868
#define C2GSR_TS 0x20
2869
#define CAN2GSR_TS C2GSR_TS
2870
#define C2GSR_TS_BIT 5
2871
#define CAN2GSR_TS_BIT C2GSR_TS_BIT
2872
#define C2GSR_ES_MASK 0x40
2873
#define CAN2GSR_ES_MASK C2GSR_ES_MASK
2874
#define C2GSR_ES 0x40
2875
#define CAN2GSR_ES C2GSR_ES
2876
#define C2GSR_ES_BIT 6
2877
#define CAN2GSR_ES_BIT C2GSR_ES_BIT
2878
#define C2GSR_BS_MASK 0x80
2879
#define CAN2GSR_BS_MASK C2GSR_BS_MASK
2880
#define C2GSR_BS 0x80
2881
#define CAN2GSR_BS C2GSR_BS
2882
#define C2GSR_BS_BIT 7
2883
#define CAN2GSR_BS_BIT C2GSR_BS_BIT
2884
#define C2GSR_RXERR_MASK 0xFF0000
2885
#define CAN2GSR_RXERR_MASK C2GSR_RXERR_MASK
2886
#define C2GSR_RXERR_BIT 16
2887
#define CAN2GSR_RXERR_BIT C2GSR_RXERR_BIT
2888
#define C2GSR_TXERR_MASK 0xFF000000
2889
#define CAN2GSR_TXERR_MASK C2GSR_TXERR_MASK
2890
#define C2GSR_TXERR_BIT 24
2891
#define CAN2GSR_TXERR_BIT C2GSR_TXERR_BIT
2892
 
2893
#define C2ICR (*(volatile unsigned long *)0xE004800C)
2894
#define CAN2ICR C2ICR
2895
#define C2ICR_OFFSET 0xC
2896
#define CAN2ICR_OFFSET C2ICR_OFFSET
2897
#define C2ICR_RI_MASK 0x1
2898
#define CAN2ICR_RI_MASK C2ICR_RI_MASK
2899
#define C2ICR_RI 0x1
2900
#define CAN2ICR_RI C2ICR_RI
2901
#define C2ICR_RI_BIT 0
2902
#define CAN2ICR_RI_BIT C2ICR_RI_BIT
2903
#define C2ICR_TI1_MASK 0x2
2904
#define CAN2ICR_TI1_MASK C2ICR_TI1_MASK
2905
#define C2ICR_TI1 0x2
2906
#define CAN2ICR_TI1 C2ICR_TI1
2907
#define C2ICR_TI1_BIT 1
2908
#define CAN2ICR_TI1_BIT C2ICR_TI1_BIT
2909
#define C2ICR_EI_MASK 0x4
2910
#define CAN2ICR_EI_MASK C2ICR_EI_MASK
2911
#define C2ICR_EI 0x4
2912
#define CAN2ICR_EI C2ICR_EI
2913
#define C2ICR_EI_BIT 2
2914
#define CAN2ICR_EI_BIT C2ICR_EI_BIT
2915
#define C2ICR_DOI_MASK 0x8
2916
#define CAN2ICR_DOI_MASK C2ICR_DOI_MASK
2917
#define C2ICR_DOI 0x8
2918
#define CAN2ICR_DOI C2ICR_DOI
2919
#define C2ICR_DOI_BIT 3
2920
#define CAN2ICR_DOI_BIT C2ICR_DOI_BIT
2921
#define C2ICR_WUI_MASK 0x10
2922
#define CAN2ICR_WUI_MASK C2ICR_WUI_MASK
2923
#define C2ICR_WUI 0x10
2924
#define CAN2ICR_WUI C2ICR_WUI
2925
#define C2ICR_WUI_BIT 4
2926
#define CAN2ICR_WUI_BIT C2ICR_WUI_BIT
2927
#define C2ICR_EPI_MASK 0x20
2928
#define CAN2ICR_EPI_MASK C2ICR_EPI_MASK
2929
#define C2ICR_EPI 0x20
2930
#define CAN2ICR_EPI C2ICR_EPI
2931
#define C2ICR_EPI_BIT 5
2932
#define CAN2ICR_EPI_BIT C2ICR_EPI_BIT
2933
#define C2ICR_ALI_MASK 0x40
2934
#define CAN2ICR_ALI_MASK C2ICR_ALI_MASK
2935
#define C2ICR_ALI 0x40
2936
#define CAN2ICR_ALI C2ICR_ALI
2937
#define C2ICR_ALI_BIT 6
2938
#define CAN2ICR_ALI_BIT C2ICR_ALI_BIT
2939
#define C2ICR_BEI_MASK 0x80
2940
#define CAN2ICR_BEI_MASK C2ICR_BEI_MASK
2941
#define C2ICR_BEI 0x80
2942
#define CAN2ICR_BEI C2ICR_BEI
2943
#define C2ICR_BEI_BIT 7
2944
#define CAN2ICR_BEI_BIT C2ICR_BEI_BIT
2945
#define C2ICR_IDI_MASK 0x100
2946
#define CAN2ICR_IDI_MASK C2ICR_IDI_MASK
2947
#define C2ICR_IDI 0x100
2948
#define CAN2ICR_IDI C2ICR_IDI
2949
#define C2ICR_IDI_BIT 8
2950
#define CAN2ICR_IDI_BIT C2ICR_IDI_BIT
2951
#define C2ICR_TI2_MASK 0x200
2952
#define CAN2ICR_TI2_MASK C2ICR_TI2_MASK
2953
#define C2ICR_TI2 0x200
2954
#define CAN2ICR_TI2 C2ICR_TI2
2955
#define C2ICR_TI2_BIT 9
2956
#define CAN2ICR_TI2_BIT C2ICR_TI2_BIT
2957
#define C2ICR_TI3_MASK 0x400
2958
#define CAN2ICR_TI3_MASK C2ICR_TI3_MASK
2959
#define C2ICR_TI3 0x400
2960
#define CAN2ICR_TI3 C2ICR_TI3
2961
#define C2ICR_TI3_BIT 10
2962
#define CAN2ICR_TI3_BIT C2ICR_TI3_BIT
2963
#define C2ICR_ERRBIT_MASK 0x1F0000
2964
#define CAN2ICR_ERRBIT_MASK C2ICR_ERRBIT_MASK
2965
#define C2ICR_ERRBIT_BIT 16
2966
#define CAN2ICR_ERRBIT_BIT C2ICR_ERRBIT_BIT
2967
#define C2ICR_ERRDIR_MASK 0x200000
2968
#define CAN2ICR_ERRDIR_MASK C2ICR_ERRDIR_MASK
2969
#define C2ICR_ERRDIR 0x200000
2970
#define CAN2ICR_ERRDIR C2ICR_ERRDIR
2971
#define C2ICR_ERRDIR_BIT 21
2972
#define CAN2ICR_ERRDIR_BIT C2ICR_ERRDIR_BIT
2973
#define C2ICR_ERRC_MASK 0xC00000
2974
#define CAN2ICR_ERRC_MASK C2ICR_ERRC_MASK
2975
#define C2ICR_ERRC_BIT 22
2976
#define CAN2ICR_ERRC_BIT C2ICR_ERRC_BIT
2977
#define C2ICR_ALCBIT_MASK 0x1F000000
2978
#define CAN2ICR_ALCBIT_MASK C2ICR_ALCBIT_MASK
2979
#define C2ICR_ALCBIT_BIT 24
2980
#define CAN2ICR_ALCBIT_BIT C2ICR_ALCBIT_BIT
2981
 
2982
#define C2IER (*(volatile unsigned long *)0xE0048010)
2983
#define CAN2IER C2IER
2984
#define C2IER_OFFSET 0x10
2985
#define CAN2IER_OFFSET C2IER_OFFSET
2986
#define C2IER_RIE_MASK 0x1
2987
#define CAN2IER_RIE_MASK C2IER_RIE_MASK
2988
#define C2IER_RIE 0x1
2989
#define CAN2IER_RIE C2IER_RIE
2990
#define C2IER_RIE_BIT 0
2991
#define CAN2IER_RIE_BIT C2IER_RIE_BIT
2992
#define C2IER_TIE1_MASK 0x2
2993
#define CAN2IER_TIE1_MASK C2IER_TIE1_MASK
2994
#define C2IER_TIE1 0x2
2995
#define CAN2IER_TIE1 C2IER_TIE1
2996
#define C2IER_TIE1_BIT 1
2997
#define CAN2IER_TIE1_BIT C2IER_TIE1_BIT
2998
#define C2IER_EIE_MASK 0x4
2999
#define CAN2IER_EIE_MASK C2IER_EIE_MASK
3000
#define C2IER_EIE 0x4
3001
#define CAN2IER_EIE C2IER_EIE
3002
#define C2IER_EIE_BIT 2
3003
#define CAN2IER_EIE_BIT C2IER_EIE_BIT
3004
#define C2IER_DOIE_MASK 0x8
3005
#define CAN2IER_DOIE_MASK C2IER_DOIE_MASK
3006
#define C2IER_DOIE 0x8
3007
#define CAN2IER_DOIE C2IER_DOIE
3008
#define C2IER_DOIE_BIT 3
3009
#define CAN2IER_DOIE_BIT C2IER_DOIE_BIT
3010
#define C2IER_WUIE_MASK 0x10
3011
#define CAN2IER_WUIE_MASK C2IER_WUIE_MASK
3012
#define C2IER_WUIE 0x10
3013
#define CAN2IER_WUIE C2IER_WUIE
3014
#define C2IER_WUIE_BIT 4
3015
#define CAN2IER_WUIE_BIT C2IER_WUIE_BIT
3016
#define C2IER_EPIE_MASK 0x20
3017
#define CAN2IER_EPIE_MASK C2IER_EPIE_MASK
3018
#define C2IER_EPIE 0x20
3019
#define CAN2IER_EPIE C2IER_EPIE
3020
#define C2IER_EPIE_BIT 5
3021
#define CAN2IER_EPIE_BIT C2IER_EPIE_BIT
3022
#define C2IER_ALIE_MASK 0x40
3023
#define CAN2IER_ALIE_MASK C2IER_ALIE_MASK
3024
#define C2IER_ALIE 0x40
3025
#define CAN2IER_ALIE C2IER_ALIE
3026
#define C2IER_ALIE_BIT 6
3027
#define CAN2IER_ALIE_BIT C2IER_ALIE_BIT
3028
#define C2IER_BEIE_MASK 0x80
3029
#define CAN2IER_BEIE_MASK C2IER_BEIE_MASK
3030
#define C2IER_BEIE 0x80
3031
#define CAN2IER_BEIE C2IER_BEIE
3032
#define C2IER_BEIE_BIT 7
3033
#define CAN2IER_BEIE_BIT C2IER_BEIE_BIT
3034
#define C2IER_IDIE_MASK 0x100
3035
#define CAN2IER_IDIE_MASK C2IER_IDIE_MASK
3036
#define C2IER_IDIE 0x100
3037
#define CAN2IER_IDIE C2IER_IDIE
3038
#define C2IER_IDIE_BIT 8
3039
#define CAN2IER_IDIE_BIT C2IER_IDIE_BIT
3040
#define C2IER_TIE2_MASK 0x200
3041
#define CAN2IER_TIE2_MASK C2IER_TIE2_MASK
3042
#define C2IER_TIE2 0x200
3043
#define CAN2IER_TIE2 C2IER_TIE2
3044
#define C2IER_TIE2_BIT 9
3045
#define CAN2IER_TIE2_BIT C2IER_TIE2_BIT
3046
#define C2IER_TIE3_MASK 0x400
3047
#define CAN2IER_TIE3_MASK C2IER_TIE3_MASK
3048
#define C2IER_TIE3 0x400
3049
#define CAN2IER_TIE3 C2IER_TIE3
3050
#define C2IER_TIE3_BIT 10
3051
#define CAN2IER_TIE3_BIT C2IER_TIE3_BIT
3052
 
3053
#define C2BTR (*(volatile unsigned long *)0xE0048014)
3054
#define CAN2BTR C2BTR
3055
#define C2BTR_OFFSET 0x14
3056
#define CAN2BTR_OFFSET C2BTR_OFFSET
3057
#define C2BTR_BRP_MASK 0x3FF
3058
#define CAN2BTR_BRP_MASK C2BTR_BRP_MASK
3059
#define C2BTR_BRP_BIT 0
3060
#define CAN2BTR_BRP_BIT C2BTR_BRP_BIT
3061
#define C2BTR_SJW_MASK 0xC000
3062
#define CAN2BTR_SJW_MASK C2BTR_SJW_MASK
3063
#define C2BTR_SJW_BIT 14
3064
#define CAN2BTR_SJW_BIT C2BTR_SJW_BIT
3065
#define C2BTR_TSEG1_MASK 0xF0000
3066
#define CAN2BTR_TSEG1_MASK C2BTR_TSEG1_MASK
3067
#define C2BTR_TSEG1_BIT 16
3068
#define CAN2BTR_TSEG1_BIT C2BTR_TSEG1_BIT
3069
#define C2BTR_TSEG2_MASK 0x700000
3070
#define CAN2BTR_TSEG2_MASK C2BTR_TSEG2_MASK
3071
#define C2BTR_TSEG2_BIT 20
3072
#define CAN2BTR_TSEG2_BIT C2BTR_TSEG2_BIT
3073
#define C2BTR_SAM_MASK 0x800000
3074
#define CAN2BTR_SAM_MASK C2BTR_SAM_MASK
3075
#define C2BTR_SAM 0x800000
3076
#define CAN2BTR_SAM C2BTR_SAM
3077
#define C2BTR_SAM_BIT 23
3078
#define CAN2BTR_SAM_BIT C2BTR_SAM_BIT
3079
 
3080
#define C2EWL (*(volatile unsigned long *)0xE0048018)
3081
#define CAN2EWL C2EWL
3082
#define C2EWL_OFFSET 0x18
3083
#define CAN2EWL_OFFSET C2EWL_OFFSET
3084
#define C2EWL_EWL_MASK 0xFF
3085
#define CAN2EWL_EWL_MASK C2EWL_EWL_MASK
3086
#define C2EWL_EWL_BIT 0
3087
#define CAN2EWL_EWL_BIT C2EWL_EWL_BIT
3088
 
3089
#define C2SR (*(volatile unsigned long *)0xE004801C)
3090
#define CAN2SR C2SR
3091
#define C2SR_OFFSET 0x1C
3092
#define CAN2SR_OFFSET C2SR_OFFSET
3093
#define C2SR_RBS_MASK 0x1
3094
#define CAN2SR_RBS_MASK C2SR_RBS_MASK
3095
#define C2SR_RBS 0x1
3096
#define CAN2SR_RBS C2SR_RBS
3097
#define C2SR_RBS_BIT 0
3098
#define CAN2SR_RBS_BIT C2SR_RBS_BIT
3099
#define C2SR_DOS_MASK 0x2
3100
#define CAN2SR_DOS_MASK C2SR_DOS_MASK
3101
#define C2SR_DOS 0x2
3102
#define CAN2SR_DOS C2SR_DOS
3103
#define C2SR_DOS_BIT 1
3104
#define CAN2SR_DOS_BIT C2SR_DOS_BIT
3105
#define C2SR_TBS1_MASK 0x4
3106
#define CAN2SR_TBS1_MASK C2SR_TBS1_MASK
3107
#define C2SR_TBS1 0x4
3108
#define CAN2SR_TBS1 C2SR_TBS1
3109
#define C2SR_TBS1_BIT 2
3110
#define CAN2SR_TBS1_BIT C2SR_TBS1_BIT
3111
#define C2SR_TCS1_MASK 0x8
3112
#define CAN2SR_TCS1_MASK C2SR_TCS1_MASK
3113
#define C2SR_TCS1 0x8
3114
#define CAN2SR_TCS1 C2SR_TCS1
3115
#define C2SR_TCS1_BIT 3
3116
#define CAN2SR_TCS1_BIT C2SR_TCS1_BIT
3117
#define C2SR_RS_MASK 0x10
3118
#define CAN2SR_RS_MASK C2SR_RS_MASK
3119
#define C2SR_RS 0x10
3120
#define CAN2SR_RS C2SR_RS
3121
#define C2SR_RS_BIT 4
3122
#define CAN2SR_RS_BIT C2SR_RS_BIT
3123
#define C2SR_TS1_MASK 0x20
3124
#define CAN2SR_TS1_MASK C2SR_TS1_MASK
3125
#define C2SR_TS1 0x20
3126
#define CAN2SR_TS1 C2SR_TS1
3127
#define C2SR_TS1_BIT 5
3128
#define CAN2SR_TS1_BIT C2SR_TS1_BIT
3129
#define C2SR_ES_MASK 0x40
3130
#define CAN2SR_ES_MASK C2SR_ES_MASK
3131
#define C2SR_ES 0x40
3132
#define CAN2SR_ES C2SR_ES
3133
#define C2SR_ES_BIT 6
3134
#define CAN2SR_ES_BIT C2SR_ES_BIT
3135
#define C2SR_BS_MASK 0x80
3136
#define CAN2SR_BS_MASK C2SR_BS_MASK
3137
#define C2SR_BS 0x80
3138
#define CAN2SR_BS C2SR_BS
3139
#define C2SR_BS_BIT 7
3140
#define CAN2SR_BS_BIT C2SR_BS_BIT
3141
#define C2SR_RBS2_MASK 0x100
3142
#define CAN2SR_RBS2_MASK C2SR_RBS2_MASK
3143
#define C2SR_RBS2 0x100
3144
#define CAN2SR_RBS2 C2SR_RBS2
3145
#define C2SR_RBS2_BIT 8
3146
#define CAN2SR_RBS2_BIT C2SR_RBS2_BIT
3147
#define C2SR_DOS2_MASK 0x200
3148
#define CAN2SR_DOS2_MASK C2SR_DOS2_MASK
3149
#define C2SR_DOS2 0x200
3150
#define CAN2SR_DOS2 C2SR_DOS2
3151
#define C2SR_DOS2_BIT 9
3152
#define CAN2SR_DOS2_BIT C2SR_DOS2_BIT
3153
#define C2SR_TBS2_MASK 0x400
3154
#define CAN2SR_TBS2_MASK C2SR_TBS2_MASK
3155
#define C2SR_TBS2 0x400
3156
#define CAN2SR_TBS2 C2SR_TBS2
3157
#define C2SR_TBS2_BIT 10
3158
#define CAN2SR_TBS2_BIT C2SR_TBS2_BIT
3159
#define C2SR_TCS2_MASK 0x800
3160
#define CAN2SR_TCS2_MASK C2SR_TCS2_MASK
3161
#define C2SR_TCS2 0x800
3162
#define CAN2SR_TCS2 C2SR_TCS2
3163
#define C2SR_TCS2_BIT 11
3164
#define CAN2SR_TCS2_BIT C2SR_TCS2_BIT
3165
#define C2SR_RS2_MASK 0x1000
3166
#define CAN2SR_RS2_MASK C2SR_RS2_MASK
3167
#define C2SR_RS2 0x1000
3168
#define CAN2SR_RS2 C2SR_RS2
3169
#define C2SR_RS2_BIT 12
3170
#define CAN2SR_RS2_BIT C2SR_RS2_BIT
3171
#define C2SR_TS2_MASK 0x2000
3172
#define CAN2SR_TS2_MASK C2SR_TS2_MASK
3173
#define C2SR_TS2 0x2000
3174
#define CAN2SR_TS2 C2SR_TS2
3175
#define C2SR_TS2_BIT 13
3176
#define CAN2SR_TS2_BIT C2SR_TS2_BIT
3177
#define C2SR_ES2_MASK 0x4000
3178
#define CAN2SR_ES2_MASK C2SR_ES2_MASK
3179
#define C2SR_ES2 0x4000
3180
#define CAN2SR_ES2 C2SR_ES2
3181
#define C2SR_ES2_BIT 14
3182
#define CAN2SR_ES2_BIT C2SR_ES2_BIT
3183
#define C2SR_BS2_MASK 0x8000
3184
#define CAN2SR_BS2_MASK C2SR_BS2_MASK
3185
#define C2SR_BS2 0x8000
3186
#define CAN2SR_BS2 C2SR_BS2
3187
#define C2SR_BS2_BIT 15
3188
#define CAN2SR_BS2_BIT C2SR_BS2_BIT
3189
#define C2SR_RBS3_MASK 0x10000
3190
#define CAN2SR_RBS3_MASK C2SR_RBS3_MASK
3191
#define C2SR_RBS3 0x10000
3192
#define CAN2SR_RBS3 C2SR_RBS3
3193
#define C2SR_RBS3_BIT 16
3194
#define CAN2SR_RBS3_BIT C2SR_RBS3_BIT
3195
#define C2SR_DOS3_MASK 0x20000
3196
#define CAN2SR_DOS3_MASK C2SR_DOS3_MASK
3197
#define C2SR_DOS3 0x20000
3198
#define CAN2SR_DOS3 C2SR_DOS3
3199
#define C2SR_DOS3_BIT 17
3200
#define CAN2SR_DOS3_BIT C2SR_DOS3_BIT
3201
#define C2SR_TBS3_MASK 0x40000
3202
#define CAN2SR_TBS3_MASK C2SR_TBS3_MASK
3203
#define C2SR_TBS3 0x40000
3204
#define CAN2SR_TBS3 C2SR_TBS3
3205
#define C2SR_TBS3_BIT 18
3206
#define CAN2SR_TBS3_BIT C2SR_TBS3_BIT
3207
#define C2SR_TCS3_MASK 0x80000
3208
#define CAN2SR_TCS3_MASK C2SR_TCS3_MASK
3209
#define C2SR_TCS3 0x80000
3210
#define CAN2SR_TCS3 C2SR_TCS3
3211
#define C2SR_TCS3_BIT 19
3212
#define CAN2SR_TCS3_BIT C2SR_TCS3_BIT
3213
#define C2SR_RS3_MASK 0x100000
3214
#define CAN2SR_RS3_MASK C2SR_RS3_MASK
3215
#define C2SR_RS3 0x100000
3216
#define CAN2SR_RS3 C2SR_RS3
3217
#define C2SR_RS3_BIT 20
3218
#define CAN2SR_RS3_BIT C2SR_RS3_BIT
3219
#define C2SR_TS3_MASK 0x200000
3220
#define CAN2SR_TS3_MASK C2SR_TS3_MASK
3221
#define C2SR_TS3 0x200000
3222
#define CAN2SR_TS3 C2SR_TS3
3223
#define C2SR_TS3_BIT 21
3224
#define CAN2SR_TS3_BIT C2SR_TS3_BIT
3225
#define C2SR_ES3_MASK 0x400000
3226
#define CAN2SR_ES3_MASK C2SR_ES3_MASK
3227
#define C2SR_ES3 0x400000
3228
#define CAN2SR_ES3 C2SR_ES3
3229
#define C2SR_ES3_BIT 22
3230
#define CAN2SR_ES3_BIT C2SR_ES3_BIT
3231
#define C2SR_BS3_MASK 0x800000
3232
#define CAN2SR_BS3_MASK C2SR_BS3_MASK
3233
#define C2SR_BS3 0x800000
3234
#define CAN2SR_BS3 C2SR_BS3
3235
#define C2SR_BS3_BIT 23
3236
#define CAN2SR_BS3_BIT C2SR_BS3_BIT
3237
 
3238
#define C2RFS (*(volatile unsigned long *)0xE0048020)
3239
#define CAN2RFS C2RFS
3240
#define C2RFS_OFFSET 0x20
3241
#define CAN2RFS_OFFSET C2RFS_OFFSET
3242
#define C2RFS_ID_Index_MASK 0x3FF
3243
#define CAN2RFS_ID_Index_MASK C2RFS_ID_Index_MASK
3244
#define C2RFS_ID_Index_BIT 0
3245
#define CAN2RFS_ID_Index_BIT C2RFS_ID_Index_BIT
3246
#define C2RFS_BP_MASK 0x400
3247
#define CAN2RFS_BP_MASK C2RFS_BP_MASK
3248
#define C2RFS_BP 0x400
3249
#define CAN2RFS_BP C2RFS_BP
3250
#define C2RFS_BP_BIT 10
3251
#define CAN2RFS_BP_BIT C2RFS_BP_BIT
3252
#define C2RFS_DLC_MASK 0xF0000
3253
#define CAN2RFS_DLC_MASK C2RFS_DLC_MASK
3254
#define C2RFS_DLC_BIT 16
3255
#define CAN2RFS_DLC_BIT C2RFS_DLC_BIT
3256
#define C2RFS_RTR_MASK 0x40000000
3257
#define CAN2RFS_RTR_MASK C2RFS_RTR_MASK
3258
#define C2RFS_RTR 0x40000000
3259
#define CAN2RFS_RTR C2RFS_RTR
3260
#define C2RFS_RTR_BIT 30
3261
#define CAN2RFS_RTR_BIT C2RFS_RTR_BIT
3262
#define C2RFS_FF_MASK 0x80000000
3263
#define CAN2RFS_FF_MASK C2RFS_FF_MASK
3264
#define C2RFS_FF 0x80000000
3265
#define CAN2RFS_FF C2RFS_FF
3266
#define C2RFS_FF_BIT 31
3267
#define CAN2RFS_FF_BIT C2RFS_FF_BIT
3268
 
3269
#define C2RID (*(volatile unsigned long *)0xE0048024)
3270
#define CAN2RID C2RID
3271
#define C2RID_OFFSET 0x24
3272
#define CAN2RID_OFFSET C2RID_OFFSET
3273
#define C2RID_ID_MASK 0x7FF
3274
#define CAN2RID_ID_MASK C2RID_ID_MASK
3275
#define C2RID_ID_BIT 0
3276
#define CAN2RID_ID_BIT C2RID_ID_BIT
3277
 
3278
#define C2RDA (*(volatile unsigned long *)0xE0048028)
3279
#define CAN2RDA C2RDA
3280
#define C2RDA_OFFSET 0x28
3281
#define CAN2RDA_OFFSET C2RDA_OFFSET
3282
#define C2RDA_Data_1_MASK 0xFF
3283
#define CAN2RDA_Data_1_MASK C2RDA_Data_1_MASK
3284
#define C2RDA_Data_1_BIT 0
3285
#define CAN2RDA_Data_1_BIT C2RDA_Data_1_BIT
3286
#define C2RDA_Data_2_MASK 0xFF00
3287
#define CAN2RDA_Data_2_MASK C2RDA_Data_2_MASK
3288
#define C2RDA_Data_2_BIT 8
3289
#define CAN2RDA_Data_2_BIT C2RDA_Data_2_BIT
3290
#define C2RDA_Data_3_MASK 0xFF0000
3291
#define CAN2RDA_Data_3_MASK C2RDA_Data_3_MASK
3292
#define C2RDA_Data_3_BIT 16
3293
#define CAN2RDA_Data_3_BIT C2RDA_Data_3_BIT
3294
#define C2RDA_Data_4_MASK 0xFF000000
3295
#define CAN2RDA_Data_4_MASK C2RDA_Data_4_MASK
3296
#define C2RDA_Data_4_BIT 24
3297
#define CAN2RDA_Data_4_BIT C2RDA_Data_4_BIT
3298
 
3299
#define C2RDB (*(volatile unsigned long *)0xE004802C)
3300
#define CAN2RDB C2RDB
3301
#define C2RDB_OFFSET 0x2C
3302
#define CAN2RDB_OFFSET C2RDB_OFFSET
3303
#define C2RDB_Data_5_MASK 0xFF
3304
#define CAN2RDB_Data_5_MASK C2RDB_Data_5_MASK
3305
#define C2RDB_Data_5_BIT 0
3306
#define CAN2RDB_Data_5_BIT C2RDB_Data_5_BIT
3307
#define C2RDB_Data_6_MASK 0xFF00
3308
#define CAN2RDB_Data_6_MASK C2RDB_Data_6_MASK
3309
#define C2RDB_Data_6_BIT 8
3310
#define CAN2RDB_Data_6_BIT C2RDB_Data_6_BIT
3311
#define C2RDB_Data_7_MASK 0xFF0000
3312
#define CAN2RDB_Data_7_MASK C2RDB_Data_7_MASK
3313
#define C2RDB_Data_7_BIT 16
3314
#define CAN2RDB_Data_7_BIT C2RDB_Data_7_BIT
3315
#define C2RDB_Data_8_MASK 0xFF000000
3316
#define CAN2RDB_Data_8_MASK C2RDB_Data_8_MASK
3317
#define C2RDB_Data_8_BIT 24
3318
#define CAN2RDB_Data_8_BIT C2RDB_Data_8_BIT
3319
 
3320
#define C2TFI1 (*(volatile unsigned long *)0xE0048030)
3321
#define CAN2TFI1 C2TFI1
3322
#define C2TFI1_OFFSET 0x30
3323
#define CAN2TFI1_OFFSET C2TFI1_OFFSET
3324
#define C2TFI1_PRIO_MASK 0xFF
3325
#define CAN2TFI1_PRIO_MASK C2TFI1_PRIO_MASK
3326
#define C2TFI1_PRIO_BIT 0
3327
#define CAN2TFI1_PRIO_BIT C2TFI1_PRIO_BIT
3328
#define C2TFI1_DLC_MASK 0xF0000
3329
#define CAN2TFI1_DLC_MASK C2TFI1_DLC_MASK
3330
#define C2TFI1_DLC_BIT 16
3331
#define CAN2TFI1_DLC_BIT C2TFI1_DLC_BIT
3332
#define C2TFI1_RTR_MASK 0x40000000
3333
#define CAN2TFI1_RTR_MASK C2TFI1_RTR_MASK
3334
#define C2TFI1_RTR 0x40000000
3335
#define CAN2TFI1_RTR C2TFI1_RTR
3336
#define C2TFI1_RTR_BIT 30
3337
#define CAN2TFI1_RTR_BIT C2TFI1_RTR_BIT
3338
#define C2TFI1_FF_MASK 0x80000000
3339
#define CAN2TFI1_FF_MASK C2TFI1_FF_MASK
3340
#define C2TFI1_FF 0x80000000
3341
#define CAN2TFI1_FF C2TFI1_FF
3342
#define C2TFI1_FF_BIT 31
3343
#define CAN2TFI1_FF_BIT C2TFI1_FF_BIT
3344
 
3345
#define C2TID1 (*(volatile unsigned long *)0xE0048034)
3346
#define CAN2TID1 C2TID1
3347
#define C2TID1_OFFSET 0x34
3348
#define CAN2TID1_OFFSET C2TID1_OFFSET
3349
#define C2TID1_ID_MASK 0x7FF
3350
#define CAN2TID1_ID_MASK C2TID1_ID_MASK
3351
#define C2TID1_ID_BIT 0
3352
#define CAN2TID1_ID_BIT C2TID1_ID_BIT
3353
 
3354
#define C2TDA1 (*(volatile unsigned long *)0xE0048038)
3355
#define CAN2TDA1 C2TDA1
3356
#define C2TDA1_OFFSET 0x38
3357
#define CAN2TDA1_OFFSET C2TDA1_OFFSET
3358
#define C2TDA1_Data_1_MASK 0xFF
3359
#define CAN2TDA1_Data_1_MASK C2TDA1_Data_1_MASK
3360
#define C2TDA1_Data_1_BIT 0
3361
#define CAN2TDA1_Data_1_BIT C2TDA1_Data_1_BIT
3362
#define C2TDA1_Data_2_MASK 0xFF00
3363
#define CAN2TDA1_Data_2_MASK C2TDA1_Data_2_MASK
3364
#define C2TDA1_Data_2_BIT 8
3365
#define CAN2TDA1_Data_2_BIT C2TDA1_Data_2_BIT
3366
#define C2TDA1_Data_3_MASK 0xFF0000
3367
#define CAN2TDA1_Data_3_MASK C2TDA1_Data_3_MASK
3368
#define C2TDA1_Data_3_BIT 16
3369
#define CAN2TDA1_Data_3_BIT C2TDA1_Data_3_BIT
3370
#define C2TDA1_Data_4_MASK 0xFF000000
3371
#define CAN2TDA1_Data_4_MASK C2TDA1_Data_4_MASK
3372
#define C2TDA1_Data_4_BIT 24
3373
#define CAN2TDA1_Data_4_BIT C2TDA1_Data_4_BIT
3374
 
3375
#define C2TDB1 (*(volatile unsigned long *)0xE004803C)
3376
#define CAN2TDB1 C2TDB1
3377
#define C2TDB1_OFFSET 0x3C
3378
#define CAN2TDB1_OFFSET C2TDB1_OFFSET
3379
#define C2TDB1_Data_5_MASK 0xFF
3380
#define CAN2TDB1_Data_5_MASK C2TDB1_Data_5_MASK
3381
#define C2TDB1_Data_5_BIT 0
3382
#define CAN2TDB1_Data_5_BIT C2TDB1_Data_5_BIT
3383
#define C2TDB1_Data_6_MASK 0xFF00
3384
#define CAN2TDB1_Data_6_MASK C2TDB1_Data_6_MASK
3385
#define C2TDB1_Data_6_BIT 8
3386
#define CAN2TDB1_Data_6_BIT C2TDB1_Data_6_BIT
3387
#define C2TDB1_Data_7_MASK 0xFF0000
3388
#define CAN2TDB1_Data_7_MASK C2TDB1_Data_7_MASK
3389
#define C2TDB1_Data_7_BIT 16
3390
#define CAN2TDB1_Data_7_BIT C2TDB1_Data_7_BIT
3391
#define C2TDB1_Data_8_MASK 0xFF000000
3392
#define CAN2TDB1_Data_8_MASK C2TDB1_Data_8_MASK
3393
#define C2TDB1_Data_8_BIT 24
3394
#define CAN2TDB1_Data_8_BIT C2TDB1_Data_8_BIT
3395
 
3396
#define C2TFI2 (*(volatile unsigned long *)0xE0048040)
3397
#define CAN2TFI2 C2TFI2
3398
#define C2TFI2_OFFSET 0x40
3399
#define CAN2TFI2_OFFSET C2TFI2_OFFSET
3400
#define C2TFI2_PRIO_MASK 0xFF
3401
#define CAN2TFI2_PRIO_MASK C2TFI2_PRIO_MASK
3402
#define C2TFI2_PRIO_BIT 0
3403
#define CAN2TFI2_PRIO_BIT C2TFI2_PRIO_BIT
3404
#define C2TFI2_DLC_MASK 0xF0000
3405
#define CAN2TFI2_DLC_MASK C2TFI2_DLC_MASK
3406
#define C2TFI2_DLC_BIT 16
3407
#define CAN2TFI2_DLC_BIT C2TFI2_DLC_BIT
3408
#define C2TFI2_RTR_MASK 0x40000000
3409
#define CAN2TFI2_RTR_MASK C2TFI2_RTR_MASK
3410
#define C2TFI2_RTR 0x40000000
3411
#define CAN2TFI2_RTR C2TFI2_RTR
3412
#define C2TFI2_RTR_BIT 30
3413
#define CAN2TFI2_RTR_BIT C2TFI2_RTR_BIT
3414
#define C2TFI2_FF_MASK 0x80000000
3415
#define CAN2TFI2_FF_MASK C2TFI2_FF_MASK
3416
#define C2TFI2_FF 0x80000000
3417
#define CAN2TFI2_FF C2TFI2_FF
3418
#define C2TFI2_FF_BIT 31
3419
#define CAN2TFI2_FF_BIT C2TFI2_FF_BIT
3420
 
3421
#define C2TID2 (*(volatile unsigned long *)0xE0048044)
3422
#define CAN2TID2 C2TID2
3423
#define C2TID2_OFFSET 0x44
3424
#define CAN2TID2_OFFSET C2TID2_OFFSET
3425
#define C2TID2_ID_MASK 0x7FF
3426
#define CAN2TID2_ID_MASK C2TID2_ID_MASK
3427
#define C2TID2_ID_BIT 0
3428
#define CAN2TID2_ID_BIT C2TID2_ID_BIT
3429
 
3430
#define C2TDA2 (*(volatile unsigned long *)0xE0048048)
3431
#define CAN2TDA2 C2TDA2
3432
#define C2TDA2_OFFSET 0x48
3433
#define CAN2TDA2_OFFSET C2TDA2_OFFSET
3434
#define C2TDA2_Data_1_MASK 0xFF
3435
#define CAN2TDA2_Data_1_MASK C2TDA2_Data_1_MASK
3436
#define C2TDA2_Data_1_BIT 0
3437
#define CAN2TDA2_Data_1_BIT C2TDA2_Data_1_BIT
3438
#define C2TDA2_Data_2_MASK 0xFF00
3439
#define CAN2TDA2_Data_2_MASK C2TDA2_Data_2_MASK
3440
#define C2TDA2_Data_2_BIT 8
3441
#define CAN2TDA2_Data_2_BIT C2TDA2_Data_2_BIT
3442
#define C2TDA2_Data_3_MASK 0xFF0000
3443
#define CAN2TDA2_Data_3_MASK C2TDA2_Data_3_MASK
3444
#define C2TDA2_Data_3_BIT 16
3445
#define CAN2TDA2_Data_3_BIT C2TDA2_Data_3_BIT
3446
#define C2TDA2_Data_4_MASK 0xFF000000
3447
#define CAN2TDA2_Data_4_MASK C2TDA2_Data_4_MASK
3448
#define C2TDA2_Data_4_BIT 24
3449
#define CAN2TDA2_Data_4_BIT C2TDA2_Data_4_BIT
3450
 
3451
#define C2TDB2 (*(volatile unsigned long *)0xE004804C)
3452
#define CAN2TDB2 C2TDB2
3453
#define C2TDB2_OFFSET 0x4C
3454
#define CAN2TDB2_OFFSET C2TDB2_OFFSET
3455
#define C2TDB2_Data_5_MASK 0xFF
3456
#define CAN2TDB2_Data_5_MASK C2TDB2_Data_5_MASK
3457
#define C2TDB2_Data_5_BIT 0
3458
#define CAN2TDB2_Data_5_BIT C2TDB2_Data_5_BIT
3459
#define C2TDB2_Data_6_MASK 0xFF00
3460
#define CAN2TDB2_Data_6_MASK C2TDB2_Data_6_MASK
3461
#define C2TDB2_Data_6_BIT 8
3462
#define CAN2TDB2_Data_6_BIT C2TDB2_Data_6_BIT
3463
#define C2TDB2_Data_7_MASK 0xFF0000
3464
#define CAN2TDB2_Data_7_MASK C2TDB2_Data_7_MASK
3465
#define C2TDB2_Data_7_BIT 16
3466
#define CAN2TDB2_Data_7_BIT C2TDB2_Data_7_BIT
3467
#define C2TDB2_Data_8_MASK 0xFF000000
3468
#define CAN2TDB2_Data_8_MASK C2TDB2_Data_8_MASK
3469
#define C2TDB2_Data_8_BIT 24
3470
#define CAN2TDB2_Data_8_BIT C2TDB2_Data_8_BIT
3471
 
3472
#define C2TFI3 (*(volatile unsigned long *)0xE0048050)
3473
#define CAN2TFI3 C2TFI3
3474
#define C2TFI3_OFFSET 0x50
3475
#define CAN2TFI3_OFFSET C2TFI3_OFFSET
3476
#define C2TFI3_PRIO_MASK 0xFF
3477
#define CAN2TFI3_PRIO_MASK C2TFI3_PRIO_MASK
3478
#define C2TFI3_PRIO_BIT 0
3479
#define CAN2TFI3_PRIO_BIT C2TFI3_PRIO_BIT
3480
#define C2TFI3_DLC_MASK 0xF0000
3481
#define CAN2TFI3_DLC_MASK C2TFI3_DLC_MASK
3482
#define C2TFI3_DLC_BIT 16
3483
#define CAN2TFI3_DLC_BIT C2TFI3_DLC_BIT
3484
#define C2TFI3_RTR_MASK 0x40000000
3485
#define CAN2TFI3_RTR_MASK C2TFI3_RTR_MASK
3486
#define C2TFI3_RTR 0x40000000
3487
#define CAN2TFI3_RTR C2TFI3_RTR
3488
#define C2TFI3_RTR_BIT 30
3489
#define CAN2TFI3_RTR_BIT C2TFI3_RTR_BIT
3490
#define C2TFI3_FF_MASK 0x80000000
3491
#define CAN2TFI3_FF_MASK C2TFI3_FF_MASK
3492
#define C2TFI3_FF 0x80000000
3493
#define CAN2TFI3_FF C2TFI3_FF
3494
#define C2TFI3_FF_BIT 31
3495
#define CAN2TFI3_FF_BIT C2TFI3_FF_BIT
3496
 
3497
#define C2TID3 (*(volatile unsigned long *)0xE0048054)
3498
#define CAN2TID3 C2TID3
3499
#define C2TID3_OFFSET 0x54
3500
#define CAN2TID3_OFFSET C2TID3_OFFSET
3501
#define C2TID3_ID_MASK 0x7FF
3502
#define CAN2TID3_ID_MASK C2TID3_ID_MASK
3503
#define C2TID3_ID_BIT 0
3504
#define CAN2TID3_ID_BIT C2TID3_ID_BIT
3505
 
3506
#define C2TDA3 (*(volatile unsigned long *)0xE0048058)
3507
#define CAN2TDA3 C2TDA3
3508
#define C2TDA3_OFFSET 0x58
3509
#define CAN2TDA3_OFFSET C2TDA3_OFFSET
3510
#define C2TDA3_Data_1_MASK 0xFF
3511
#define CAN2TDA3_Data_1_MASK C2TDA3_Data_1_MASK
3512
#define C2TDA3_Data_1_BIT 0
3513
#define CAN2TDA3_Data_1_BIT C2TDA3_Data_1_BIT
3514
#define C2TDA3_Data_2_MASK 0xFF00
3515
#define CAN2TDA3_Data_2_MASK C2TDA3_Data_2_MASK
3516
#define C2TDA3_Data_2_BIT 8
3517
#define CAN2TDA3_Data_2_BIT C2TDA3_Data_2_BIT
3518
#define C2TDA3_Data_3_MASK 0xFF0000
3519
#define CAN2TDA3_Data_3_MASK C2TDA3_Data_3_MASK
3520
#define C2TDA3_Data_3_BIT 16
3521
#define CAN2TDA3_Data_3_BIT C2TDA3_Data_3_BIT
3522
#define C2TDA3_Data_4_MASK 0xFF000000
3523
#define CAN2TDA3_Data_4_MASK C2TDA3_Data_4_MASK
3524
#define C2TDA3_Data_4_BIT 24
3525
#define CAN2TDA3_Data_4_BIT C2TDA3_Data_4_BIT
3526
 
3527
#define C2TDB3 (*(volatile unsigned long *)0xE004805C)
3528
#define CAN2TDB3 C2TDB3
3529
#define C2TDB3_OFFSET 0x5C
3530
#define CAN2TDB3_OFFSET C2TDB3_OFFSET
3531
#define C2TDB3_Data_5_MASK 0xFF
3532
#define CAN2TDB3_Data_5_MASK C2TDB3_Data_5_MASK
3533
#define C2TDB3_Data_5_BIT 0
3534
#define CAN2TDB3_Data_5_BIT C2TDB3_Data_5_BIT
3535
#define C2TDB3_Data_6_MASK 0xFF00
3536
#define CAN2TDB3_Data_6_MASK C2TDB3_Data_6_MASK
3537
#define C2TDB3_Data_6_BIT 8
3538
#define CAN2TDB3_Data_6_BIT C2TDB3_Data_6_BIT
3539
#define C2TDB3_Data_7_MASK 0xFF0000
3540
#define CAN2TDB3_Data_7_MASK C2TDB3_Data_7_MASK
3541
#define C2TDB3_Data_7_BIT 16
3542
#define CAN2TDB3_Data_7_BIT C2TDB3_Data_7_BIT
3543
#define C2TDB3_Data_8_MASK 0xFF000000
3544
#define CAN2TDB3_Data_8_MASK C2TDB3_Data_8_MASK
3545
#define C2TDB3_Data_8_BIT 24
3546
#define CAN2TDB3_Data_8_BIT C2TDB3_Data_8_BIT
3547
 
3548
#define CAN3_BASE 0xE004C000
3549
 
3550
#define C3MOD (*(volatile unsigned long *)0xE004C000)
3551
#define CAN3MOD C3MOD
3552
#define C3MOD_OFFSET 0x0
3553
#define CAN3MOD_OFFSET C3MOD_OFFSET
3554
#define C3MOD_RM_MASK 0x1
3555
#define CAN3MOD_RM_MASK C3MOD_RM_MASK
3556
#define C3MOD_RM 0x1
3557
#define CAN3MOD_RM C3MOD_RM
3558
#define C3MOD_RM_BIT 0
3559
#define CAN3MOD_RM_BIT C3MOD_RM_BIT
3560
#define C3MOD_LOM_MASK 0x2
3561
#define CAN3MOD_LOM_MASK C3MOD_LOM_MASK
3562
#define C3MOD_LOM 0x2
3563
#define CAN3MOD_LOM C3MOD_LOM
3564
#define C3MOD_LOM_BIT 1
3565
#define CAN3MOD_LOM_BIT C3MOD_LOM_BIT
3566
#define C3MOD_STM_MASK 0x4
3567
#define CAN3MOD_STM_MASK C3MOD_STM_MASK
3568
#define C3MOD_STM 0x4
3569
#define CAN3MOD_STM C3MOD_STM
3570
#define C3MOD_STM_BIT 2
3571
#define CAN3MOD_STM_BIT C3MOD_STM_BIT
3572
#define C3MOD_TPM_MASK 0x8
3573
#define CAN3MOD_TPM_MASK C3MOD_TPM_MASK
3574
#define C3MOD_TPM 0x8
3575
#define CAN3MOD_TPM C3MOD_TPM
3576
#define C3MOD_TPM_BIT 3
3577
#define CAN3MOD_TPM_BIT C3MOD_TPM_BIT
3578
#define C3MOD_SM_MASK 0x10
3579
#define CAN3MOD_SM_MASK C3MOD_SM_MASK
3580
#define C3MOD_SM 0x10
3581
#define CAN3MOD_SM C3MOD_SM
3582
#define C3MOD_SM_BIT 4
3583
#define CAN3MOD_SM_BIT C3MOD_SM_BIT
3584
#define C3MOD_RPM_MASK 0x20
3585
#define CAN3MOD_RPM_MASK C3MOD_RPM_MASK
3586
#define C3MOD_RPM 0x20
3587
#define CAN3MOD_RPM C3MOD_RPM
3588
#define C3MOD_RPM_BIT 5
3589
#define CAN3MOD_RPM_BIT C3MOD_RPM_BIT
3590
#define C3MOD_TM_MASK 0x80
3591
#define CAN3MOD_TM_MASK C3MOD_TM_MASK
3592
#define C3MOD_TM 0x80
3593
#define CAN3MOD_TM C3MOD_TM
3594
#define C3MOD_TM_BIT 7
3595
#define CAN3MOD_TM_BIT C3MOD_TM_BIT
3596
 
3597
#define C3CMR (*(volatile unsigned long *)0xE004C004)
3598
#define CAN3CMR C3CMR
3599
#define C3CMR_OFFSET 0x4
3600
#define CAN3CMR_OFFSET C3CMR_OFFSET
3601
#define C3CMR_TR_MASK 0x1
3602
#define CAN3CMR_TR_MASK C3CMR_TR_MASK
3603
#define C3CMR_TR 0x1
3604
#define CAN3CMR_TR C3CMR_TR
3605
#define C3CMR_TR_BIT 0
3606
#define CAN3CMR_TR_BIT C3CMR_TR_BIT
3607
#define C3CMR_AT_MASK 0x2
3608
#define CAN3CMR_AT_MASK C3CMR_AT_MASK
3609
#define C3CMR_AT 0x2
3610
#define CAN3CMR_AT C3CMR_AT
3611
#define C3CMR_AT_BIT 1
3612
#define CAN3CMR_AT_BIT C3CMR_AT_BIT
3613
#define C3CMR_RRB_MASK 0x4
3614
#define CAN3CMR_RRB_MASK C3CMR_RRB_MASK
3615
#define C3CMR_RRB 0x4
3616
#define CAN3CMR_RRB C3CMR_RRB
3617
#define C3CMR_RRB_BIT 2
3618
#define CAN3CMR_RRB_BIT C3CMR_RRB_BIT
3619
#define C3CMR_CDO_MASK 0x8
3620
#define CAN3CMR_CDO_MASK C3CMR_CDO_MASK
3621
#define C3CMR_CDO 0x8
3622
#define CAN3CMR_CDO C3CMR_CDO
3623
#define C3CMR_CDO_BIT 3
3624
#define CAN3CMR_CDO_BIT C3CMR_CDO_BIT
3625
#define C3CMR_SRR_MASK 0x10
3626
#define CAN3CMR_SRR_MASK C3CMR_SRR_MASK
3627
#define C3CMR_SRR 0x10
3628
#define CAN3CMR_SRR C3CMR_SRR
3629
#define C3CMR_SRR_BIT 4
3630
#define CAN3CMR_SRR_BIT C3CMR_SRR_BIT
3631
#define C3CMR_STB1_MASK 0x20
3632
#define CAN3CMR_STB1_MASK C3CMR_STB1_MASK
3633
#define C3CMR_STB1 0x20
3634
#define CAN3CMR_STB1 C3CMR_STB1
3635
#define C3CMR_STB1_BIT 5
3636
#define CAN3CMR_STB1_BIT C3CMR_STB1_BIT
3637
#define C3CMR_STB2_MASK 0x40
3638
#define CAN3CMR_STB2_MASK C3CMR_STB2_MASK
3639
#define C3CMR_STB2 0x40
3640
#define CAN3CMR_STB2 C3CMR_STB2
3641
#define C3CMR_STB2_BIT 6
3642
#define CAN3CMR_STB2_BIT C3CMR_STB2_BIT
3643
#define C3CMR_STB3_MASK 0x80
3644
#define CAN3CMR_STB3_MASK C3CMR_STB3_MASK
3645
#define C3CMR_STB3 0x80
3646
#define CAN3CMR_STB3 C3CMR_STB3
3647
#define C3CMR_STB3_BIT 7
3648
#define CAN3CMR_STB3_BIT C3CMR_STB3_BIT
3649
 
3650
#define C3GSR (*(volatile unsigned long *)0xE004C008)
3651
#define CAN3GSR C3GSR
3652
#define C3GSR_OFFSET 0x8
3653
#define CAN3GSR_OFFSET C3GSR_OFFSET
3654
#define C3GSR_RBS_MASK 0x1
3655
#define CAN3GSR_RBS_MASK C3GSR_RBS_MASK
3656
#define C3GSR_RBS 0x1
3657
#define CAN3GSR_RBS C3GSR_RBS
3658
#define C3GSR_RBS_BIT 0
3659
#define CAN3GSR_RBS_BIT C3GSR_RBS_BIT
3660
#define C3GSR_DOS_MASK 0x2
3661
#define CAN3GSR_DOS_MASK C3GSR_DOS_MASK
3662
#define C3GSR_DOS 0x2
3663
#define CAN3GSR_DOS C3GSR_DOS
3664
#define C3GSR_DOS_BIT 1
3665
#define CAN3GSR_DOS_BIT C3GSR_DOS_BIT
3666
#define C3GSR_TBS_MASK 0x4
3667
#define CAN3GSR_TBS_MASK C3GSR_TBS_MASK
3668
#define C3GSR_TBS 0x4
3669
#define CAN3GSR_TBS C3GSR_TBS
3670
#define C3GSR_TBS_BIT 2
3671
#define CAN3GSR_TBS_BIT C3GSR_TBS_BIT
3672
#define C3GSR_TCS_MASK 0x8
3673
#define CAN3GSR_TCS_MASK C3GSR_TCS_MASK
3674
#define C3GSR_TCS 0x8
3675
#define CAN3GSR_TCS C3GSR_TCS
3676
#define C3GSR_TCS_BIT 3
3677
#define CAN3GSR_TCS_BIT C3GSR_TCS_BIT
3678
#define C3GSR_RS_MASK 0x10
3679
#define CAN3GSR_RS_MASK C3GSR_RS_MASK
3680
#define C3GSR_RS 0x10
3681
#define CAN3GSR_RS C3GSR_RS
3682
#define C3GSR_RS_BIT 4
3683
#define CAN3GSR_RS_BIT C3GSR_RS_BIT
3684
#define C3GSR_TS_MASK 0x20
3685
#define CAN3GSR_TS_MASK C3GSR_TS_MASK
3686
#define C3GSR_TS 0x20
3687
#define CAN3GSR_TS C3GSR_TS
3688
#define C3GSR_TS_BIT 5
3689
#define CAN3GSR_TS_BIT C3GSR_TS_BIT
3690
#define C3GSR_ES_MASK 0x40
3691
#define CAN3GSR_ES_MASK C3GSR_ES_MASK
3692
#define C3GSR_ES 0x40
3693
#define CAN3GSR_ES C3GSR_ES
3694
#define C3GSR_ES_BIT 6
3695
#define CAN3GSR_ES_BIT C3GSR_ES_BIT
3696
#define C3GSR_BS_MASK 0x80
3697
#define CAN3GSR_BS_MASK C3GSR_BS_MASK
3698
#define C3GSR_BS 0x80
3699
#define CAN3GSR_BS C3GSR_BS
3700
#define C3GSR_BS_BIT 7
3701
#define CAN3GSR_BS_BIT C3GSR_BS_BIT
3702
#define C3GSR_RXERR_MASK 0xFF0000
3703
#define CAN3GSR_RXERR_MASK C3GSR_RXERR_MASK
3704
#define C3GSR_RXERR_BIT 16
3705
#define CAN3GSR_RXERR_BIT C3GSR_RXERR_BIT
3706
#define C3GSR_TXERR_MASK 0xFF000000
3707
#define CAN3GSR_TXERR_MASK C3GSR_TXERR_MASK
3708
#define C3GSR_TXERR_BIT 24
3709
#define CAN3GSR_TXERR_BIT C3GSR_TXERR_BIT
3710
 
3711
#define C3ICR (*(volatile unsigned long *)0xE004C00C)
3712
#define CAN3ICR C3ICR
3713
#define C3ICR_OFFSET 0xC
3714
#define CAN3ICR_OFFSET C3ICR_OFFSET
3715
#define C3ICR_RI_MASK 0x1
3716
#define CAN3ICR_RI_MASK C3ICR_RI_MASK
3717
#define C3ICR_RI 0x1
3718
#define CAN3ICR_RI C3ICR_RI
3719
#define C3ICR_RI_BIT 0
3720
#define CAN3ICR_RI_BIT C3ICR_RI_BIT
3721
#define C3ICR_TI1_MASK 0x2
3722
#define CAN3ICR_TI1_MASK C3ICR_TI1_MASK
3723
#define C3ICR_TI1 0x2
3724
#define CAN3ICR_TI1 C3ICR_TI1
3725
#define C3ICR_TI1_BIT 1
3726
#define CAN3ICR_TI1_BIT C3ICR_TI1_BIT
3727
#define C3ICR_EI_MASK 0x4
3728
#define CAN3ICR_EI_MASK C3ICR_EI_MASK
3729
#define C3ICR_EI 0x4
3730
#define CAN3ICR_EI C3ICR_EI
3731
#define C3ICR_EI_BIT 2
3732
#define CAN3ICR_EI_BIT C3ICR_EI_BIT
3733
#define C3ICR_DOI_MASK 0x8
3734
#define CAN3ICR_DOI_MASK C3ICR_DOI_MASK
3735
#define C3ICR_DOI 0x8
3736
#define CAN3ICR_DOI C3ICR_DOI
3737
#define C3ICR_DOI_BIT 3
3738
#define CAN3ICR_DOI_BIT C3ICR_DOI_BIT
3739
#define C3ICR_WUI_MASK 0x10
3740
#define CAN3ICR_WUI_MASK C3ICR_WUI_MASK
3741
#define C3ICR_WUI 0x10
3742
#define CAN3ICR_WUI C3ICR_WUI
3743
#define C3ICR_WUI_BIT 4
3744
#define CAN3ICR_WUI_BIT C3ICR_WUI_BIT
3745
#define C3ICR_EPI_MASK 0x20
3746
#define CAN3ICR_EPI_MASK C3ICR_EPI_MASK
3747
#define C3ICR_EPI 0x20
3748
#define CAN3ICR_EPI C3ICR_EPI
3749
#define C3ICR_EPI_BIT 5
3750
#define CAN3ICR_EPI_BIT C3ICR_EPI_BIT
3751
#define C3ICR_ALI_MASK 0x40
3752
#define CAN3ICR_ALI_MASK C3ICR_ALI_MASK
3753
#define C3ICR_ALI 0x40
3754
#define CAN3ICR_ALI C3ICR_ALI
3755
#define C3ICR_ALI_BIT 6
3756
#define CAN3ICR_ALI_BIT C3ICR_ALI_BIT
3757
#define C3ICR_BEI_MASK 0x80
3758
#define CAN3ICR_BEI_MASK C3ICR_BEI_MASK
3759
#define C3ICR_BEI 0x80
3760
#define CAN3ICR_BEI C3ICR_BEI
3761
#define C3ICR_BEI_BIT 7
3762
#define CAN3ICR_BEI_BIT C3ICR_BEI_BIT
3763
#define C3ICR_IDI_MASK 0x100
3764
#define CAN3ICR_IDI_MASK C3ICR_IDI_MASK
3765
#define C3ICR_IDI 0x100
3766
#define CAN3ICR_IDI C3ICR_IDI
3767
#define C3ICR_IDI_BIT 8
3768
#define CAN3ICR_IDI_BIT C3ICR_IDI_BIT
3769
#define C3ICR_TI2_MASK 0x200
3770
#define CAN3ICR_TI2_MASK C3ICR_TI2_MASK
3771
#define C3ICR_TI2 0x200
3772
#define CAN3ICR_TI2 C3ICR_TI2
3773
#define C3ICR_TI2_BIT 9
3774
#define CAN3ICR_TI2_BIT C3ICR_TI2_BIT
3775
#define C3ICR_TI3_MASK 0x400
3776
#define CAN3ICR_TI3_MASK C3ICR_TI3_MASK
3777
#define C3ICR_TI3 0x400
3778
#define CAN3ICR_TI3 C3ICR_TI3
3779
#define C3ICR_TI3_BIT 10
3780
#define CAN3ICR_TI3_BIT C3ICR_TI3_BIT
3781
#define C3ICR_ERRBIT_MASK 0x1F0000
3782
#define CAN3ICR_ERRBIT_MASK C3ICR_ERRBIT_MASK
3783
#define C3ICR_ERRBIT_BIT 16
3784
#define CAN3ICR_ERRBIT_BIT C3ICR_ERRBIT_BIT
3785
#define C3ICR_ERRDIR_MASK 0x200000
3786
#define CAN3ICR_ERRDIR_MASK C3ICR_ERRDIR_MASK
3787
#define C3ICR_ERRDIR 0x200000
3788
#define CAN3ICR_ERRDIR C3ICR_ERRDIR
3789
#define C3ICR_ERRDIR_BIT 21
3790
#define CAN3ICR_ERRDIR_BIT C3ICR_ERRDIR_BIT
3791
#define C3ICR_ERRC_MASK 0xC00000
3792
#define CAN3ICR_ERRC_MASK C3ICR_ERRC_MASK
3793
#define C3ICR_ERRC_BIT 22
3794
#define CAN3ICR_ERRC_BIT C3ICR_ERRC_BIT
3795
#define C3ICR_ALCBIT_MASK 0x1F000000
3796
#define CAN3ICR_ALCBIT_MASK C3ICR_ALCBIT_MASK
3797
#define C3ICR_ALCBIT_BIT 24
3798
#define CAN3ICR_ALCBIT_BIT C3ICR_ALCBIT_BIT
3799
 
3800
#define C3IER (*(volatile unsigned long *)0xE004C010)
3801
#define CAN3IER C3IER
3802
#define C3IER_OFFSET 0x10
3803
#define CAN3IER_OFFSET C3IER_OFFSET
3804
#define C3IER_RIE_MASK 0x1
3805
#define CAN3IER_RIE_MASK C3IER_RIE_MASK
3806
#define C3IER_RIE 0x1
3807
#define CAN3IER_RIE C3IER_RIE
3808
#define C3IER_RIE_BIT 0
3809
#define CAN3IER_RIE_BIT C3IER_RIE_BIT
3810
#define C3IER_TIE1_MASK 0x2
3811
#define CAN3IER_TIE1_MASK C3IER_TIE1_MASK
3812
#define C3IER_TIE1 0x2
3813
#define CAN3IER_TIE1 C3IER_TIE1
3814
#define C3IER_TIE1_BIT 1
3815
#define CAN3IER_TIE1_BIT C3IER_TIE1_BIT
3816
#define C3IER_EIE_MASK 0x4
3817
#define CAN3IER_EIE_MASK C3IER_EIE_MASK
3818
#define C3IER_EIE 0x4
3819
#define CAN3IER_EIE C3IER_EIE
3820
#define C3IER_EIE_BIT 2
3821
#define CAN3IER_EIE_BIT C3IER_EIE_BIT
3822
#define C3IER_DOIE_MASK 0x8
3823
#define CAN3IER_DOIE_MASK C3IER_DOIE_MASK
3824
#define C3IER_DOIE 0x8
3825
#define CAN3IER_DOIE C3IER_DOIE
3826
#define C3IER_DOIE_BIT 3
3827
#define CAN3IER_DOIE_BIT C3IER_DOIE_BIT
3828
#define C3IER_WUIE_MASK 0x10
3829
#define CAN3IER_WUIE_MASK C3IER_WUIE_MASK
3830
#define C3IER_WUIE 0x10
3831
#define CAN3IER_WUIE C3IER_WUIE
3832
#define C3IER_WUIE_BIT 4
3833
#define CAN3IER_WUIE_BIT C3IER_WUIE_BIT
3834
#define C3IER_EPIE_MASK 0x20
3835
#define CAN3IER_EPIE_MASK C3IER_EPIE_MASK
3836
#define C3IER_EPIE 0x20
3837
#define CAN3IER_EPIE C3IER_EPIE
3838
#define C3IER_EPIE_BIT 5
3839
#define CAN3IER_EPIE_BIT C3IER_EPIE_BIT
3840
#define C3IER_ALIE_MASK 0x40
3841
#define CAN3IER_ALIE_MASK C3IER_ALIE_MASK
3842
#define C3IER_ALIE 0x40
3843
#define CAN3IER_ALIE C3IER_ALIE
3844
#define C3IER_ALIE_BIT 6
3845
#define CAN3IER_ALIE_BIT C3IER_ALIE_BIT
3846
#define C3IER_BEIE_MASK 0x80
3847
#define CAN3IER_BEIE_MASK C3IER_BEIE_MASK
3848
#define C3IER_BEIE 0x80
3849
#define CAN3IER_BEIE C3IER_BEIE
3850
#define C3IER_BEIE_BIT 7
3851
#define CAN3IER_BEIE_BIT C3IER_BEIE_BIT
3852
#define C3IER_IDIE_MASK 0x100
3853
#define CAN3IER_IDIE_MASK C3IER_IDIE_MASK
3854
#define C3IER_IDIE 0x100
3855
#define CAN3IER_IDIE C3IER_IDIE
3856
#define C3IER_IDIE_BIT 8
3857
#define CAN3IER_IDIE_BIT C3IER_IDIE_BIT
3858
#define C3IER_TIE2_MASK 0x200
3859
#define CAN3IER_TIE2_MASK C3IER_TIE2_MASK
3860
#define C3IER_TIE2 0x200
3861
#define CAN3IER_TIE2 C3IER_TIE2
3862
#define C3IER_TIE2_BIT 9
3863
#define CAN3IER_TIE2_BIT C3IER_TIE2_BIT
3864
#define C3IER_TIE3_MASK 0x400
3865
#define CAN3IER_TIE3_MASK C3IER_TIE3_MASK
3866
#define C3IER_TIE3 0x400
3867
#define CAN3IER_TIE3 C3IER_TIE3
3868
#define C3IER_TIE3_BIT 10
3869
#define CAN3IER_TIE3_BIT C3IER_TIE3_BIT
3870
 
3871
#define C3BTR (*(volatile unsigned long *)0xE004C014)
3872
#define CAN3BTR C3BTR
3873
#define C3BTR_OFFSET 0x14
3874
#define CAN3BTR_OFFSET C3BTR_OFFSET
3875
#define C3BTR_BRP_MASK 0x3FF
3876
#define CAN3BTR_BRP_MASK C3BTR_BRP_MASK
3877
#define C3BTR_BRP_BIT 0
3878
#define CAN3BTR_BRP_BIT C3BTR_BRP_BIT
3879
#define C3BTR_SJW_MASK 0xC000
3880
#define CAN3BTR_SJW_MASK C3BTR_SJW_MASK
3881
#define C3BTR_SJW_BIT 14
3882
#define CAN3BTR_SJW_BIT C3BTR_SJW_BIT
3883
#define C3BTR_TSEG1_MASK 0xF0000
3884
#define CAN3BTR_TSEG1_MASK C3BTR_TSEG1_MASK
3885
#define C3BTR_TSEG1_BIT 16
3886
#define CAN3BTR_TSEG1_BIT C3BTR_TSEG1_BIT
3887
#define C3BTR_TSEG2_MASK 0x700000
3888
#define CAN3BTR_TSEG2_MASK C3BTR_TSEG2_MASK
3889
#define C3BTR_TSEG2_BIT 20
3890
#define CAN3BTR_TSEG2_BIT C3BTR_TSEG2_BIT
3891
#define C3BTR_SAM_MASK 0x800000
3892
#define CAN3BTR_SAM_MASK C3BTR_SAM_MASK
3893
#define C3BTR_SAM 0x800000
3894
#define CAN3BTR_SAM C3BTR_SAM
3895
#define C3BTR_SAM_BIT 23
3896
#define CAN3BTR_SAM_BIT C3BTR_SAM_BIT
3897
 
3898
#define C3EWL (*(volatile unsigned long *)0xE004C018)
3899
#define CAN3EWL C3EWL
3900
#define C3EWL_OFFSET 0x18
3901
#define CAN3EWL_OFFSET C3EWL_OFFSET
3902
#define C3EWL_EWL_MASK 0xFF
3903
#define CAN3EWL_EWL_MASK C3EWL_EWL_MASK
3904
#define C3EWL_EWL_BIT 0
3905
#define CAN3EWL_EWL_BIT C3EWL_EWL_BIT
3906
 
3907
#define C3SR (*(volatile unsigned long *)0xE004C01C)
3908
#define CAN3SR C3SR
3909
#define C3SR_OFFSET 0x1C
3910
#define CAN3SR_OFFSET C3SR_OFFSET
3911
#define C3SR_RBS_MASK 0x1
3912
#define CAN3SR_RBS_MASK C3SR_RBS_MASK
3913
#define C3SR_RBS 0x1
3914
#define CAN3SR_RBS C3SR_RBS
3915
#define C3SR_RBS_BIT 0
3916
#define CAN3SR_RBS_BIT C3SR_RBS_BIT
3917
#define C3SR_DOS_MASK 0x2
3918
#define CAN3SR_DOS_MASK C3SR_DOS_MASK
3919
#define C3SR_DOS 0x2
3920
#define CAN3SR_DOS C3SR_DOS
3921
#define C3SR_DOS_BIT 1
3922
#define CAN3SR_DOS_BIT C3SR_DOS_BIT
3923
#define C3SR_TBS1_MASK 0x4
3924
#define CAN3SR_TBS1_MASK C3SR_TBS1_MASK
3925
#define C3SR_TBS1 0x4
3926
#define CAN3SR_TBS1 C3SR_TBS1
3927
#define C3SR_TBS1_BIT 2
3928
#define CAN3SR_TBS1_BIT C3SR_TBS1_BIT
3929
#define C3SR_TCS1_MASK 0x8
3930
#define CAN3SR_TCS1_MASK C3SR_TCS1_MASK
3931
#define C3SR_TCS1 0x8
3932
#define CAN3SR_TCS1 C3SR_TCS1
3933
#define C3SR_TCS1_BIT 3
3934
#define CAN3SR_TCS1_BIT C3SR_TCS1_BIT
3935
#define C3SR_RS_MASK 0x10
3936
#define CAN3SR_RS_MASK C3SR_RS_MASK
3937
#define C3SR_RS 0x10
3938
#define CAN3SR_RS C3SR_RS
3939
#define C3SR_RS_BIT 4
3940
#define CAN3SR_RS_BIT C3SR_RS_BIT
3941
#define C3SR_TS1_MASK 0x20
3942
#define CAN3SR_TS1_MASK C3SR_TS1_MASK
3943
#define C3SR_TS1 0x20
3944
#define CAN3SR_TS1 C3SR_TS1
3945
#define C3SR_TS1_BIT 5
3946
#define CAN3SR_TS1_BIT C3SR_TS1_BIT
3947
#define C3SR_ES_MASK 0x40
3948
#define CAN3SR_ES_MASK C3SR_ES_MASK
3949
#define C3SR_ES 0x40
3950
#define CAN3SR_ES C3SR_ES
3951
#define C3SR_ES_BIT 6
3952
#define CAN3SR_ES_BIT C3SR_ES_BIT
3953
#define C3SR_BS_MASK 0x80
3954
#define CAN3SR_BS_MASK C3SR_BS_MASK
3955
#define C3SR_BS 0x80
3956
#define CAN3SR_BS C3SR_BS
3957
#define C3SR_BS_BIT 7
3958
#define CAN3SR_BS_BIT C3SR_BS_BIT
3959
#define C3SR_RBS2_MASK 0x100
3960
#define CAN3SR_RBS2_MASK C3SR_RBS2_MASK
3961
#define C3SR_RBS2 0x100
3962
#define CAN3SR_RBS2 C3SR_RBS2
3963
#define C3SR_RBS2_BIT 8
3964
#define CAN3SR_RBS2_BIT C3SR_RBS2_BIT
3965
#define C3SR_DOS2_MASK 0x200
3966
#define CAN3SR_DOS2_MASK C3SR_DOS2_MASK
3967
#define C3SR_DOS2 0x200
3968
#define CAN3SR_DOS2 C3SR_DOS2
3969
#define C3SR_DOS2_BIT 9
3970
#define CAN3SR_DOS2_BIT C3SR_DOS2_BIT
3971
#define C3SR_TBS2_MASK 0x400
3972
#define CAN3SR_TBS2_MASK C3SR_TBS2_MASK
3973
#define C3SR_TBS2 0x400
3974
#define CAN3SR_TBS2 C3SR_TBS2
3975
#define C3SR_TBS2_BIT 10
3976
#define CAN3SR_TBS2_BIT C3SR_TBS2_BIT
3977
#define C3SR_TCS2_MASK 0x800
3978
#define CAN3SR_TCS2_MASK C3SR_TCS2_MASK
3979
#define C3SR_TCS2 0x800
3980
#define CAN3SR_TCS2 C3SR_TCS2
3981
#define C3SR_TCS2_BIT 11
3982
#define CAN3SR_TCS2_BIT C3SR_TCS2_BIT
3983
#define C3SR_RS2_MASK 0x1000
3984
#define CAN3SR_RS2_MASK C3SR_RS2_MASK
3985
#define C3SR_RS2 0x1000
3986
#define CAN3SR_RS2 C3SR_RS2
3987
#define C3SR_RS2_BIT 12
3988
#define CAN3SR_RS2_BIT C3SR_RS2_BIT
3989
#define C3SR_TS2_MASK 0x2000
3990
#define CAN3SR_TS2_MASK C3SR_TS2_MASK
3991
#define C3SR_TS2 0x2000
3992
#define CAN3SR_TS2 C3SR_TS2
3993
#define C3SR_TS2_BIT 13
3994
#define CAN3SR_TS2_BIT C3SR_TS2_BIT
3995
#define C3SR_ES2_MASK 0x4000
3996
#define CAN3SR_ES2_MASK C3SR_ES2_MASK
3997
#define C3SR_ES2 0x4000
3998
#define CAN3SR_ES2 C3SR_ES2
3999
#define C3SR_ES2_BIT 14
4000
#define CAN3SR_ES2_BIT C3SR_ES2_BIT
4001
#define C3SR_BS2_MASK 0x8000
4002
#define CAN3SR_BS2_MASK C3SR_BS2_MASK
4003
#define C3SR_BS2 0x8000
4004
#define CAN3SR_BS2 C3SR_BS2
4005
#define C3SR_BS2_BIT 15
4006
#define CAN3SR_BS2_BIT C3SR_BS2_BIT
4007
#define C3SR_RBS3_MASK 0x10000
4008
#define CAN3SR_RBS3_MASK C3SR_RBS3_MASK
4009
#define C3SR_RBS3 0x10000
4010
#define CAN3SR_RBS3 C3SR_RBS3
4011
#define C3SR_RBS3_BIT 16
4012
#define CAN3SR_RBS3_BIT C3SR_RBS3_BIT
4013
#define C3SR_DOS3_MASK 0x20000
4014
#define CAN3SR_DOS3_MASK C3SR_DOS3_MASK
4015
#define C3SR_DOS3 0x20000
4016
#define CAN3SR_DOS3 C3SR_DOS3
4017
#define C3SR_DOS3_BIT 17
4018
#define CAN3SR_DOS3_BIT C3SR_DOS3_BIT
4019
#define C3SR_TBS3_MASK 0x40000
4020
#define CAN3SR_TBS3_MASK C3SR_TBS3_MASK
4021
#define C3SR_TBS3 0x40000
4022
#define CAN3SR_TBS3 C3SR_TBS3
4023
#define C3SR_TBS3_BIT 18
4024
#define CAN3SR_TBS3_BIT C3SR_TBS3_BIT
4025
#define C3SR_TCS3_MASK 0x80000
4026
#define CAN3SR_TCS3_MASK C3SR_TCS3_MASK
4027
#define C3SR_TCS3 0x80000
4028
#define CAN3SR_TCS3 C3SR_TCS3
4029
#define C3SR_TCS3_BIT 19
4030
#define CAN3SR_TCS3_BIT C3SR_TCS3_BIT
4031
#define C3SR_RS3_MASK 0x100000
4032
#define CAN3SR_RS3_MASK C3SR_RS3_MASK
4033
#define C3SR_RS3 0x100000
4034
#define CAN3SR_RS3 C3SR_RS3
4035
#define C3SR_RS3_BIT 20
4036
#define CAN3SR_RS3_BIT C3SR_RS3_BIT
4037
#define C3SR_TS3_MASK 0x200000
4038
#define CAN3SR_TS3_MASK C3SR_TS3_MASK
4039
#define C3SR_TS3 0x200000
4040
#define CAN3SR_TS3 C3SR_TS3
4041
#define C3SR_TS3_BIT 21
4042
#define CAN3SR_TS3_BIT C3SR_TS3_BIT
4043
#define C3SR_ES3_MASK 0x400000
4044
#define CAN3SR_ES3_MASK C3SR_ES3_MASK
4045
#define C3SR_ES3 0x400000
4046
#define CAN3SR_ES3 C3SR_ES3
4047
#define C3SR_ES3_BIT 22
4048
#define CAN3SR_ES3_BIT C3SR_ES3_BIT
4049
#define C3SR_BS3_MASK 0x800000
4050
#define CAN3SR_BS3_MASK C3SR_BS3_MASK
4051
#define C3SR_BS3 0x800000
4052
#define CAN3SR_BS3 C3SR_BS3
4053
#define C3SR_BS3_BIT 23
4054
#define CAN3SR_BS3_BIT C3SR_BS3_BIT
4055
 
4056
#define C3RFS (*(volatile unsigned long *)0xE004C020)
4057
#define CAN3RFS C3RFS
4058
#define C3RFS_OFFSET 0x20
4059
#define CAN3RFS_OFFSET C3RFS_OFFSET
4060
#define C3RFS_ID_Index_MASK 0x3FF
4061
#define CAN3RFS_ID_Index_MASK C3RFS_ID_Index_MASK
4062
#define C3RFS_ID_Index_BIT 0
4063
#define CAN3RFS_ID_Index_BIT C3RFS_ID_Index_BIT
4064
#define C3RFS_BP_MASK 0x400
4065
#define CAN3RFS_BP_MASK C3RFS_BP_MASK
4066
#define C3RFS_BP 0x400
4067
#define CAN3RFS_BP C3RFS_BP
4068
#define C3RFS_BP_BIT 10
4069
#define CAN3RFS_BP_BIT C3RFS_BP_BIT
4070
#define C3RFS_DLC_MASK 0xF0000
4071
#define CAN3RFS_DLC_MASK C3RFS_DLC_MASK
4072
#define C3RFS_DLC_BIT 16
4073
#define CAN3RFS_DLC_BIT C3RFS_DLC_BIT
4074
#define C3RFS_RTR_MASK 0x40000000
4075
#define CAN3RFS_RTR_MASK C3RFS_RTR_MASK
4076
#define C3RFS_RTR 0x40000000
4077
#define CAN3RFS_RTR C3RFS_RTR
4078
#define C3RFS_RTR_BIT 30
4079
#define CAN3RFS_RTR_BIT C3RFS_RTR_BIT
4080
#define C3RFS_FF_MASK 0x80000000
4081
#define CAN3RFS_FF_MASK C3RFS_FF_MASK
4082
#define C3RFS_FF 0x80000000
4083
#define CAN3RFS_FF C3RFS_FF
4084
#define C3RFS_FF_BIT 31
4085
#define CAN3RFS_FF_BIT C3RFS_FF_BIT
4086
 
4087
#define C3RID (*(volatile unsigned long *)0xE004C024)
4088
#define CAN3RID C3RID
4089
#define C3RID_OFFSET 0x24
4090
#define CAN3RID_OFFSET C3RID_OFFSET
4091
#define C3RID_ID_MASK 0x7FF
4092
#define CAN3RID_ID_MASK C3RID_ID_MASK
4093
#define C3RID_ID_BIT 0
4094
#define CAN3RID_ID_BIT C3RID_ID_BIT
4095
 
4096
#define C3RDA (*(volatile unsigned long *)0xE004C028)
4097
#define CAN3RDA C3RDA
4098
#define C3RDA_OFFSET 0x28
4099
#define CAN3RDA_OFFSET C3RDA_OFFSET
4100
#define C3RDA_Data_1_MASK 0xFF
4101
#define CAN3RDA_Data_1_MASK C3RDA_Data_1_MASK
4102
#define C3RDA_Data_1_BIT 0
4103
#define CAN3RDA_Data_1_BIT C3RDA_Data_1_BIT
4104
#define C3RDA_Data_2_MASK 0xFF00
4105
#define CAN3RDA_Data_2_MASK C3RDA_Data_2_MASK
4106
#define C3RDA_Data_2_BIT 8
4107
#define CAN3RDA_Data_2_BIT C3RDA_Data_2_BIT
4108
#define C3RDA_Data_3_MASK 0xFF0000
4109
#define CAN3RDA_Data_3_MASK C3RDA_Data_3_MASK
4110
#define C3RDA_Data_3_BIT 16
4111
#define CAN3RDA_Data_3_BIT C3RDA_Data_3_BIT
4112
#define C3RDA_Data_4_MASK 0xFF000000
4113
#define CAN3RDA_Data_4_MASK C3RDA_Data_4_MASK
4114
#define C3RDA_Data_4_BIT 24
4115
#define CAN3RDA_Data_4_BIT C3RDA_Data_4_BIT
4116
 
4117
#define C3RDB (*(volatile unsigned long *)0xE004C02C)
4118
#define CAN3RDB C3RDB
4119
#define C3RDB_OFFSET 0x2C
4120
#define CAN3RDB_OFFSET C3RDB_OFFSET
4121
#define C3RDB_Data_5_MASK 0xFF
4122
#define CAN3RDB_Data_5_MASK C3RDB_Data_5_MASK
4123
#define C3RDB_Data_5_BIT 0
4124
#define CAN3RDB_Data_5_BIT C3RDB_Data_5_BIT
4125
#define C3RDB_Data_6_MASK 0xFF00
4126
#define CAN3RDB_Data_6_MASK C3RDB_Data_6_MASK
4127
#define C3RDB_Data_6_BIT 8
4128
#define CAN3RDB_Data_6_BIT C3RDB_Data_6_BIT
4129
#define C3RDB_Data_7_MASK 0xFF0000
4130
#define CAN3RDB_Data_7_MASK C3RDB_Data_7_MASK
4131
#define C3RDB_Data_7_BIT 16
4132
#define CAN3RDB_Data_7_BIT C3RDB_Data_7_BIT
4133
#define C3RDB_Data_8_MASK 0xFF000000
4134
#define CAN3RDB_Data_8_MASK C3RDB_Data_8_MASK
4135
#define C3RDB_Data_8_BIT 24
4136
#define CAN3RDB_Data_8_BIT C3RDB_Data_8_BIT
4137
 
4138
#define C3TFI1 (*(volatile unsigned long *)0xE004C030)
4139
#define CAN3TFI1 C3TFI1
4140
#define C3TFI1_OFFSET 0x30
4141
#define CAN3TFI1_OFFSET C3TFI1_OFFSET
4142
#define C3TFI1_PRIO_MASK 0xFF
4143
#define CAN3TFI1_PRIO_MASK C3TFI1_PRIO_MASK
4144
#define C3TFI1_PRIO_BIT 0
4145
#define CAN3TFI1_PRIO_BIT C3TFI1_PRIO_BIT
4146
#define C3TFI1_DLC_MASK 0xF0000
4147
#define CAN3TFI1_DLC_MASK C3TFI1_DLC_MASK
4148
#define C3TFI1_DLC_BIT 16
4149
#define CAN3TFI1_DLC_BIT C3TFI1_DLC_BIT
4150
#define C3TFI1_RTR_MASK 0x40000000
4151
#define CAN3TFI1_RTR_MASK C3TFI1_RTR_MASK
4152
#define C3TFI1_RTR 0x40000000
4153
#define CAN3TFI1_RTR C3TFI1_RTR
4154
#define C3TFI1_RTR_BIT 30
4155
#define CAN3TFI1_RTR_BIT C3TFI1_RTR_BIT
4156
#define C3TFI1_FF_MASK 0x80000000
4157
#define CAN3TFI1_FF_MASK C3TFI1_FF_MASK
4158
#define C3TFI1_FF 0x80000000
4159
#define CAN3TFI1_FF C3TFI1_FF
4160
#define C3TFI1_FF_BIT 31
4161
#define CAN3TFI1_FF_BIT C3TFI1_FF_BIT
4162
 
4163
#define C3TID1 (*(volatile unsigned long *)0xE004C034)
4164
#define CAN3TID1 C3TID1
4165
#define C3TID1_OFFSET 0x34
4166
#define CAN3TID1_OFFSET C3TID1_OFFSET
4167
#define C3TID1_ID_MASK 0x7FF
4168
#define CAN3TID1_ID_MASK C3TID1_ID_MASK
4169
#define C3TID1_ID_BIT 0
4170
#define CAN3TID1_ID_BIT C3TID1_ID_BIT
4171
 
4172
#define C3TDA1 (*(volatile unsigned long *)0xE004C038)
4173
#define CAN3TDA1 C3TDA1
4174
#define C3TDA1_OFFSET 0x38
4175
#define CAN3TDA1_OFFSET C3TDA1_OFFSET
4176
#define C3TDA1_Data_1_MASK 0xFF
4177
#define CAN3TDA1_Data_1_MASK C3TDA1_Data_1_MASK
4178
#define C3TDA1_Data_1_BIT 0
4179
#define CAN3TDA1_Data_1_BIT C3TDA1_Data_1_BIT
4180
#define C3TDA1_Data_2_MASK 0xFF00
4181
#define CAN3TDA1_Data_2_MASK C3TDA1_Data_2_MASK
4182
#define C3TDA1_Data_2_BIT 8
4183
#define CAN3TDA1_Data_2_BIT C3TDA1_Data_2_BIT
4184
#define C3TDA1_Data_3_MASK 0xFF0000
4185
#define CAN3TDA1_Data_3_MASK C3TDA1_Data_3_MASK
4186
#define C3TDA1_Data_3_BIT 16
4187
#define CAN3TDA1_Data_3_BIT C3TDA1_Data_3_BIT
4188
#define C3TDA1_Data_4_MASK 0xFF000000
4189
#define CAN3TDA1_Data_4_MASK C3TDA1_Data_4_MASK
4190
#define C3TDA1_Data_4_BIT 24
4191
#define CAN3TDA1_Data_4_BIT C3TDA1_Data_4_BIT
4192
 
4193
#define C3TDB1 (*(volatile unsigned long *)0xE004C03C)
4194
#define CAN3TDB1 C3TDB1
4195
#define C3TDB1_OFFSET 0x3C
4196
#define CAN3TDB1_OFFSET C3TDB1_OFFSET
4197
#define C3TDB1_Data_5_MASK 0xFF
4198
#define CAN3TDB1_Data_5_MASK C3TDB1_Data_5_MASK
4199
#define C3TDB1_Data_5_BIT 0
4200
#define CAN3TDB1_Data_5_BIT C3TDB1_Data_5_BIT
4201
#define C3TDB1_Data_6_MASK 0xFF00
4202
#define CAN3TDB1_Data_6_MASK C3TDB1_Data_6_MASK
4203
#define C3TDB1_Data_6_BIT 8
4204
#define CAN3TDB1_Data_6_BIT C3TDB1_Data_6_BIT
4205
#define C3TDB1_Data_7_MASK 0xFF0000
4206
#define CAN3TDB1_Data_7_MASK C3TDB1_Data_7_MASK
4207
#define C3TDB1_Data_7_BIT 16
4208
#define CAN3TDB1_Data_7_BIT C3TDB1_Data_7_BIT
4209
#define C3TDB1_Data_8_MASK 0xFF000000
4210
#define CAN3TDB1_Data_8_MASK C3TDB1_Data_8_MASK
4211
#define C3TDB1_Data_8_BIT 24
4212
#define CAN3TDB1_Data_8_BIT C3TDB1_Data_8_BIT
4213
 
4214
#define C3TFI2 (*(volatile unsigned long *)0xE004C040)
4215
#define CAN3TFI2 C3TFI2
4216
#define C3TFI2_OFFSET 0x40
4217
#define CAN3TFI2_OFFSET C3TFI2_OFFSET
4218
#define C3TFI2_PRIO_MASK 0xFF
4219
#define CAN3TFI2_PRIO_MASK C3TFI2_PRIO_MASK
4220
#define C3TFI2_PRIO_BIT 0
4221
#define CAN3TFI2_PRIO_BIT C3TFI2_PRIO_BIT
4222
#define C3TFI2_DLC_MASK 0xF0000
4223
#define CAN3TFI2_DLC_MASK C3TFI2_DLC_MASK
4224
#define C3TFI2_DLC_BIT 16
4225
#define CAN3TFI2_DLC_BIT C3TFI2_DLC_BIT
4226
#define C3TFI2_RTR_MASK 0x40000000
4227
#define CAN3TFI2_RTR_MASK C3TFI2_RTR_MASK
4228
#define C3TFI2_RTR 0x40000000
4229
#define CAN3TFI2_RTR C3TFI2_RTR
4230
#define C3TFI2_RTR_BIT 30
4231
#define CAN3TFI2_RTR_BIT C3TFI2_RTR_BIT
4232
#define C3TFI2_FF_MASK 0x80000000
4233
#define CAN3TFI2_FF_MASK C3TFI2_FF_MASK
4234
#define C3TFI2_FF 0x80000000
4235
#define CAN3TFI2_FF C3TFI2_FF
4236
#define C3TFI2_FF_BIT 31
4237
#define CAN3TFI2_FF_BIT C3TFI2_FF_BIT
4238
 
4239
#define C3TID2 (*(volatile unsigned long *)0xE004C044)
4240
#define CAN3TID2 C3TID2
4241
#define C3TID2_OFFSET 0x44
4242
#define CAN3TID2_OFFSET C3TID2_OFFSET
4243
#define C3TID2_ID_MASK 0x7FF
4244
#define CAN3TID2_ID_MASK C3TID2_ID_MASK
4245
#define C3TID2_ID_BIT 0
4246
#define CAN3TID2_ID_BIT C3TID2_ID_BIT
4247
 
4248
#define C3TDA2 (*(volatile unsigned long *)0xE004C048)
4249
#define CAN3TDA2 C3TDA2
4250
#define C3TDA2_OFFSET 0x48
4251
#define CAN3TDA2_OFFSET C3TDA2_OFFSET
4252
#define C3TDA2_Data_1_MASK 0xFF
4253
#define CAN3TDA2_Data_1_MASK C3TDA2_Data_1_MASK
4254
#define C3TDA2_Data_1_BIT 0
4255
#define CAN3TDA2_Data_1_BIT C3TDA2_Data_1_BIT
4256
#define C3TDA2_Data_2_MASK 0xFF00
4257
#define CAN3TDA2_Data_2_MASK C3TDA2_Data_2_MASK
4258
#define C3TDA2_Data_2_BIT 8
4259
#define CAN3TDA2_Data_2_BIT C3TDA2_Data_2_BIT
4260
#define C3TDA2_Data_3_MASK 0xFF0000
4261
#define CAN3TDA2_Data_3_MASK C3TDA2_Data_3_MASK
4262
#define C3TDA2_Data_3_BIT 16
4263
#define CAN3TDA2_Data_3_BIT C3TDA2_Data_3_BIT
4264
#define C3TDA2_Data_4_MASK 0xFF000000
4265
#define CAN3TDA2_Data_4_MASK C3TDA2_Data_4_MASK
4266
#define C3TDA2_Data_4_BIT 24
4267
#define CAN3TDA2_Data_4_BIT C3TDA2_Data_4_BIT
4268
 
4269
#define C3TDB2 (*(volatile unsigned long *)0xE004C04C)
4270
#define CAN3TDB2 C3TDB2
4271
#define C3TDB2_OFFSET 0x4C
4272
#define CAN3TDB2_OFFSET C3TDB2_OFFSET
4273
#define C3TDB2_Data_5_MASK 0xFF
4274
#define CAN3TDB2_Data_5_MASK C3TDB2_Data_5_MASK
4275
#define C3TDB2_Data_5_BIT 0
4276
#define CAN3TDB2_Data_5_BIT C3TDB2_Data_5_BIT
4277
#define C3TDB2_Data_6_MASK 0xFF00
4278
#define CAN3TDB2_Data_6_MASK C3TDB2_Data_6_MASK
4279
#define C3TDB2_Data_6_BIT 8
4280
#define CAN3TDB2_Data_6_BIT C3TDB2_Data_6_BIT
4281
#define C3TDB2_Data_7_MASK 0xFF0000
4282
#define CAN3TDB2_Data_7_MASK C3TDB2_Data_7_MASK
4283
#define C3TDB2_Data_7_BIT 16
4284
#define CAN3TDB2_Data_7_BIT C3TDB2_Data_7_BIT
4285
#define C3TDB2_Data_8_MASK 0xFF000000
4286
#define CAN3TDB2_Data_8_MASK C3TDB2_Data_8_MASK
4287
#define C3TDB2_Data_8_BIT 24
4288
#define CAN3TDB2_Data_8_BIT C3TDB2_Data_8_BIT
4289
 
4290
#define C3TFI3 (*(volatile unsigned long *)0xE004C050)
4291
#define CAN3TFI3 C3TFI3
4292
#define C3TFI3_OFFSET 0x50
4293
#define CAN3TFI3_OFFSET C3TFI3_OFFSET
4294
#define C3TFI3_PRIO_MASK 0xFF
4295
#define CAN3TFI3_PRIO_MASK C3TFI3_PRIO_MASK
4296
#define C3TFI3_PRIO_BIT 0
4297
#define CAN3TFI3_PRIO_BIT C3TFI3_PRIO_BIT
4298
#define C3TFI3_DLC_MASK 0xF0000
4299
#define CAN3TFI3_DLC_MASK C3TFI3_DLC_MASK
4300
#define C3TFI3_DLC_BIT 16
4301
#define CAN3TFI3_DLC_BIT C3TFI3_DLC_BIT
4302
#define C3TFI3_RTR_MASK 0x40000000
4303
#define CAN3TFI3_RTR_MASK C3TFI3_RTR_MASK
4304
#define C3TFI3_RTR 0x40000000
4305
#define CAN3TFI3_RTR C3TFI3_RTR
4306
#define C3TFI3_RTR_BIT 30
4307
#define CAN3TFI3_RTR_BIT C3TFI3_RTR_BIT
4308
#define C3TFI3_FF_MASK 0x80000000
4309
#define CAN3TFI3_FF_MASK C3TFI3_FF_MASK
4310
#define C3TFI3_FF 0x80000000
4311
#define CAN3TFI3_FF C3TFI3_FF
4312
#define C3TFI3_FF_BIT 31
4313
#define CAN3TFI3_FF_BIT C3TFI3_FF_BIT
4314
 
4315
#define C3TID3 (*(volatile unsigned long *)0xE004C054)
4316
#define CAN3TID3 C3TID3
4317
#define C3TID3_OFFSET 0x54
4318
#define CAN3TID3_OFFSET C3TID3_OFFSET
4319
#define C3TID3_ID_MASK 0x7FF
4320
#define CAN3TID3_ID_MASK C3TID3_ID_MASK
4321
#define C3TID3_ID_BIT 0
4322
#define CAN3TID3_ID_BIT C3TID3_ID_BIT
4323
 
4324
#define C3TDA3 (*(volatile unsigned long *)0xE004C058)
4325
#define CAN3TDA3 C3TDA3
4326
#define C3TDA3_OFFSET 0x58
4327
#define CAN3TDA3_OFFSET C3TDA3_OFFSET
4328
#define C3TDA3_Data_1_MASK 0xFF
4329
#define CAN3TDA3_Data_1_MASK C3TDA3_Data_1_MASK
4330
#define C3TDA3_Data_1_BIT 0
4331
#define CAN3TDA3_Data_1_BIT C3TDA3_Data_1_BIT
4332
#define C3TDA3_Data_2_MASK 0xFF00
4333
#define CAN3TDA3_Data_2_MASK C3TDA3_Data_2_MASK
4334
#define C3TDA3_Data_2_BIT 8
4335
#define CAN3TDA3_Data_2_BIT C3TDA3_Data_2_BIT
4336
#define C3TDA3_Data_3_MASK 0xFF0000
4337
#define CAN3TDA3_Data_3_MASK C3TDA3_Data_3_MASK
4338
#define C3TDA3_Data_3_BIT 16
4339
#define CAN3TDA3_Data_3_BIT C3TDA3_Data_3_BIT
4340
#define C3TDA3_Data_4_MASK 0xFF000000
4341
#define CAN3TDA3_Data_4_MASK C3TDA3_Data_4_MASK
4342
#define C3TDA3_Data_4_BIT 24
4343
#define CAN3TDA3_Data_4_BIT C3TDA3_Data_4_BIT
4344
 
4345
#define C3TDB3 (*(volatile unsigned long *)0xE004C05C)
4346
#define CAN3TDB3 C3TDB3
4347
#define C3TDB3_OFFSET 0x5C
4348
#define CAN3TDB3_OFFSET C3TDB3_OFFSET
4349
#define C3TDB3_Data_5_MASK 0xFF
4350
#define CAN3TDB3_Data_5_MASK C3TDB3_Data_5_MASK
4351
#define C3TDB3_Data_5_BIT 0
4352
#define CAN3TDB3_Data_5_BIT C3TDB3_Data_5_BIT
4353
#define C3TDB3_Data_6_MASK 0xFF00
4354
#define CAN3TDB3_Data_6_MASK C3TDB3_Data_6_MASK
4355
#define C3TDB3_Data_6_BIT 8
4356
#define CAN3TDB3_Data_6_BIT C3TDB3_Data_6_BIT
4357
#define C3TDB3_Data_7_MASK 0xFF0000
4358
#define CAN3TDB3_Data_7_MASK C3TDB3_Data_7_MASK
4359
#define C3TDB3_Data_7_BIT 16
4360
#define CAN3TDB3_Data_7_BIT C3TDB3_Data_7_BIT
4361
#define C3TDB3_Data_8_MASK 0xFF000000
4362
#define CAN3TDB3_Data_8_MASK C3TDB3_Data_8_MASK
4363
#define C3TDB3_Data_8_BIT 24
4364
#define CAN3TDB3_Data_8_BIT C3TDB3_Data_8_BIT
4365
 
4366
#define CAN4_BASE 0xE0050000
4367
 
4368
#define C4MOD (*(volatile unsigned long *)0xE0050000)
4369
#define CAN4MOD C4MOD
4370
#define C4MOD_OFFSET 0x0
4371
#define CAN4MOD_OFFSET C4MOD_OFFSET
4372
#define C4MOD_RM_MASK 0x1
4373
#define CAN4MOD_RM_MASK C4MOD_RM_MASK
4374
#define C4MOD_RM 0x1
4375
#define CAN4MOD_RM C4MOD_RM
4376
#define C4MOD_RM_BIT 0
4377
#define CAN4MOD_RM_BIT C4MOD_RM_BIT
4378
#define C4MOD_LOM_MASK 0x2
4379
#define CAN4MOD_LOM_MASK C4MOD_LOM_MASK
4380
#define C4MOD_LOM 0x2
4381
#define CAN4MOD_LOM C4MOD_LOM
4382
#define C4MOD_LOM_BIT 1
4383
#define CAN4MOD_LOM_BIT C4MOD_LOM_BIT
4384
#define C4MOD_STM_MASK 0x4
4385
#define CAN4MOD_STM_MASK C4MOD_STM_MASK
4386
#define C4MOD_STM 0x4
4387
#define CAN4MOD_STM C4MOD_STM
4388
#define C4MOD_STM_BIT 2
4389
#define CAN4MOD_STM_BIT C4MOD_STM_BIT
4390
#define C4MOD_TPM_MASK 0x8
4391
#define CAN4MOD_TPM_MASK C4MOD_TPM_MASK
4392
#define C4MOD_TPM 0x8
4393
#define CAN4MOD_TPM C4MOD_TPM
4394
#define C4MOD_TPM_BIT 3
4395
#define CAN4MOD_TPM_BIT C4MOD_TPM_BIT
4396
#define C4MOD_SM_MASK 0x10
4397
#define CAN4MOD_SM_MASK C4MOD_SM_MASK
4398
#define C4MOD_SM 0x10
4399
#define CAN4MOD_SM C4MOD_SM
4400
#define C4MOD_SM_BIT 4
4401
#define CAN4MOD_SM_BIT C4MOD_SM_BIT
4402
#define C4MOD_RPM_MASK 0x20
4403
#define CAN4MOD_RPM_MASK C4MOD_RPM_MASK
4404
#define C4MOD_RPM 0x20
4405
#define CAN4MOD_RPM C4MOD_RPM
4406
#define C4MOD_RPM_BIT 5
4407
#define CAN4MOD_RPM_BIT C4MOD_RPM_BIT
4408
#define C4MOD_TM_MASK 0x80
4409
#define CAN4MOD_TM_MASK C4MOD_TM_MASK
4410
#define C4MOD_TM 0x80
4411
#define CAN4MOD_TM C4MOD_TM
4412
#define C4MOD_TM_BIT 7
4413
#define CAN4MOD_TM_BIT C4MOD_TM_BIT
4414
 
4415
#define C4CMR (*(volatile unsigned long *)0xE0050004)
4416
#define CAN4CMR C4CMR
4417
#define C4CMR_OFFSET 0x4
4418
#define CAN4CMR_OFFSET C4CMR_OFFSET
4419
#define C4CMR_TR_MASK 0x1
4420
#define CAN4CMR_TR_MASK C4CMR_TR_MASK
4421
#define C4CMR_TR 0x1
4422
#define CAN4CMR_TR C4CMR_TR
4423
#define C4CMR_TR_BIT 0
4424
#define CAN4CMR_TR_BIT C4CMR_TR_BIT
4425
#define C4CMR_AT_MASK 0x2
4426
#define CAN4CMR_AT_MASK C4CMR_AT_MASK
4427
#define C4CMR_AT 0x2
4428
#define CAN4CMR_AT C4CMR_AT
4429
#define C4CMR_AT_BIT 1
4430
#define CAN4CMR_AT_BIT C4CMR_AT_BIT
4431
#define C4CMR_RRB_MASK 0x4
4432
#define CAN4CMR_RRB_MASK C4CMR_RRB_MASK
4433
#define C4CMR_RRB 0x4
4434
#define CAN4CMR_RRB C4CMR_RRB
4435
#define C4CMR_RRB_BIT 2
4436
#define CAN4CMR_RRB_BIT C4CMR_RRB_BIT
4437
#define C4CMR_CDO_MASK 0x8
4438
#define CAN4CMR_CDO_MASK C4CMR_CDO_MASK
4439
#define C4CMR_CDO 0x8
4440
#define CAN4CMR_CDO C4CMR_CDO
4441
#define C4CMR_CDO_BIT 3
4442
#define CAN4CMR_CDO_BIT C4CMR_CDO_BIT
4443
#define C4CMR_SRR_MASK 0x10
4444
#define CAN4CMR_SRR_MASK C4CMR_SRR_MASK
4445
#define C4CMR_SRR 0x10
4446
#define CAN4CMR_SRR C4CMR_SRR
4447
#define C4CMR_SRR_BIT 4
4448
#define CAN4CMR_SRR_BIT C4CMR_SRR_BIT
4449
#define C4CMR_STB1_MASK 0x20
4450
#define CAN4CMR_STB1_MASK C4CMR_STB1_MASK
4451
#define C4CMR_STB1 0x20
4452
#define CAN4CMR_STB1 C4CMR_STB1
4453
#define C4CMR_STB1_BIT 5
4454
#define CAN4CMR_STB1_BIT C4CMR_STB1_BIT
4455
#define C4CMR_STB2_MASK 0x40
4456
#define CAN4CMR_STB2_MASK C4CMR_STB2_MASK
4457
#define C4CMR_STB2 0x40
4458
#define CAN4CMR_STB2 C4CMR_STB2
4459
#define C4CMR_STB2_BIT 6
4460
#define CAN4CMR_STB2_BIT C4CMR_STB2_BIT
4461
#define C4CMR_STB3_MASK 0x80
4462
#define CAN4CMR_STB3_MASK C4CMR_STB3_MASK
4463
#define C4CMR_STB3 0x80
4464
#define CAN4CMR_STB3 C4CMR_STB3
4465
#define C4CMR_STB3_BIT 7
4466
#define CAN4CMR_STB3_BIT C4CMR_STB3_BIT
4467
 
4468
#define C4GSR (*(volatile unsigned long *)0xE0050008)
4469
#define CAN4GSR C4GSR
4470
#define C4GSR_OFFSET 0x8
4471
#define CAN4GSR_OFFSET C4GSR_OFFSET
4472
#define C4GSR_RBS_MASK 0x1
4473
#define CAN4GSR_RBS_MASK C4GSR_RBS_MASK
4474
#define C4GSR_RBS 0x1
4475
#define CAN4GSR_RBS C4GSR_RBS
4476
#define C4GSR_RBS_BIT 0
4477
#define CAN4GSR_RBS_BIT C4GSR_RBS_BIT
4478
#define C4GSR_DOS_MASK 0x2
4479
#define CAN4GSR_DOS_MASK C4GSR_DOS_MASK
4480
#define C4GSR_DOS 0x2
4481
#define CAN4GSR_DOS C4GSR_DOS
4482
#define C4GSR_DOS_BIT 1
4483
#define CAN4GSR_DOS_BIT C4GSR_DOS_BIT
4484
#define C4GSR_TBS_MASK 0x4
4485
#define CAN4GSR_TBS_MASK C4GSR_TBS_MASK
4486
#define C4GSR_TBS 0x4
4487
#define CAN4GSR_TBS C4GSR_TBS
4488
#define C4GSR_TBS_BIT 2
4489
#define CAN4GSR_TBS_BIT C4GSR_TBS_BIT
4490
#define C4GSR_TCS_MASK 0x8
4491
#define CAN4GSR_TCS_MASK C4GSR_TCS_MASK
4492
#define C4GSR_TCS 0x8
4493
#define CAN4GSR_TCS C4GSR_TCS
4494
#define C4GSR_TCS_BIT 3
4495
#define CAN4GSR_TCS_BIT C4GSR_TCS_BIT
4496
#define C4GSR_RS_MASK 0x10
4497
#define CAN4GSR_RS_MASK C4GSR_RS_MASK
4498
#define C4GSR_RS 0x10
4499
#define CAN4GSR_RS C4GSR_RS
4500
#define C4GSR_RS_BIT 4
4501
#define CAN4GSR_RS_BIT C4GSR_RS_BIT
4502
#define C4GSR_TS_MASK 0x20
4503
#define CAN4GSR_TS_MASK C4GSR_TS_MASK
4504
#define C4GSR_TS 0x20
4505
#define CAN4GSR_TS C4GSR_TS
4506
#define C4GSR_TS_BIT 5
4507
#define CAN4GSR_TS_BIT C4GSR_TS_BIT
4508
#define C4GSR_ES_MASK 0x40
4509
#define CAN4GSR_ES_MASK C4GSR_ES_MASK
4510
#define C4GSR_ES 0x40
4511
#define CAN4GSR_ES C4GSR_ES
4512
#define C4GSR_ES_BIT 6
4513
#define CAN4GSR_ES_BIT C4GSR_ES_BIT
4514
#define C4GSR_BS_MASK 0x80
4515
#define CAN4GSR_BS_MASK C4GSR_BS_MASK
4516
#define C4GSR_BS 0x80
4517
#define CAN4GSR_BS C4GSR_BS
4518
#define C4GSR_BS_BIT 7
4519
#define CAN4GSR_BS_BIT C4GSR_BS_BIT
4520
#define C4GSR_RXERR_MASK 0xFF0000
4521
#define CAN4GSR_RXERR_MASK C4GSR_RXERR_MASK
4522
#define C4GSR_RXERR_BIT 16
4523
#define CAN4GSR_RXERR_BIT C4GSR_RXERR_BIT
4524
#define C4GSR_TXERR_MASK 0xFF000000
4525
#define CAN4GSR_TXERR_MASK C4GSR_TXERR_MASK
4526
#define C4GSR_TXERR_BIT 24
4527
#define CAN4GSR_TXERR_BIT C4GSR_TXERR_BIT
4528
 
4529
#define C4ICR (*(volatile unsigned long *)0xE005000C)
4530
#define CAN4ICR C4ICR
4531
#define C4ICR_OFFSET 0xC
4532
#define CAN4ICR_OFFSET C4ICR_OFFSET
4533
#define C4ICR_RI_MASK 0x1
4534
#define CAN4ICR_RI_MASK C4ICR_RI_MASK
4535
#define C4ICR_RI 0x1
4536
#define CAN4ICR_RI C4ICR_RI
4537
#define C4ICR_RI_BIT 0
4538
#define CAN4ICR_RI_BIT C4ICR_RI_BIT
4539
#define C4ICR_TI1_MASK 0x2
4540
#define CAN4ICR_TI1_MASK C4ICR_TI1_MASK
4541
#define C4ICR_TI1 0x2
4542
#define CAN4ICR_TI1 C4ICR_TI1
4543
#define C4ICR_TI1_BIT 1
4544
#define CAN4ICR_TI1_BIT C4ICR_TI1_BIT
4545
#define C4ICR_EI_MASK 0x4
4546
#define CAN4ICR_EI_MASK C4ICR_EI_MASK
4547
#define C4ICR_EI 0x4
4548
#define CAN4ICR_EI C4ICR_EI
4549
#define C4ICR_EI_BIT 2
4550
#define CAN4ICR_EI_BIT C4ICR_EI_BIT
4551
#define C4ICR_DOI_MASK 0x8
4552
#define CAN4ICR_DOI_MASK C4ICR_DOI_MASK
4553
#define C4ICR_DOI 0x8
4554
#define CAN4ICR_DOI C4ICR_DOI
4555
#define C4ICR_DOI_BIT 3
4556
#define CAN4ICR_DOI_BIT C4ICR_DOI_BIT
4557
#define C4ICR_WUI_MASK 0x10
4558
#define CAN4ICR_WUI_MASK C4ICR_WUI_MASK
4559
#define C4ICR_WUI 0x10
4560
#define CAN4ICR_WUI C4ICR_WUI
4561
#define C4ICR_WUI_BIT 4
4562
#define CAN4ICR_WUI_BIT C4ICR_WUI_BIT
4563
#define C4ICR_EPI_MASK 0x20
4564
#define CAN4ICR_EPI_MASK C4ICR_EPI_MASK
4565
#define C4ICR_EPI 0x20
4566
#define CAN4ICR_EPI C4ICR_EPI
4567
#define C4ICR_EPI_BIT 5
4568
#define CAN4ICR_EPI_BIT C4ICR_EPI_BIT
4569
#define C4ICR_ALI_MASK 0x40
4570
#define CAN4ICR_ALI_MASK C4ICR_ALI_MASK
4571
#define C4ICR_ALI 0x40
4572
#define CAN4ICR_ALI C4ICR_ALI
4573
#define C4ICR_ALI_BIT 6
4574
#define CAN4ICR_ALI_BIT C4ICR_ALI_BIT
4575
#define C4ICR_BEI_MASK 0x80
4576
#define CAN4ICR_BEI_MASK C4ICR_BEI_MASK
4577
#define C4ICR_BEI 0x80
4578
#define CAN4ICR_BEI C4ICR_BEI
4579
#define C4ICR_BEI_BIT 7
4580
#define CAN4ICR_BEI_BIT C4ICR_BEI_BIT
4581
#define C4ICR_IDI_MASK 0x100
4582
#define CAN4ICR_IDI_MASK C4ICR_IDI_MASK
4583
#define C4ICR_IDI 0x100
4584
#define CAN4ICR_IDI C4ICR_IDI
4585
#define C4ICR_IDI_BIT 8
4586
#define CAN4ICR_IDI_BIT C4ICR_IDI_BIT
4587
#define C4ICR_TI2_MASK 0x200
4588
#define CAN4ICR_TI2_MASK C4ICR_TI2_MASK
4589
#define C4ICR_TI2 0x200
4590
#define CAN4ICR_TI2 C4ICR_TI2
4591
#define C4ICR_TI2_BIT 9
4592
#define CAN4ICR_TI2_BIT C4ICR_TI2_BIT
4593
#define C4ICR_TI3_MASK 0x400
4594
#define CAN4ICR_TI3_MASK C4ICR_TI3_MASK
4595
#define C4ICR_TI3 0x400
4596
#define CAN4ICR_TI3 C4ICR_TI3
4597
#define C4ICR_TI3_BIT 10
4598
#define CAN4ICR_TI3_BIT C4ICR_TI3_BIT
4599
#define C4ICR_ERRBIT_MASK 0x1F0000
4600
#define CAN4ICR_ERRBIT_MASK C4ICR_ERRBIT_MASK
4601
#define C4ICR_ERRBIT_BIT 16
4602
#define CAN4ICR_ERRBIT_BIT C4ICR_ERRBIT_BIT
4603
#define C4ICR_ERRDIR_MASK 0x200000
4604
#define CAN4ICR_ERRDIR_MASK C4ICR_ERRDIR_MASK
4605
#define C4ICR_ERRDIR 0x200000
4606
#define CAN4ICR_ERRDIR C4ICR_ERRDIR
4607
#define C4ICR_ERRDIR_BIT 21
4608
#define CAN4ICR_ERRDIR_BIT C4ICR_ERRDIR_BIT
4609
#define C4ICR_ERRC_MASK 0xC00000
4610
#define CAN4ICR_ERRC_MASK C4ICR_ERRC_MASK
4611
#define C4ICR_ERRC_BIT 22
4612
#define CAN4ICR_ERRC_BIT C4ICR_ERRC_BIT
4613
#define C4ICR_ALCBIT_MASK 0x1F000000
4614
#define CAN4ICR_ALCBIT_MASK C4ICR_ALCBIT_MASK
4615
#define C4ICR_ALCBIT_BIT 24
4616
#define CAN4ICR_ALCBIT_BIT C4ICR_ALCBIT_BIT
4617
 
4618
#define C4IER (*(volatile unsigned long *)0xE0050010)
4619
#define CAN4IER C4IER
4620
#define C4IER_OFFSET 0x10
4621
#define CAN4IER_OFFSET C4IER_OFFSET
4622
#define C4IER_RIE_MASK 0x1
4623
#define CAN4IER_RIE_MASK C4IER_RIE_MASK
4624
#define C4IER_RIE 0x1
4625
#define CAN4IER_RIE C4IER_RIE
4626
#define C4IER_RIE_BIT 0
4627
#define CAN4IER_RIE_BIT C4IER_RIE_BIT
4628
#define C4IER_TIE1_MASK 0x2
4629
#define CAN4IER_TIE1_MASK C4IER_TIE1_MASK
4630
#define C4IER_TIE1 0x2
4631
#define CAN4IER_TIE1 C4IER_TIE1
4632
#define C4IER_TIE1_BIT 1
4633
#define CAN4IER_TIE1_BIT C4IER_TIE1_BIT
4634
#define C4IER_EIE_MASK 0x4
4635
#define CAN4IER_EIE_MASK C4IER_EIE_MASK
4636
#define C4IER_EIE 0x4
4637
#define CAN4IER_EIE C4IER_EIE
4638
#define C4IER_EIE_BIT 2
4639
#define CAN4IER_EIE_BIT C4IER_EIE_BIT
4640
#define C4IER_DOIE_MASK 0x8
4641
#define CAN4IER_DOIE_MASK C4IER_DOIE_MASK
4642
#define C4IER_DOIE 0x8
4643
#define CAN4IER_DOIE C4IER_DOIE
4644
#define C4IER_DOIE_BIT 3
4645
#define CAN4IER_DOIE_BIT C4IER_DOIE_BIT
4646
#define C4IER_WUIE_MASK 0x10
4647
#define CAN4IER_WUIE_MASK C4IER_WUIE_MASK
4648
#define C4IER_WUIE 0x10
4649
#define CAN4IER_WUIE C4IER_WUIE
4650
#define C4IER_WUIE_BIT 4
4651
#define CAN4IER_WUIE_BIT C4IER_WUIE_BIT
4652
#define C4IER_EPIE_MASK 0x20
4653
#define CAN4IER_EPIE_MASK C4IER_EPIE_MASK
4654
#define C4IER_EPIE 0x20
4655
#define CAN4IER_EPIE C4IER_EPIE
4656
#define C4IER_EPIE_BIT 5
4657
#define CAN4IER_EPIE_BIT C4IER_EPIE_BIT
4658
#define C4IER_ALIE_MASK 0x40
4659
#define CAN4IER_ALIE_MASK C4IER_ALIE_MASK
4660
#define C4IER_ALIE 0x40
4661
#define CAN4IER_ALIE C4IER_ALIE
4662
#define C4IER_ALIE_BIT 6
4663
#define CAN4IER_ALIE_BIT C4IER_ALIE_BIT
4664
#define C4IER_BEIE_MASK 0x80
4665
#define CAN4IER_BEIE_MASK C4IER_BEIE_MASK
4666
#define C4IER_BEIE 0x80
4667
#define CAN4IER_BEIE C4IER_BEIE
4668
#define C4IER_BEIE_BIT 7
4669
#define CAN4IER_BEIE_BIT C4IER_BEIE_BIT
4670
#define C4IER_IDIE_MASK 0x100
4671
#define CAN4IER_IDIE_MASK C4IER_IDIE_MASK
4672
#define C4IER_IDIE 0x100
4673
#define CAN4IER_IDIE C4IER_IDIE
4674
#define C4IER_IDIE_BIT 8
4675
#define CAN4IER_IDIE_BIT C4IER_IDIE_BIT
4676
#define C4IER_TIE2_MASK 0x200
4677
#define CAN4IER_TIE2_MASK C4IER_TIE2_MASK
4678
#define C4IER_TIE2 0x200
4679
#define CAN4IER_TIE2 C4IER_TIE2
4680
#define C4IER_TIE2_BIT 9
4681
#define CAN4IER_TIE2_BIT C4IER_TIE2_BIT
4682
#define C4IER_TIE3_MASK 0x400
4683
#define CAN4IER_TIE3_MASK C4IER_TIE3_MASK
4684
#define C4IER_TIE3 0x400
4685
#define CAN4IER_TIE3 C4IER_TIE3
4686
#define C4IER_TIE3_BIT 10
4687
#define CAN4IER_TIE3_BIT C4IER_TIE3_BIT
4688
 
4689
#define C4BTR (*(volatile unsigned long *)0xE0050014)
4690
#define CAN4BTR C4BTR
4691
#define C4BTR_OFFSET 0x14
4692
#define CAN4BTR_OFFSET C4BTR_OFFSET
4693
#define C4BTR_BRP_MASK 0x3FF
4694
#define CAN4BTR_BRP_MASK C4BTR_BRP_MASK
4695
#define C4BTR_BRP_BIT 0
4696
#define CAN4BTR_BRP_BIT C4BTR_BRP_BIT
4697
#define C4BTR_SJW_MASK 0xC000
4698
#define CAN4BTR_SJW_MASK C4BTR_SJW_MASK
4699
#define C4BTR_SJW_BIT 14
4700
#define CAN4BTR_SJW_BIT C4BTR_SJW_BIT
4701
#define C4BTR_TSEG1_MASK 0xF0000
4702
#define CAN4BTR_TSEG1_MASK C4BTR_TSEG1_MASK
4703
#define C4BTR_TSEG1_BIT 16
4704
#define CAN4BTR_TSEG1_BIT C4BTR_TSEG1_BIT
4705
#define C4BTR_TSEG2_MASK 0x700000
4706
#define CAN4BTR_TSEG2_MASK C4BTR_TSEG2_MASK
4707
#define C4BTR_TSEG2_BIT 20
4708
#define CAN4BTR_TSEG2_BIT C4BTR_TSEG2_BIT
4709
#define C4BTR_SAM_MASK 0x800000
4710
#define CAN4BTR_SAM_MASK C4BTR_SAM_MASK
4711
#define C4BTR_SAM 0x800000
4712
#define CAN4BTR_SAM C4BTR_SAM
4713
#define C4BTR_SAM_BIT 23
4714
#define CAN4BTR_SAM_BIT C4BTR_SAM_BIT
4715
 
4716
#define C4EWL (*(volatile unsigned long *)0xE0050018)
4717
#define CAN4EWL C4EWL
4718
#define C4EWL_OFFSET 0x18
4719
#define CAN4EWL_OFFSET C4EWL_OFFSET
4720
#define C4EWL_EWL_MASK 0xFF
4721
#define CAN4EWL_EWL_MASK C4EWL_EWL_MASK
4722
#define C4EWL_EWL_BIT 0
4723
#define CAN4EWL_EWL_BIT C4EWL_EWL_BIT
4724
 
4725
#define C4SR (*(volatile unsigned long *)0xE005001C)
4726
#define CAN4SR C4SR
4727
#define C4SR_OFFSET 0x1C
4728
#define CAN4SR_OFFSET C4SR_OFFSET
4729
#define C4SR_RBS_MASK 0x1
4730
#define CAN4SR_RBS_MASK C4SR_RBS_MASK
4731
#define C4SR_RBS 0x1
4732
#define CAN4SR_RBS C4SR_RBS
4733
#define C4SR_RBS_BIT 0
4734
#define CAN4SR_RBS_BIT C4SR_RBS_BIT
4735
#define C4SR_DOS_MASK 0x2
4736
#define CAN4SR_DOS_MASK C4SR_DOS_MASK
4737
#define C4SR_DOS 0x2
4738
#define CAN4SR_DOS C4SR_DOS
4739
#define C4SR_DOS_BIT 1
4740
#define CAN4SR_DOS_BIT C4SR_DOS_BIT
4741
#define C4SR_TBS1_MASK 0x4
4742
#define CAN4SR_TBS1_MASK C4SR_TBS1_MASK
4743
#define C4SR_TBS1 0x4
4744
#define CAN4SR_TBS1 C4SR_TBS1
4745
#define C4SR_TBS1_BIT 2
4746
#define CAN4SR_TBS1_BIT C4SR_TBS1_BIT
4747
#define C4SR_TCS1_MASK 0x8
4748
#define CAN4SR_TCS1_MASK C4SR_TCS1_MASK
4749
#define C4SR_TCS1 0x8
4750
#define CAN4SR_TCS1 C4SR_TCS1
4751
#define C4SR_TCS1_BIT 3
4752
#define CAN4SR_TCS1_BIT C4SR_TCS1_BIT
4753
#define C4SR_RS_MASK 0x10
4754
#define CAN4SR_RS_MASK C4SR_RS_MASK
4755
#define C4SR_RS 0x10
4756
#define CAN4SR_RS C4SR_RS
4757
#define C4SR_RS_BIT 4
4758
#define CAN4SR_RS_BIT C4SR_RS_BIT
4759
#define C4SR_TS1_MASK 0x20
4760
#define CAN4SR_TS1_MASK C4SR_TS1_MASK
4761
#define C4SR_TS1 0x20
4762
#define CAN4SR_TS1 C4SR_TS1
4763
#define C4SR_TS1_BIT 5
4764
#define CAN4SR_TS1_BIT C4SR_TS1_BIT
4765
#define C4SR_ES_MASK 0x40
4766
#define CAN4SR_ES_MASK C4SR_ES_MASK
4767
#define C4SR_ES 0x40
4768
#define CAN4SR_ES C4SR_ES
4769
#define C4SR_ES_BIT 6
4770
#define CAN4SR_ES_BIT C4SR_ES_BIT
4771
#define C4SR_BS_MASK 0x80
4772
#define CAN4SR_BS_MASK C4SR_BS_MASK
4773
#define C4SR_BS 0x80
4774
#define CAN4SR_BS C4SR_BS
4775
#define C4SR_BS_BIT 7
4776
#define CAN4SR_BS_BIT C4SR_BS_BIT
4777
#define C4SR_RBS2_MASK 0x100
4778
#define CAN4SR_RBS2_MASK C4SR_RBS2_MASK
4779
#define C4SR_RBS2 0x100
4780
#define CAN4SR_RBS2 C4SR_RBS2
4781
#define C4SR_RBS2_BIT 8
4782
#define CAN4SR_RBS2_BIT C4SR_RBS2_BIT
4783
#define C4SR_DOS2_MASK 0x200
4784
#define CAN4SR_DOS2_MASK C4SR_DOS2_MASK
4785
#define C4SR_DOS2 0x200
4786
#define CAN4SR_DOS2 C4SR_DOS2
4787
#define C4SR_DOS2_BIT 9
4788
#define CAN4SR_DOS2_BIT C4SR_DOS2_BIT
4789
#define C4SR_TBS2_MASK 0x400
4790
#define CAN4SR_TBS2_MASK C4SR_TBS2_MASK
4791
#define C4SR_TBS2 0x400
4792
#define CAN4SR_TBS2 C4SR_TBS2
4793
#define C4SR_TBS2_BIT 10
4794
#define CAN4SR_TBS2_BIT C4SR_TBS2_BIT
4795
#define C4SR_TCS2_MASK 0x800
4796
#define CAN4SR_TCS2_MASK C4SR_TCS2_MASK
4797
#define C4SR_TCS2 0x800
4798
#define CAN4SR_TCS2 C4SR_TCS2
4799
#define C4SR_TCS2_BIT 11
4800
#define CAN4SR_TCS2_BIT C4SR_TCS2_BIT
4801
#define C4SR_RS2_MASK 0x1000
4802
#define CAN4SR_RS2_MASK C4SR_RS2_MASK
4803
#define C4SR_RS2 0x1000
4804
#define CAN4SR_RS2 C4SR_RS2
4805
#define C4SR_RS2_BIT 12
4806
#define CAN4SR_RS2_BIT C4SR_RS2_BIT
4807
#define C4SR_TS2_MASK 0x2000
4808
#define CAN4SR_TS2_MASK C4SR_TS2_MASK
4809
#define C4SR_TS2 0x2000
4810
#define CAN4SR_TS2 C4SR_TS2
4811
#define C4SR_TS2_BIT 13
4812
#define CAN4SR_TS2_BIT C4SR_TS2_BIT
4813
#define C4SR_ES2_MASK 0x4000
4814
#define CAN4SR_ES2_MASK C4SR_ES2_MASK
4815
#define C4SR_ES2 0x4000
4816
#define CAN4SR_ES2 C4SR_ES2
4817
#define C4SR_ES2_BIT 14
4818
#define CAN4SR_ES2_BIT C4SR_ES2_BIT
4819
#define C4SR_BS2_MASK 0x8000
4820
#define CAN4SR_BS2_MASK C4SR_BS2_MASK
4821
#define C4SR_BS2 0x8000
4822
#define CAN4SR_BS2 C4SR_BS2
4823
#define C4SR_BS2_BIT 15
4824
#define CAN4SR_BS2_BIT C4SR_BS2_BIT
4825
#define C4SR_RBS3_MASK 0x10000
4826
#define CAN4SR_RBS3_MASK C4SR_RBS3_MASK
4827
#define C4SR_RBS3 0x10000
4828
#define CAN4SR_RBS3 C4SR_RBS3
4829
#define C4SR_RBS3_BIT 16
4830
#define CAN4SR_RBS3_BIT C4SR_RBS3_BIT
4831
#define C4SR_DOS3_MASK 0x20000
4832
#define CAN4SR_DOS3_MASK C4SR_DOS3_MASK
4833
#define C4SR_DOS3 0x20000
4834
#define CAN4SR_DOS3 C4SR_DOS3
4835
#define C4SR_DOS3_BIT 17
4836
#define CAN4SR_DOS3_BIT C4SR_DOS3_BIT
4837
#define C4SR_TBS3_MASK 0x40000
4838
#define CAN4SR_TBS3_MASK C4SR_TBS3_MASK
4839
#define C4SR_TBS3 0x40000
4840
#define CAN4SR_TBS3 C4SR_TBS3
4841
#define C4SR_TBS3_BIT 18
4842
#define CAN4SR_TBS3_BIT C4SR_TBS3_BIT
4843
#define C4SR_TCS3_MASK 0x80000
4844
#define CAN4SR_TCS3_MASK C4SR_TCS3_MASK
4845
#define C4SR_TCS3 0x80000
4846
#define CAN4SR_TCS3 C4SR_TCS3
4847
#define C4SR_TCS3_BIT 19
4848
#define CAN4SR_TCS3_BIT C4SR_TCS3_BIT
4849
#define C4SR_RS3_MASK 0x100000
4850
#define CAN4SR_RS3_MASK C4SR_RS3_MASK
4851
#define C4SR_RS3 0x100000
4852
#define CAN4SR_RS3 C4SR_RS3
4853
#define C4SR_RS3_BIT 20
4854
#define CAN4SR_RS3_BIT C4SR_RS3_BIT
4855
#define C4SR_TS3_MASK 0x200000
4856
#define CAN4SR_TS3_MASK C4SR_TS3_MASK
4857
#define C4SR_TS3 0x200000
4858
#define CAN4SR_TS3 C4SR_TS3
4859
#define C4SR_TS3_BIT 21
4860
#define CAN4SR_TS3_BIT C4SR_TS3_BIT
4861
#define C4SR_ES3_MASK 0x400000
4862
#define CAN4SR_ES3_MASK C4SR_ES3_MASK
4863
#define C4SR_ES3 0x400000
4864
#define CAN4SR_ES3 C4SR_ES3
4865
#define C4SR_ES3_BIT 22
4866
#define CAN4SR_ES3_BIT C4SR_ES3_BIT
4867
#define C4SR_BS3_MASK 0x800000
4868
#define CAN4SR_BS3_MASK C4SR_BS3_MASK
4869
#define C4SR_BS3 0x800000
4870
#define CAN4SR_BS3 C4SR_BS3
4871
#define C4SR_BS3_BIT 23
4872
#define CAN4SR_BS3_BIT C4SR_BS3_BIT
4873
 
4874
#define C4RFS (*(volatile unsigned long *)0xE0050020)
4875
#define CAN4RFS C4RFS
4876
#define C4RFS_OFFSET 0x20
4877
#define CAN4RFS_OFFSET C4RFS_OFFSET
4878
#define C4RFS_ID_Index_MASK 0x3FF
4879
#define CAN4RFS_ID_Index_MASK C4RFS_ID_Index_MASK
4880
#define C4RFS_ID_Index_BIT 0
4881
#define CAN4RFS_ID_Index_BIT C4RFS_ID_Index_BIT
4882
#define C4RFS_BP_MASK 0x400
4883
#define CAN4RFS_BP_MASK C4RFS_BP_MASK
4884
#define C4RFS_BP 0x400
4885
#define CAN4RFS_BP C4RFS_BP
4886
#define C4RFS_BP_BIT 10
4887
#define CAN4RFS_BP_BIT C4RFS_BP_BIT
4888
#define C4RFS_DLC_MASK 0xF0000
4889
#define CAN4RFS_DLC_MASK C4RFS_DLC_MASK
4890
#define C4RFS_DLC_BIT 16
4891
#define CAN4RFS_DLC_BIT C4RFS_DLC_BIT
4892
#define C4RFS_RTR_MASK 0x40000000
4893
#define CAN4RFS_RTR_MASK C4RFS_RTR_MASK
4894
#define C4RFS_RTR 0x40000000
4895
#define CAN4RFS_RTR C4RFS_RTR
4896
#define C4RFS_RTR_BIT 30
4897
#define CAN4RFS_RTR_BIT C4RFS_RTR_BIT
4898
#define C4RFS_FF_MASK 0x80000000
4899
#define CAN4RFS_FF_MASK C4RFS_FF_MASK
4900
#define C4RFS_FF 0x80000000
4901
#define CAN4RFS_FF C4RFS_FF
4902
#define C4RFS_FF_BIT 31
4903
#define CAN4RFS_FF_BIT C4RFS_FF_BIT
4904
 
4905
#define C4RID (*(volatile unsigned long *)0xE0050024)
4906
#define CAN4RID C4RID
4907
#define C4RID_OFFSET 0x24
4908
#define CAN4RID_OFFSET C4RID_OFFSET
4909
#define C4RID_ID_MASK 0x7FF
4910
#define CAN4RID_ID_MASK C4RID_ID_MASK
4911
#define C4RID_ID_BIT 0
4912
#define CAN4RID_ID_BIT C4RID_ID_BIT
4913
 
4914
#define C4RDA (*(volatile unsigned long *)0xE0050028)
4915
#define CAN4RDA C4RDA
4916
#define C4RDA_OFFSET 0x28
4917
#define CAN4RDA_OFFSET C4RDA_OFFSET
4918
#define C4RDA_Data_1_MASK 0xFF
4919
#define CAN4RDA_Data_1_MASK C4RDA_Data_1_MASK
4920
#define C4RDA_Data_1_BIT 0
4921
#define CAN4RDA_Data_1_BIT C4RDA_Data_1_BIT
4922
#define C4RDA_Data_2_MASK 0xFF00
4923
#define CAN4RDA_Data_2_MASK C4RDA_Data_2_MASK
4924
#define C4RDA_Data_2_BIT 8
4925
#define CAN4RDA_Data_2_BIT C4RDA_Data_2_BIT
4926
#define C4RDA_Data_3_MASK 0xFF0000
4927
#define CAN4RDA_Data_3_MASK C4RDA_Data_3_MASK
4928
#define C4RDA_Data_3_BIT 16
4929
#define CAN4RDA_Data_3_BIT C4RDA_Data_3_BIT
4930
#define C4RDA_Data_4_MASK 0xFF000000
4931
#define CAN4RDA_Data_4_MASK C4RDA_Data_4_MASK
4932
#define C4RDA_Data_4_BIT 24
4933
#define CAN4RDA_Data_4_BIT C4RDA_Data_4_BIT
4934
 
4935
#define C4RDB (*(volatile unsigned long *)0xE005002C)
4936
#define CAN4RDB C4RDB
4937
#define C4RDB_OFFSET 0x2C
4938
#define CAN4RDB_OFFSET C4RDB_OFFSET
4939
#define C4RDB_Data_5_MASK 0xFF
4940
#define CAN4RDB_Data_5_MASK C4RDB_Data_5_MASK
4941
#define C4RDB_Data_5_BIT 0
4942
#define CAN4RDB_Data_5_BIT C4RDB_Data_5_BIT
4943
#define C4RDB_Data_6_MASK 0xFF00
4944
#define CAN4RDB_Data_6_MASK C4RDB_Data_6_MASK
4945
#define C4RDB_Data_6_BIT 8
4946
#define CAN4RDB_Data_6_BIT C4RDB_Data_6_BIT
4947
#define C4RDB_Data_7_MASK 0xFF0000
4948
#define CAN4RDB_Data_7_MASK C4RDB_Data_7_MASK
4949
#define C4RDB_Data_7_BIT 16
4950
#define CAN4RDB_Data_7_BIT C4RDB_Data_7_BIT
4951
#define C4RDB_Data_8_MASK 0xFF000000
4952
#define CAN4RDB_Data_8_MASK C4RDB_Data_8_MASK
4953
#define C4RDB_Data_8_BIT 24
4954
#define CAN4RDB_Data_8_BIT C4RDB_Data_8_BIT
4955
 
4956
#define C4TFI1 (*(volatile unsigned long *)0xE0050030)
4957
#define CAN4TFI1 C4TFI1
4958
#define C4TFI1_OFFSET 0x30
4959
#define CAN4TFI1_OFFSET C4TFI1_OFFSET
4960
#define C4TFI1_PRIO_MASK 0xFF
4961
#define CAN4TFI1_PRIO_MASK C4TFI1_PRIO_MASK
4962
#define C4TFI1_PRIO_BIT 0
4963
#define CAN4TFI1_PRIO_BIT C4TFI1_PRIO_BIT
4964
#define C4TFI1_DLC_MASK 0xF0000
4965
#define CAN4TFI1_DLC_MASK C4TFI1_DLC_MASK
4966
#define C4TFI1_DLC_BIT 16
4967
#define CAN4TFI1_DLC_BIT C4TFI1_DLC_BIT
4968
#define C4TFI1_RTR_MASK 0x40000000
4969
#define CAN4TFI1_RTR_MASK C4TFI1_RTR_MASK
4970
#define C4TFI1_RTR 0x40000000
4971
#define CAN4TFI1_RTR C4TFI1_RTR
4972
#define C4TFI1_RTR_BIT 30
4973
#define CAN4TFI1_RTR_BIT C4TFI1_RTR_BIT
4974
#define C4TFI1_FF_MASK 0x80000000
4975
#define CAN4TFI1_FF_MASK C4TFI1_FF_MASK
4976
#define C4TFI1_FF 0x80000000
4977
#define CAN4TFI1_FF C4TFI1_FF
4978
#define C4TFI1_FF_BIT 31
4979
#define CAN4TFI1_FF_BIT C4TFI1_FF_BIT
4980
 
4981
#define C4TID1 (*(volatile unsigned long *)0xE0050034)
4982
#define CAN4TID1 C4TID1
4983
#define C4TID1_OFFSET 0x34
4984
#define CAN4TID1_OFFSET C4TID1_OFFSET
4985
#define C4TID1_ID_MASK 0x7FF
4986
#define CAN4TID1_ID_MASK C4TID1_ID_MASK
4987
#define C4TID1_ID_BIT 0
4988
#define CAN4TID1_ID_BIT C4TID1_ID_BIT
4989
 
4990
#define C4TDA1 (*(volatile unsigned long *)0xE0050038)
4991
#define CAN4TDA1 C4TDA1
4992
#define C4TDA1_OFFSET 0x38
4993
#define CAN4TDA1_OFFSET C4TDA1_OFFSET
4994
#define C4TDA1_Data_1_MASK 0xFF
4995
#define CAN4TDA1_Data_1_MASK C4TDA1_Data_1_MASK
4996
#define C4TDA1_Data_1_BIT 0
4997
#define CAN4TDA1_Data_1_BIT C4TDA1_Data_1_BIT
4998
#define C4TDA1_Data_2_MASK 0xFF00
4999
#define CAN4TDA1_Data_2_MASK C4TDA1_Data_2_MASK
5000
#define C4TDA1_Data_2_BIT 8
5001
#define CAN4TDA1_Data_2_BIT C4TDA1_Data_2_BIT
5002
#define C4TDA1_Data_3_MASK 0xFF0000
5003
#define CAN4TDA1_Data_3_MASK C4TDA1_Data_3_MASK
5004
#define C4TDA1_Data_3_BIT 16
5005
#define CAN4TDA1_Data_3_BIT C4TDA1_Data_3_BIT
5006
#define C4TDA1_Data_4_MASK 0xFF000000
5007
#define CAN4TDA1_Data_4_MASK C4TDA1_Data_4_MASK
5008
#define C4TDA1_Data_4_BIT 24
5009
#define CAN4TDA1_Data_4_BIT C4TDA1_Data_4_BIT
5010
 
5011
#define C4TDB1 (*(volatile unsigned long *)0xE005003C)
5012
#define CAN4TDB1 C4TDB1
5013
#define C4TDB1_OFFSET 0x3C
5014
#define CAN4TDB1_OFFSET C4TDB1_OFFSET
5015
#define C4TDB1_Data_5_MASK 0xFF
5016
#define CAN4TDB1_Data_5_MASK C4TDB1_Data_5_MASK
5017
#define C4TDB1_Data_5_BIT 0
5018
#define CAN4TDB1_Data_5_BIT C4TDB1_Data_5_BIT
5019
#define C4TDB1_Data_6_MASK 0xFF00
5020
#define CAN4TDB1_Data_6_MASK C4TDB1_Data_6_MASK
5021
#define C4TDB1_Data_6_BIT 8
5022
#define CAN4TDB1_Data_6_BIT C4TDB1_Data_6_BIT
5023
#define C4TDB1_Data_7_MASK 0xFF0000
5024
#define CAN4TDB1_Data_7_MASK C4TDB1_Data_7_MASK
5025
#define C4TDB1_Data_7_BIT 16
5026
#define CAN4TDB1_Data_7_BIT C4TDB1_Data_7_BIT
5027
#define C4TDB1_Data_8_MASK 0xFF000000
5028
#define CAN4TDB1_Data_8_MASK C4TDB1_Data_8_MASK
5029
#define C4TDB1_Data_8_BIT 24
5030
#define CAN4TDB1_Data_8_BIT C4TDB1_Data_8_BIT
5031
 
5032
#define C4TFI2 (*(volatile unsigned long *)0xE0050040)
5033
#define CAN4TFI2 C4TFI2
5034
#define C4TFI2_OFFSET 0x40
5035
#define CAN4TFI2_OFFSET C4TFI2_OFFSET
5036
#define C4TFI2_PRIO_MASK 0xFF
5037
#define CAN4TFI2_PRIO_MASK C4TFI2_PRIO_MASK
5038
#define C4TFI2_PRIO_BIT 0
5039
#define CAN4TFI2_PRIO_BIT C4TFI2_PRIO_BIT
5040
#define C4TFI2_DLC_MASK 0xF0000
5041
#define CAN4TFI2_DLC_MASK C4TFI2_DLC_MASK
5042
#define C4TFI2_DLC_BIT 16
5043
#define CAN4TFI2_DLC_BIT C4TFI2_DLC_BIT
5044
#define C4TFI2_RTR_MASK 0x40000000
5045
#define CAN4TFI2_RTR_MASK C4TFI2_RTR_MASK
5046
#define C4TFI2_RTR 0x40000000
5047
#define CAN4TFI2_RTR C4TFI2_RTR
5048
#define C4TFI2_RTR_BIT 30
5049
#define CAN4TFI2_RTR_BIT C4TFI2_RTR_BIT
5050
#define C4TFI2_FF_MASK 0x80000000
5051
#define CAN4TFI2_FF_MASK C4TFI2_FF_MASK
5052
#define C4TFI2_FF 0x80000000
5053
#define CAN4TFI2_FF C4TFI2_FF
5054
#define C4TFI2_FF_BIT 31
5055
#define CAN4TFI2_FF_BIT C4TFI2_FF_BIT
5056
 
5057
#define C4TID2 (*(volatile unsigned long *)0xE0050044)
5058
#define CAN4TID2 C4TID2
5059
#define C4TID2_OFFSET 0x44
5060
#define CAN4TID2_OFFSET C4TID2_OFFSET
5061
#define C4TID2_ID_MASK 0x7FF
5062
#define CAN4TID2_ID_MASK C4TID2_ID_MASK
5063
#define C4TID2_ID_BIT 0
5064
#define CAN4TID2_ID_BIT C4TID2_ID_BIT
5065
 
5066
#define C4TDA2 (*(volatile unsigned long *)0xE0050048)
5067
#define CAN4TDA2 C4TDA2
5068
#define C4TDA2_OFFSET 0x48
5069
#define CAN4TDA2_OFFSET C4TDA2_OFFSET
5070
#define C4TDA2_Data_1_MASK 0xFF
5071
#define CAN4TDA2_Data_1_MASK C4TDA2_Data_1_MASK
5072
#define C4TDA2_Data_1_BIT 0
5073
#define CAN4TDA2_Data_1_BIT C4TDA2_Data_1_BIT
5074
#define C4TDA2_Data_2_MASK 0xFF00
5075
#define CAN4TDA2_Data_2_MASK C4TDA2_Data_2_MASK
5076
#define C4TDA2_Data_2_BIT 8
5077
#define CAN4TDA2_Data_2_BIT C4TDA2_Data_2_BIT
5078
#define C4TDA2_Data_3_MASK 0xFF0000
5079
#define CAN4TDA2_Data_3_MASK C4TDA2_Data_3_MASK
5080
#define C4TDA2_Data_3_BIT 16
5081
#define CAN4TDA2_Data_3_BIT C4TDA2_Data_3_BIT
5082
#define C4TDA2_Data_4_MASK 0xFF000000
5083
#define CAN4TDA2_Data_4_MASK C4TDA2_Data_4_MASK
5084
#define C4TDA2_Data_4_BIT 24
5085
#define CAN4TDA2_Data_4_BIT C4TDA2_Data_4_BIT
5086
 
5087
#define C4TDB2 (*(volatile unsigned long *)0xE005004C)
5088
#define CAN4TDB2 C4TDB2
5089
#define C4TDB2_OFFSET 0x4C
5090
#define CAN4TDB2_OFFSET C4TDB2_OFFSET
5091
#define C4TDB2_Data_5_MASK 0xFF
5092
#define CAN4TDB2_Data_5_MASK C4TDB2_Data_5_MASK
5093
#define C4TDB2_Data_5_BIT 0
5094
#define CAN4TDB2_Data_5_BIT C4TDB2_Data_5_BIT
5095
#define C4TDB2_Data_6_MASK 0xFF00
5096
#define CAN4TDB2_Data_6_MASK C4TDB2_Data_6_MASK
5097
#define C4TDB2_Data_6_BIT 8
5098
#define CAN4TDB2_Data_6_BIT C4TDB2_Data_6_BIT
5099
#define C4TDB2_Data_7_MASK 0xFF0000
5100
#define CAN4TDB2_Data_7_MASK C4TDB2_Data_7_MASK
5101
#define C4TDB2_Data_7_BIT 16
5102
#define CAN4TDB2_Data_7_BIT C4TDB2_Data_7_BIT
5103
#define C4TDB2_Data_8_MASK 0xFF000000
5104
#define CAN4TDB2_Data_8_MASK C4TDB2_Data_8_MASK
5105
#define C4TDB2_Data_8_BIT 24
5106
#define CAN4TDB2_Data_8_BIT C4TDB2_Data_8_BIT
5107
 
5108
#define C4TFI3 (*(volatile unsigned long *)0xE0050050)
5109
#define CAN4TFI3 C4TFI3
5110
#define C4TFI3_OFFSET 0x50
5111
#define CAN4TFI3_OFFSET C4TFI3_OFFSET
5112
#define C4TFI3_PRIO_MASK 0xFF
5113
#define CAN4TFI3_PRIO_MASK C4TFI3_PRIO_MASK
5114
#define C4TFI3_PRIO_BIT 0
5115
#define CAN4TFI3_PRIO_BIT C4TFI3_PRIO_BIT
5116
#define C4TFI3_DLC_MASK 0xF0000
5117
#define CAN4TFI3_DLC_MASK C4TFI3_DLC_MASK
5118
#define C4TFI3_DLC_BIT 16
5119
#define CAN4TFI3_DLC_BIT C4TFI3_DLC_BIT
5120
#define C4TFI3_RTR_MASK 0x40000000
5121
#define CAN4TFI3_RTR_MASK C4TFI3_RTR_MASK
5122
#define C4TFI3_RTR 0x40000000
5123
#define CAN4TFI3_RTR C4TFI3_RTR
5124
#define C4TFI3_RTR_BIT 30
5125
#define CAN4TFI3_RTR_BIT C4TFI3_RTR_BIT
5126
#define C4TFI3_FF_MASK 0x80000000
5127
#define CAN4TFI3_FF_MASK C4TFI3_FF_MASK
5128
#define C4TFI3_FF 0x80000000
5129
#define CAN4TFI3_FF C4TFI3_FF
5130
#define C4TFI3_FF_BIT 31
5131
#define CAN4TFI3_FF_BIT C4TFI3_FF_BIT
5132
 
5133
#define C4TID3 (*(volatile unsigned long *)0xE0050054)
5134
#define CAN4TID3 C4TID3
5135
#define C4TID3_OFFSET 0x54
5136
#define CAN4TID3_OFFSET C4TID3_OFFSET
5137
#define C4TID3_ID_MASK 0x7FF
5138
#define CAN4TID3_ID_MASK C4TID3_ID_MASK
5139
#define C4TID3_ID_BIT 0
5140
#define CAN4TID3_ID_BIT C4TID3_ID_BIT
5141
 
5142
#define C4TDA3 (*(volatile unsigned long *)0xE0050058)
5143
#define CAN4TDA3 C4TDA3
5144
#define C4TDA3_OFFSET 0x58
5145
#define CAN4TDA3_OFFSET C4TDA3_OFFSET
5146
#define C4TDA3_Data_1_MASK 0xFF
5147
#define CAN4TDA3_Data_1_MASK C4TDA3_Data_1_MASK
5148
#define C4TDA3_Data_1_BIT 0
5149
#define CAN4TDA3_Data_1_BIT C4TDA3_Data_1_BIT
5150
#define C4TDA3_Data_2_MASK 0xFF00
5151
#define CAN4TDA3_Data_2_MASK C4TDA3_Data_2_MASK
5152
#define C4TDA3_Data_2_BIT 8
5153
#define CAN4TDA3_Data_2_BIT C4TDA3_Data_2_BIT
5154
#define C4TDA3_Data_3_MASK 0xFF0000
5155
#define CAN4TDA3_Data_3_MASK C4TDA3_Data_3_MASK
5156
#define C4TDA3_Data_3_BIT 16
5157
#define CAN4TDA3_Data_3_BIT C4TDA3_Data_3_BIT
5158
#define C4TDA3_Data_4_MASK 0xFF000000
5159
#define CAN4TDA3_Data_4_MASK C4TDA3_Data_4_MASK
5160
#define C4TDA3_Data_4_BIT 24
5161
#define CAN4TDA3_Data_4_BIT C4TDA3_Data_4_BIT
5162
 
5163
#define C4TDB3 (*(volatile unsigned long *)0xE005005C)
5164
#define CAN4TDB3 C4TDB3
5165
#define C4TDB3_OFFSET 0x5C
5166
#define CAN4TDB3_OFFSET C4TDB3_OFFSET
5167
#define C4TDB3_Data_5_MASK 0xFF
5168
#define CAN4TDB3_Data_5_MASK C4TDB3_Data_5_MASK
5169
#define C4TDB3_Data_5_BIT 0
5170
#define CAN4TDB3_Data_5_BIT C4TDB3_Data_5_BIT
5171
#define C4TDB3_Data_6_MASK 0xFF00
5172
#define CAN4TDB3_Data_6_MASK C4TDB3_Data_6_MASK
5173
#define C4TDB3_Data_6_BIT 8
5174
#define CAN4TDB3_Data_6_BIT C4TDB3_Data_6_BIT
5175
#define C4TDB3_Data_7_MASK 0xFF0000
5176
#define CAN4TDB3_Data_7_MASK C4TDB3_Data_7_MASK
5177
#define C4TDB3_Data_7_BIT 16
5178
#define CAN4TDB3_Data_7_BIT C4TDB3_Data_7_BIT
5179
#define C4TDB3_Data_8_MASK 0xFF000000
5180
#define CAN4TDB3_Data_8_MASK C4TDB3_Data_8_MASK
5181
#define C4TDB3_Data_8_BIT 24
5182
#define CAN4TDB3_Data_8_BIT C4TDB3_Data_8_BIT
5183
 
5184
#define SSP_BASE 0xE005C000
5185
 
5186
#define SSPCR0 (*(volatile unsigned long *)0xE005C000)
5187
#define SSPCR0_OFFSET 0x0
5188
#define SSPCR0_SCR_MASK 0xFF00
5189
#define SSPCR0_SCR_BIT 8
5190
#define SSPCR0_CPHA_MASK 0x80
5191
#define SSPCR0_CPHA 0x80
5192
#define SSPCR0_CPHA_BIT 7
5193
#define SSPCR0_CPOL_MASK 0x40
5194
#define SSPCR0_CPOL 0x40
5195
#define SSPCR0_CPOL_BIT 6
5196
#define SSPCR0_FRF_MASK 0x30
5197
#define SSPCR0_FRF_BIT 4
5198
#define SSPCR0_DSS_MASK 0xF
5199
#define SSPCR0_DSS_BIT 0
5200
 
5201
#define SSPCR1 (*(volatile unsigned long *)0xE005C004)
5202
#define SSPCR1_OFFSET 0x4
5203
#define SSPCR1_SOD_MASK 0x8
5204
#define SSPCR1_SOD 0x8
5205
#define SSPCR1_SOD_BIT 3
5206
#define SSPCR1_MS_MASK 0x4
5207
#define SSPCR1_MS 0x4
5208
#define SSPCR1_MS_BIT 2
5209
#define SSPCR1_SSE_MASK 0x2
5210
#define SSPCR1_SSE 0x2
5211
#define SSPCR1_SSE_BIT 1
5212
#define SSPCR1_LBE_MASK 0x1
5213
#define SSPCR1_LBE 0x1
5214
#define SSPCR1_LBE_BIT 0
5215
 
5216
#define SSPDR (*(volatile unsigned long *)0xE005C008)
5217
#define SSPDR_OFFSET 0x8
5218
 
5219
#define SSPSR (*(volatile unsigned long *)0xE005C00C)
5220
#define SSPSR_OFFSET 0xC
5221
#define SSPSR_BSY_MASK 0x10
5222
#define SSPSR_BSY 0x10
5223
#define SSPSR_BSY_BIT 4
5224
#define SSPSR_RFF_MASK 0x8
5225
#define SSPSR_RFF 0x8
5226
#define SSPSR_RFF_BIT 3
5227
#define SSPSR_RNE_MASK 0x4
5228
#define SSPSR_RNE 0x4
5229
#define SSPSR_RNE_BIT 2
5230
#define SSPSR_TNF_MASK 0x2
5231
#define SSPSR_TNF 0x2
5232
#define SSPSR_TNF_BIT 1
5233
#define SSPSR_TFE_MASK 0x1
5234
#define SSPSR_TFE 0x1
5235
#define SSPSR_TFE_BIT 0
5236
 
5237
#define SSPCPSR (*(volatile unsigned long *)0xE005C010)
5238
#define SSPCPSR_OFFSET 0x10
5239
#define SSPCPSR_CPSDVSR_MASK 0xFF
5240
#define SSPCPSR_CPSDVSR_BIT 0
5241
 
5242
#define SSPIMSC (*(volatile unsigned long *)0xE005C014)
5243
#define SSPIMSC_OFFSET 0x14
5244
#define SSPIMSC_TXIM_MASK 0x8
5245
#define SSPIMSC_TXIM 0x8
5246
#define SSPIMSC_TXIM_BIT 3
5247
#define SSPIMSC_RXIM_MASK 0x4
5248
#define SSPIMSC_RXIM 0x4
5249
#define SSPIMSC_RXIM_BIT 2
5250
#define SSPIMSC_RTIM_MASK 0x2
5251
#define SSPIMSC_RTIM 0x2
5252
#define SSPIMSC_RTIM_BIT 1
5253
#define SSPIMSC_RORIM_MASK 0x1
5254
#define SSPIMSC_RORIM 0x1
5255
#define SSPIMSC_RORIM_BIT 0
5256
 
5257
#define SSPRIS (*(volatile unsigned long *)0xE005C018)
5258
#define SSPRIS_OFFSET 0x18
5259
#define SSPRIS_TXRIS_MASK 0x8
5260
#define SSPRIS_TXRIS 0x8
5261
#define SSPRIS_TXRIS_BIT 3
5262
#define SSPRIS_RXRIS_MASK 0x4
5263
#define SSPRIS_RXRIS 0x4
5264
#define SSPRIS_RXRIS_BIT 2
5265
#define SSPRIS_RTRIS_MASK 0x2
5266
#define SSPRIS_RTRIS 0x2
5267
#define SSPRIS_RTRIS_BIT 1
5268
#define SSPRIS_RORRIS_MASK 0x1
5269
#define SSPRIS_RORRIS 0x1
5270
#define SSPRIS_RORRIS_BIT 0
5271
 
5272
#define SSPMIS (*(volatile unsigned long *)0xE005C01C)
5273
#define SSPMIS_OFFSET 0x1C
5274
#define SSPMIS_TXMIS_MASK 0x8
5275
#define SSPMIS_TXMIS 0x8
5276
#define SSPMIS_TXMIS_BIT 3
5277
#define SSPMIS_RXMIS_MASK 0x4
5278
#define SSPMIS_RXMIS 0x4
5279
#define SSPMIS_RXMIS_BIT 2
5280
#define SSPMIS_RTMIS_MASK 0x2
5281
#define SSPMIS_RTMIS 0x2
5282
#define SSPMIS_RTMIS_BIT 1
5283
#define SSPMIS_RORMIS_MASK 0x1
5284
#define SSPMIS_RORMIS 0x1
5285
#define SSPMIS_RORMIS_BIT 0
5286
 
5287
#define SSPICR (*(volatile unsigned long *)0xE005C020)
5288
#define SSPICR_OFFSET 0x20
5289
#define SSPICR_RTIC_MASK 0x2
5290
#define SSPICR_RTIC 0x2
5291
#define SSPICR_RTIC_BIT 1
5292
#define SSPICR_RORIC_MASK 0x1
5293
#define SSPICR_RORIC 0x1
5294
#define SSPICR_RORIC_BIT 0
5295
 
5296
#define SCB_BASE 0xE01FC000
5297
 
5298
#define MAMCR (*(volatile unsigned char *)0xE01FC000)
5299
#define MAMCR_OFFSET 0x0
5300
#define MAMCR_MAM_mode_control_MASK 0x3
5301
#define MAMCR_MAM_mode_control_BIT 0
5302
 
5303
#define MAMTIM (*(volatile unsigned char *)0xE01FC004)
5304
#define MAMTIM_OFFSET 0x4
5305
#define MAMTIM_MAM_fetch_cycle_timing_MASK 0x7
5306
#define MAMTIM_MAM_fetch_cycle_timing_BIT 0
5307
 
5308
#define MEMMAP (*(volatile unsigned char *)0xE01FC040)
5309
#define MEMMAP_OFFSET 0x40
5310
#define MEMMAP_MAP_MASK 0x3
5311
#define MEMMAP_MAP_BIT 0
5312
 
5313
#define PLLCON (*(volatile unsigned char *)0xE01FC080)
5314
#define PLLCON_OFFSET 0x80
5315
#define PLLCON_PLLE_MASK 0x1
5316
#define PLLCON_PLLE 0x1
5317
#define PLLCON_PLLE_BIT 0
5318
#define PLLCON_PLLC_MASK 0x2
5319
#define PLLCON_PLLC 0x2
5320
#define PLLCON_PLLC_BIT 1
5321
 
5322
#define PLLCFG (*(volatile unsigned char *)0xE01FC084)
5323
#define PLLCFG_OFFSET 0x84
5324
#define PLLCFG_MSEL_MASK 0x1F
5325
#define PLLCFG_MSEL_BIT 0
5326
#define PLLCFG_PSEL_MASK 0x60
5327
#define PLLCFG_PSEL_BIT 5
5328
 
5329
#define PLLSTAT (*(volatile unsigned short *)0xE01FC088)
5330
#define PLLSTAT_OFFSET 0x88
5331
#define PLLSTAT_MSEL_MASK 0x1F
5332
#define PLLSTAT_MSEL_BIT 0
5333
#define PLLSTAT_PSEL_MASK 0x60
5334
#define PLLSTAT_PSEL_BIT 5
5335
#define PLLSTAT_PLLE_MASK 0x100
5336
#define PLLSTAT_PLLE 0x100
5337
#define PLLSTAT_PLLE_BIT 8
5338
#define PLLSTAT_PLLC_MASK 0x200
5339
#define PLLSTAT_PLLC 0x200
5340
#define PLLSTAT_PLLC_BIT 9
5341
#define PLLSTAT_PLOCK_MASK 0x400
5342
#define PLLSTAT_PLOCK 0x400
5343
#define PLLSTAT_PLOCK_BIT 10
5344
 
5345
#define PLLFEED (*(volatile unsigned char *)0xE01FC08C)
5346
#define PLLFEED_OFFSET 0x8C
5347
 
5348
#define PCON (*(volatile unsigned char *)0xE01FC0C0)
5349
#define PCON_OFFSET 0xC0
5350
#define PCON_IDL_MASK 0x1
5351
#define PCON_IDL 0x1
5352
#define PCON_IDL_BIT 0
5353
#define PCON_PD_MASK 0x2
5354
#define PCON_PD 0x2
5355
#define PCON_PD_BIT 1
5356
 
5357
#define PCONP (*(volatile unsigned long *)0xE01FC0C4)
5358
#define PCONP_OFFSET 0xC4
5359
#define PCONP_PCTIM0_MASK 0x2
5360
#define PCONP_PCTIM0 0x2
5361
#define PCONP_PCTIM0_BIT 1
5362
#define PCONP_PCTIM1_MASK 0x4
5363
#define PCONP_PCTIM1 0x4
5364
#define PCONP_PCTIM1_BIT 2
5365
#define PCONP_PCUART0_MASK 0x8
5366
#define PCONP_PCUART0 0x8
5367
#define PCONP_PCUART0_BIT 3
5368
#define PCONP_PCUART1_MASK 0x10
5369
#define PCONP_PCUART1 0x10
5370
#define PCONP_PCUART1_BIT 4
5371
#define PCONP_PCPWM0_MASK 0x20
5372
#define PCONP_PCPWM0 0x20
5373
#define PCONP_PCPWM0_BIT 5
5374
#define PCONP_PCI2C_MASK 0x80
5375
#define PCONP_PCI2C 0x80
5376
#define PCONP_PCI2C_BIT 7
5377
#define PCONP_PCSPI0_MASK 0x100
5378
#define PCONP_PCSPI0 0x100
5379
#define PCONP_PCSPI0_BIT 8
5380
#define PCONP_PCRTC_MASK 0x200
5381
#define PCONP_PCRTC 0x200
5382
#define PCONP_PCRTC_BIT 9
5383
#define PCONP_PCSPI1_MASK 0x400
5384
#define PCONP_PCSPI1 0x400
5385
#define PCONP_PCSPI1_BIT 10
5386
#define PCONP_PCAD_MASK 0x1000
5387
#define PCONP_PCAD 0x1000
5388
#define PCONP_PCAD_BIT 12
5389
#define PCONP_PCAN1_MASK 0x2000
5390
#define PCONP_PCAN1 0x2000
5391
#define PCONP_PCAN1_BIT 13
5392
#define PCONP_PCAN2_MASK 0x4000
5393
#define PCONP_PCAN2 0x4000
5394
#define PCONP_PCAN2_BIT 14
5395
#define PCONP_PCAN3_MASK 0x8000
5396
#define PCONP_PCAN3 0x8000
5397
#define PCONP_PCAN3_BIT 15
5398
#define PCONP_PCAN4_MASK 0x10000
5399
#define PCONP_PCAN4 0x10000
5400
#define PCONP_PCAN4_BIT 16
5401
 
5402
#define VPBDIV (*(volatile unsigned char *)0xE01FC100)
5403
#define VPBDIV_OFFSET 0x100
5404
#define VPBDIV_VPBDIV_MASK 0x3
5405
#define VPBDIV_VPBDIV_BIT 0
5406
 
5407
#define EXTINT (*(volatile unsigned char *)0xE01FC140)
5408
#define EXTINT_OFFSET 0x140
5409
#define EXTINT_EINT0_MASK 0x1
5410
#define EXTINT_EINT0 0x1
5411
#define EXTINT_EINT0_BIT 0
5412
#define EXTINT_EINT1_MASK 0x2
5413
#define EXTINT_EINT1 0x2
5414
#define EXTINT_EINT1_BIT 1
5415
#define EXTINT_EINT2_MASK 0x4
5416
#define EXTINT_EINT2 0x4
5417
#define EXTINT_EINT2_BIT 2
5418
#define EXTINT_EINT3_MASK 0x8
5419
#define EXTINT_EINT3 0x8
5420
#define EXTINT_EINT3_BIT 3
5421
 
5422
#define EXTWAKE (*(volatile unsigned char *)0xE01FC144)
5423
#define EXTWAKE_OFFSET 0x144
5424
#define EXTWAKE_EXTWAKE0_MASK 0x1
5425
#define EXTWAKE_EXTWAKE0 0x1
5426
#define EXTWAKE_EXTWAKE0_BIT 0
5427
#define EXTWAKE_EXTWAKE1_MASK 0x2
5428
#define EXTWAKE_EXTWAKE1 0x2
5429
#define EXTWAKE_EXTWAKE1_BIT 1
5430
#define EXTWAKE_EXTWAKE2_MASK 0x4
5431
#define EXTWAKE_EXTWAKE2 0x4
5432
#define EXTWAKE_EXTWAKE2_BIT 2
5433
#define EXTWAKE_EXTWAKE3_MASK 0x8
5434
#define EXTWAKE_EXTWAKE3 0x8
5435
#define EXTWAKE_EXTWAKE3_BIT 3
5436
 
5437
#define EXTMODE (*(volatile unsigned char *)0xE01FC148)
5438
#define EXTMODE_OFFSET 0x148
5439
#define EXTMODE_EXTMODE0_MASK 0x1
5440
#define EXTMODE_EXTMODE0 0x1
5441
#define EXTMODE_EXTMODE0_BIT 0
5442
#define EXTMODE_EXTMODE1_MASK 0x2
5443
#define EXTMODE_EXTMODE1 0x2
5444
#define EXTMODE_EXTMODE1_BIT 1
5445
#define EXTMODE_EXTMODE2_MASK 0x4
5446
#define EXTMODE_EXTMODE2 0x4
5447
#define EXTMODE_EXTMODE2_BIT 2
5448
#define EXTMODE_EXTMODE3_MASK 0x8
5449
#define EXTMODE_EXTMODE3 0x8
5450
#define EXTMODE_EXTMODE3_BIT 3
5451
 
5452
#define EXTPOLAR (*(volatile unsigned char *)0xE01FC14C)
5453
#define EXTPOLAR_OFFSET 0x14C
5454
#define EXTPOLAR_EXTPOLAR0_MASK 0x1
5455
#define EXTPOLAR_EXTPOLAR0 0x1
5456
#define EXTPOLAR_EXTPOLAR0_BIT 0
5457
#define EXTPOLAR_EXTPOLAR1_MASK 0x2
5458
#define EXTPOLAR_EXTPOLAR1 0x2
5459
#define EXTPOLAR_EXTPOLAR1_BIT 1
5460
#define EXTPOLAR_EXTPOLAR2_MASK 0x4
5461
#define EXTPOLAR_EXTPOLAR2 0x4
5462
#define EXTPOLAR_EXTPOLAR2_BIT 2
5463
#define EXTPOLAR_EXTPOLAR3_MASK 0x8
5464
#define EXTPOLAR_EXTPOLAR3 0x8
5465
#define EXTPOLAR_EXTPOLAR3_BIT 3
5466
 
5467
#define VIC_BASE 0xFFFFF000
5468
 
5469
#define VICIRQStatus (*(volatile unsigned long *)0xFFFFF000)
5470
#define VICIRQStatus_OFFSET 0x0
5471
 
5472
#define VICFIQStatus (*(volatile unsigned long *)0xFFFFF004)
5473
#define VICFIQStatus_OFFSET 0x4
5474
 
5475
#define VICRawIntr (*(volatile unsigned long *)0xFFFFF008)
5476
#define VICRawIntr_OFFSET 0x8
5477
 
5478
#define VICIntSelect (*(volatile unsigned long *)0xFFFFF00C)
5479
#define VICIntSelect_OFFSET 0xC
5480
 
5481
#define VICIntEnable (*(volatile unsigned long *)0xFFFFF010)
5482
#define VICIntEnable_OFFSET 0x10
5483
 
5484
#define VICIntEnClr (*(volatile unsigned long *)0xFFFFF014)
5485
#define VICIntEnClr_OFFSET 0x14
5486
 
5487
#define VICSoftInt (*(volatile unsigned long *)0xFFFFF018)
5488
#define VICSoftInt_OFFSET 0x18
5489
 
5490
#define VICSoftIntClear (*(volatile unsigned long *)0xFFFFF01C)
5491
#define VICSoftIntClear_OFFSET 0x1C
5492
 
5493
#define VICProtection (*(volatile unsigned long *)0xFFFFF020)
5494
#define VICProtection_OFFSET 0x20
5495
 
5496
#define VICVectAddr (*(volatile unsigned long *)0xFFFFF030)
5497
#define VICVectAddr_OFFSET 0x30
5498
 
5499
#define VICDefVectAddr (*(volatile unsigned long *)0xFFFFF034)
5500
#define VICDefVectAddr_OFFSET 0x34
5501
 
5502
#define VICVectAddr0 (*(volatile unsigned long *)0xFFFFF100)
5503
#define VICVectAddr0_OFFSET 0x100
5504
 
5505
#define VICVectAddr1 (*(volatile unsigned long *)0xFFFFF104)
5506
#define VICVectAddr1_OFFSET 0x104
5507
 
5508
#define VICVectAddr2 (*(volatile unsigned long *)0xFFFFF108)
5509
#define VICVectAddr2_OFFSET 0x108
5510
 
5511
#define VICVectAddr3 (*(volatile unsigned long *)0xFFFFF10C)
5512
#define VICVectAddr3_OFFSET 0x10C
5513
 
5514
#define VICVectAddr4 (*(volatile unsigned long *)0xFFFFF110)
5515
#define VICVectAddr4_OFFSET 0x110
5516
 
5517
#define VICVectAddr5 (*(volatile unsigned long *)0xFFFFF114)
5518
#define VICVectAddr5_OFFSET 0x114
5519
 
5520
#define VICVectAddr6 (*(volatile unsigned long *)0xFFFFF118)
5521
#define VICVectAddr6_OFFSET 0x118
5522
 
5523
#define VICVectAddr7 (*(volatile unsigned long *)0xFFFFF11C)
5524
#define VICVectAddr7_OFFSET 0x11C
5525
 
5526
#define VICVectAddr8 (*(volatile unsigned long *)0xFFFFF120)
5527
#define VICVectAddr8_OFFSET 0x120
5528
 
5529
#define VICVectAddr9 (*(volatile unsigned long *)0xFFFFF124)
5530
#define VICVectAddr9_OFFSET 0x124
5531
 
5532
#define VICVectAddr10 (*(volatile unsigned long *)0xFFFFF128)
5533
#define VICVectAddr10_OFFSET 0x128
5534
 
5535
#define VICVectAddr11 (*(volatile unsigned long *)0xFFFFF12C)
5536
#define VICVectAddr11_OFFSET 0x12C
5537
 
5538
#define VICVectAddr12 (*(volatile unsigned long *)0xFFFFF130)
5539
#define VICVectAddr12_OFFSET 0x130
5540
 
5541
#define VICVectAddr13 (*(volatile unsigned long *)0xFFFFF134)
5542
#define VICVectAddr13_OFFSET 0x134
5543
 
5544
#define VICVectAddr14 (*(volatile unsigned long *)0xFFFFF138)
5545
#define VICVectAddr14_OFFSET 0x138
5546
 
5547
#define VICVectAddr15 (*(volatile unsigned long *)0xFFFFF13C)
5548
#define VICVectAddr15_OFFSET 0x13C
5549
 
5550
#define VICVectCntl0 (*(volatile unsigned long *)0xFFFFF200)
5551
#define VICVectCntl0_OFFSET 0x200
5552
 
5553
#define VICVectCntl1 (*(volatile unsigned long *)0xFFFFF204)
5554
#define VICVectCntl1_OFFSET 0x204
5555
 
5556
#define VICVectCntl2 (*(volatile unsigned long *)0xFFFFF208)
5557
#define VICVectCntl2_OFFSET 0x208
5558
 
5559
#define VICVectCntl3 (*(volatile unsigned long *)0xFFFFF20C)
5560
#define VICVectCntl3_OFFSET 0x20C
5561
 
5562
#define VICVectCntl4 (*(volatile unsigned long *)0xFFFFF210)
5563
#define VICVectCntl4_OFFSET 0x210
5564
 
5565
#define VICVectCntl5 (*(volatile unsigned long *)0xFFFFF214)
5566
#define VICVectCntl5_OFFSET 0x214
5567
 
5568
#define VICVectCntl6 (*(volatile unsigned long *)0xFFFFF218)
5569
#define VICVectCntl6_OFFSET 0x218
5570
 
5571
#define VICVectCntl7 (*(volatile unsigned long *)0xFFFFF21C)
5572
#define VICVectCntl7_OFFSET 0x21C
5573
 
5574
#define VICVectCntl8 (*(volatile unsigned long *)0xFFFFF220)
5575
#define VICVectCntl8_OFFSET 0x220
5576
 
5577
#define VICVectCntl9 (*(volatile unsigned long *)0xFFFFF224)
5578
#define VICVectCntl9_OFFSET 0x224
5579
 
5580
#define VICVectCntl10 (*(volatile unsigned long *)0xFFFFF228)
5581
#define VICVectCntl10_OFFSET 0x228
5582
 
5583
#define VICVectCntl11 (*(volatile unsigned long *)0xFFFFF22C)
5584
#define VICVectCntl11_OFFSET 0x22C
5585
 
5586
#define VICVectCntl12 (*(volatile unsigned long *)0xFFFFF230)
5587
#define VICVectCntl12_OFFSET 0x230
5588
 
5589
#define VICVectCntl13 (*(volatile unsigned long *)0xFFFFF234)
5590
#define VICVectCntl13_OFFSET 0x234
5591
 
5592
#define VICVectCntl14 (*(volatile unsigned long *)0xFFFFF238)
5593
#define VICVectCntl14_OFFSET 0x238
5594
 
5595
#define VICVectCntl15 (*(volatile unsigned long *)0xFFFFF23C)
5596
#define VICVectCntl15_OFFSET 0x23C
5597
 
5598
 
5599
#endif

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.