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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [ARM7_LPC2368_Eclipse/] [RTOSDemo/] [webserver/] [emac.c] - Blame information for rev 867

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1 577 jeremybenn
/******************************************************************
2
 *****                                                        *****
3
 *****  Name: cs8900.c                                        *****
4
 *****  Ver.: 1.0                                             *****
5
 *****  Date: 07/05/2001                                      *****
6
 *****  Auth: Andreas Dannenberg                              *****
7
 *****        HTWK Leipzig                                    *****
8
 *****        university of applied sciences                  *****
9
 *****        Germany                                         *****
10
 *****  Func: ethernet packet-driver for use with LAN-        *****
11
 *****        controller CS8900 from Crystal/Cirrus Logic     *****
12
 *****                                                        *****
13
 *****  Keil: Module modified for use with Philips            *****
14
 *****        LPC2378 EMAC Ethernet controller                *****
15
 *****                                                        *****
16
 ******************************************************************/
17
 
18
/* Adapted from file originally written by Andreas Dannenberg.  Supplied with permission. */
19
 
20
#include "FreeRTOS.h"
21
#include "semphr.h" 
22
#include "task.h"
23
#include "emac.h"
24
 
25
/* The semaphore used to wake the uIP task when data arives. */
26
xSemaphoreHandle xEMACSemaphore = NULL;
27
 
28
static unsigned short *rptr;
29
static unsigned short *tptr;
30
 
31
// easyWEB internal function
32
// help function to swap the byte order of a WORD
33
 
34
static unsigned short SwapBytes(unsigned short Data)
35
{
36
  return (Data >> 8) | (Data << 8);
37
}
38
 
39
// Keil: function added to write PHY
40
void write_PHY (int PhyReg, int Value)
41
{
42
  unsigned int tout;
43
 
44
  MAC_MADR = DP83848C_DEF_ADR | PhyReg;
45
  MAC_MWTD = Value;
46
 
47
  /* Wait utill operation completed */
48
  tout = 0;
49
  for (tout = 0; tout < MII_WR_TOUT; tout++) {
50
    if ((MAC_MIND & MIND_BUSY) == 0) {
51
      break;
52
    }
53
  }
54
}
55
 
56
 
57
// Keil: function added to read PHY
58
unsigned short read_PHY (unsigned char PhyReg)
59
{
60
  unsigned int tout;
61
 
62
  MAC_MADR = DP83848C_DEF_ADR | PhyReg;
63
  MAC_MCMD = MCMD_READ;
64
 
65
  /* Wait until operation completed */
66
  tout = 0;
67
  for (tout = 0; tout < MII_RD_TOUT; tout++) {
68
    if ((MAC_MIND & MIND_BUSY) == 0) {
69
      break;
70
    }
71
  }
72
  MAC_MCMD = 0;
73
  return (MAC_MRDD);
74
}
75
 
76
 
77
// Keil: function added to initialize Rx Descriptors
78
void rx_descr_init (void)
79
{
80
  unsigned int i;
81
 
82
  for (i = 0; i < NUM_RX_FRAG; i++) {
83
    RX_DESC_PACKET(i)  = RX_BUF(i);
84
    RX_DESC_CTRL(i)    = RCTRL_INT | (ETH_FRAG_SIZE-1);
85
    RX_STAT_INFO(i)    = 0;
86
    RX_STAT_HASHCRC(i) = 0;
87
  }
88
 
89
  /* Set EMAC Receive Descriptor Registers. */
90
  MAC_RXDESCRIPTOR    = RX_DESC_BASE;
91
  MAC_RXSTATUS        = RX_STAT_BASE;
92
  MAC_RXDESCRIPTORNUM = NUM_RX_FRAG-1;
93
 
94
  /* Rx Descriptors Point to 0 */
95
  MAC_RXCONSUMEINDEX  = 0;
96
}
97
 
98
 
99
// Keil: function added to initialize Tx Descriptors
100
void tx_descr_init (void) {
101
  unsigned int i;
102
 
103
  for (i = 0; i < NUM_TX_FRAG; i++) {
104
    TX_DESC_PACKET(i) = TX_BUF(i);
105
    TX_DESC_CTRL(i)   = 0;
106
    TX_STAT_INFO(i)   = 0;
107
  }
108
 
109
  /* Set EMAC Transmit Descriptor Registers. */
110
  MAC_TXDESCRIPTOR    = TX_DESC_BASE;
111
  MAC_TXSTATUS        = TX_STAT_BASE;
112
  MAC_TXDESCRIPTORNUM = NUM_TX_FRAG-1;
113
 
114
  /* Tx Descriptors Point to 0 */
115
  MAC_TXPRODUCEINDEX  = 0;
116
}
117
 
118
 
119
// configure port-pins for use with LAN-controller,
120
// reset it and send the configuration-sequence
121
 
122
portBASE_TYPE Init_EMAC(void)
123
{
124
portBASE_TYPE xReturn = pdPASS;
125
 
126
// Keil: function modified to access the EMAC
127
// Initializes the EMAC ethernet controller
128
  volatile unsigned int regv,tout,id1,id2;
129
 
130
  /* Enable P1 Ethernet Pins. */
131
  PINSEL2 = configPINSEL2_VALUE;
132
  PINSEL3 = (PINSEL3 & ~0x0000000F) | 0x00000005;
133
 
134
  /* Power Up the EMAC controller. */
135
  PCONP |= 0x40000000;
136
  vTaskDelay( 1 );
137
 
138
  /* Reset all EMAC internal modules. */
139
  MAC_MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX | MAC1_SIM_RES | MAC1_SOFT_RES;
140
  MAC_COMMAND = CR_REG_RES | CR_TX_RES | CR_RX_RES;
141
 
142
  /* A short delay after reset. */
143
  vTaskDelay( 1 );
144
 
145
  /* Initialize MAC control registers. */
146
  MAC_MAC1 = MAC1_PASS_ALL;
147
  MAC_MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;
148
  MAC_MAXF = ETH_MAX_FLEN;
149
  MAC_CLRT = CLRT_DEF;
150
  MAC_IPGR = IPGR_DEF;
151
 
152
  /* Enable Reduced MII interface. */
153
  MAC_COMMAND = CR_RMII | CR_PASS_RUNT_FRM;
154
 
155
  /* Reset Reduced MII Logic. */
156
  MAC_SUPP = SUPP_RES_RMII;
157
  MAC_SUPP = 0;
158
 
159
  /* Put the DP83848C in reset mode */
160
  write_PHY (PHY_REG_BMCR, 0x8000);
161
  write_PHY (PHY_REG_BMCR, 0x8000);
162
 
163
  /* Wait for hardware reset to end. */
164
  for (tout = 0; tout < 100; tout++) {
165
    vTaskDelay( 10 );
166
    regv = read_PHY (PHY_REG_BMCR);
167
    if (!(regv & 0x8000)) {
168
      /* Reset complete */
169
      break;
170
    }
171
  }
172
 
173
  /* Check if this is a DP83848C PHY. */
174
  id1 = read_PHY (PHY_REG_IDR1);
175
  id2 = read_PHY (PHY_REG_IDR2);
176
  if (((id1 << 16) | (id2 & 0xFFF0)) == DP83848C_ID) {
177
    /* Configure the PHY device */
178
 
179
    /* Use autonegotiation about the link speed. */
180
    write_PHY (PHY_REG_BMCR, PHY_AUTO_NEG);
181
    /* Wait to complete Auto_Negotiation. */
182
    for (tout = 0; tout < 10; tout++) {
183
      vTaskDelay( 100 );
184
      regv = read_PHY (PHY_REG_BMSR);
185
      if (regv & 0x0020) {
186
        /* Autonegotiation Complete. */
187
        break;
188
      }
189
    }
190
  }
191
  else
192
  {
193
    xReturn = pdFAIL;
194
  }
195
 
196
  /* Check the link status. */
197
  if( xReturn == pdPASS )
198
  {
199
    xReturn = pdFAIL;
200
    for (tout = 0; tout < 10; tout++) {
201
      vTaskDelay( 100 );
202
      regv = read_PHY (PHY_REG_STS);
203
      if (regv & 0x0001) {
204
        /* Link is on. */
205
        xReturn = pdPASS;
206
        break;
207
      }
208
    }
209
  }
210
 
211
  if( xReturn == pdPASS )
212
  {
213
    /* Configure Full/Half Duplex mode. */
214
    if (regv & 0x0004) {
215
      /* Full duplex is enabled. */
216
      MAC_MAC2    |= MAC2_FULL_DUP;
217
      MAC_COMMAND |= CR_FULL_DUP;
218
      MAC_IPGT     = IPGT_FULL_DUP;
219
    }
220
    else {
221
      /* Half duplex mode. */
222
      MAC_IPGT = IPGT_HALF_DUP;
223
    }
224
 
225
    /* Configure 100MBit/10MBit mode. */
226
    if (regv & 0x0002) {
227
      /* 10MBit mode. */
228
      MAC_SUPP = 0;
229
    }
230
    else {
231
      /* 100MBit mode. */
232
      MAC_SUPP = SUPP_SPEED;
233
    }
234
 
235
    /* Set the Ethernet MAC Address registers */
236
    MAC_SA0 = (emacETHADDR0 << 8) | emacETHADDR1;
237
    MAC_SA1 = (emacETHADDR2 << 8) | emacETHADDR3;
238
    MAC_SA2 = (emacETHADDR4 << 8) | emacETHADDR5;
239
 
240
    /* Initialize Tx and Rx DMA Descriptors */
241
    rx_descr_init ();
242
    tx_descr_init ();
243
 
244
    /* Receive Broadcast and Perfect Match Packets */
245
    MAC_RXFILTERCTRL = RFC_UCAST_EN | RFC_BCAST_EN | RFC_PERFECT_EN;
246
 
247
    /* Create the semaphore used ot wake the uIP task. */
248
    vSemaphoreCreateBinary( xEMACSemaphore );
249
 
250
    /* Reset all interrupts */
251
    MAC_INTCLEAR  = 0xFFFF;
252
 
253
    /* Enable receive and transmit mode of MAC Ethernet core */
254
    MAC_COMMAND  |= (CR_RX_EN | CR_TX_EN);
255
    MAC_MAC1     |= MAC1_REC_EN;
256
  }
257
 
258
  return xReturn;
259
}
260
 
261
 
262
// reads a word in little-endian byte order from RX_BUFFER
263
 
264
unsigned short ReadFrame_EMAC(void)
265
{
266
  return (*rptr++);
267
}
268
 
269
// reads a word in big-endian byte order from RX_FRAME_PORT
270
// (useful to avoid permanent byte-swapping while reading
271
// TCP/IP-data)
272
 
273
unsigned short ReadFrameBE_EMAC(void)
274
{
275
  unsigned short ReturnValue;
276
 
277
  ReturnValue = SwapBytes (*rptr++);
278
  return (ReturnValue);
279
}
280
 
281
 
282
// copies bytes from frame port to MCU-memory
283
// NOTES: * an odd number of byte may only be transfered
284
//          if the frame is read to the end!
285
//        * MCU-memory MUST start at word-boundary
286
 
287
void CopyFromFrame_EMAC(void *Dest, unsigned short Size)
288
{
289
  unsigned short * piDest;                       // Keil: Pointer added to correct expression
290
 
291
  piDest = Dest;                                 // Keil: Line added
292
  while (Size > 1) {
293
    *piDest++ = ReadFrame_EMAC();
294
    Size -= 2;
295
  }
296
 
297
  if (Size) {                                         // check for leftover byte...
298
    *(unsigned char *)piDest = (char)ReadFrame_EMAC();// the LAN-Controller will return 0
299
  }                                                   // for the highbyte
300
}
301
 
302
// does a dummy read on frame-I/O-port
303
// NOTE: only an even number of bytes is read!
304
 
305
void DummyReadFrame_EMAC(unsigned short Size)    // discards an EVEN number of bytes
306
{                                                // from RX-fifo
307
  while (Size > 1) {
308
    ReadFrame_EMAC();
309
    Size -= 2;
310
  }
311
}
312
 
313
// Reads the length of the received ethernet frame and checks if the 
314
// destination address is a broadcast message or not
315
// returns the frame length
316
unsigned short StartReadFrame(void) {
317
  unsigned short RxLen;
318
  unsigned int idx;
319
 
320
  idx = MAC_RXCONSUMEINDEX;
321
  RxLen = (RX_STAT_INFO(idx) & RINFO_SIZE) - 3;
322
  rptr = (unsigned short *)RX_DESC_PACKET(idx);
323
  return(RxLen);
324
}
325
 
326
void EndReadFrame(void) {
327
  unsigned int idx;
328
 
329
  /* DMA free packet. */
330
  idx = MAC_RXCONSUMEINDEX;
331
 
332
  if (++idx == NUM_RX_FRAG)
333
    idx = 0;
334
 
335
  MAC_RXCONSUMEINDEX = idx;
336
}
337
 
338
unsigned int CheckFrameReceived(void) {             // Packet received ?
339
 
340
  if (MAC_RXPRODUCEINDEX != MAC_RXCONSUMEINDEX)     // more packets received ?
341
    return(1);
342
  else
343
    return(0);
344
}
345
 
346
unsigned int uiGetEMACRxData( unsigned char *ucBuffer )
347
{
348
unsigned int uiLen = 0;
349
 
350
    if( MAC_RXPRODUCEINDEX != MAC_RXCONSUMEINDEX )
351
    {
352
        uiLen = StartReadFrame();
353
        CopyFromFrame_EMAC( ucBuffer, uiLen );
354
        EndReadFrame();
355
    }
356
 
357
    return uiLen;
358
}
359
 
360
// requests space in EMAC memory for storing an outgoing frame
361
 
362
void RequestSend(void)
363
{
364
  unsigned int idx;
365
 
366
  idx  = MAC_TXPRODUCEINDEX;
367
  tptr = (unsigned short *)TX_DESC_PACKET(idx);
368
}
369
 
370
// check if ethernet controller is ready to accept the
371
// frame we want to send
372
 
373
unsigned int Rdy4Tx(void)
374
{
375
  return (1);   // the ethernet controller transmits much faster
376
}               // than the CPU can load its buffers
377
 
378
 
379
// writes a word in little-endian byte order to TX_BUFFER
380
void WriteFrame_EMAC(unsigned short Data)
381
{
382
  *tptr++ = Data;
383
}
384
 
385
// copies bytes from MCU-memory to frame port
386
// NOTES: * an odd number of byte may only be transfered
387
//          if the frame is written to the end!
388
//        * MCU-memory MUST start at word-boundary
389
 
390
void CopyToFrame_EMAC(void *Source, unsigned int Size)
391
{
392
  unsigned short * piSource;
393
 
394
  piSource = Source;
395
  Size = (Size + 1) & 0xFFFE;    // round Size up to next even number
396
  while (Size > 0) {
397
    WriteFrame_EMAC(*piSource++);
398
    Size -= 2;
399
  }
400
}
401
 
402
void DoSend_EMAC(unsigned short FrameSize)
403
{
404
  unsigned int idx;
405
 
406
  idx = MAC_TXPRODUCEINDEX;
407
  TX_DESC_CTRL(idx) = FrameSize | TCTRL_LAST;
408
  if (++idx == NUM_TX_FRAG) idx = 0;
409
  MAC_TXPRODUCEINDEX = idx;
410
}
411
 

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