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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [ARM7_STR71x_IAR/] [71x_init.s] - Blame information for rev 609

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1 577 jeremybenn
;******************** (C) COPYRIGHT 2003 STMicroelectronics ********************
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;* File Name          : 71x_init.s
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;* Author             : MCD Application Team
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;* Date First Issued  : 06/23/2004
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;* Description        : This is the first code executed after RESET.
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;*                      This code used to initialize system stacks
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;*                      and critical peripherals before entering the C code.
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;*******************************************************************************
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;* History:
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;*  13/01/2006 : V3.1
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;*  24/05/2005 : V3.0
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;*  30/11/2004 : V2.0
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;*  14/07/2004 : V1.3
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;*  01/01/2004 : V1.2
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;*******************************************************************************
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; THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
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; CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
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; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
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; OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
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; OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
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; CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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;*******************************************************************************/
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; --- Standard definitions of mode bits and interrupt (I & F) flags in PSRs
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Mode_USR           EQU   0x10
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Mode_FIQ           EQU   0x11
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Mode_IRQ           EQU   0x12
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Mode_SVC           EQU   0x13
31
Mode_ABT           EQU   0x17
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Mode_UNDEF         EQU   0x1B
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Mode_SYS           EQU   0x1F ; available on ARM Arch 4 and later
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I_Bit              EQU   0x80 ; when I bit is set, IRQ is disabled
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F_Bit              EQU   0x40 ; when F bit is set, FIQ is disabled
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39
 
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EIC_Base_addr      EQU   0xFFFFF800; EIC base address
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ICR_off_addr       EQU   0x00      ; Interrupt Control register offset
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CIPR_off_addr      EQU   0x08      ; Current Interrupt Priority Register offset
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IVR_off_addr       EQU   0x18      ; Interrupt Vector Register offset
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FIR_off_addr       EQU   0x1C      ; Fast Interrupt Register offset
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IER_off_addr       EQU   0x20      ; Interrupt Enable Register offset
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IPR_off_addr       EQU   0x40      ; Interrupt Pending Bit Register offset
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SIR0_off_addr      EQU   0x60      ; Source Interrupt Register 0
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EMI_Base_addr      EQU   0x6C000000; EMI base address
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BCON0_off_addr     EQU   0x00      ; Bank 0 configuration register offset
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BCON1_off_addr     EQU   0x04      ; Bank 1 configuration register offset
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BCON2_off_addr     EQU   0x08      ; Bank 2 configuration register offset
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BCON3_off_addr     EQU   0x0C      ; Bank 3 configuration register offset
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EMI_ENABLE         EQU   0x8000
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EMI_SIZE_16        EQU   0x0001
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GPIO2_Base_addr    EQU   0xE0005000; GPIO2 base address
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PC0_off_addr       EQU   0x00      ; Port Configuration Register 0 offset
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PC1_off_addr       EQU   0x04      ; Port Configuration Register 1 offset
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PC2_off_addr       EQU   0x08      ; Port Configuration Register 2 offset
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PD_off_addr        EQU   0x0C      ; Port Data Register offset
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CPM_Base_addr      EQU   0xA0000040; CPM Base Address
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BOOTCR_off_addr    EQU   0x10      ; CPM - Boot Configuration Register
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FLASH_mask         EQU   0x0000    ; to remap FLASH at 0x0
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RAM_mask           EQU   0x0002    ; to remap RAM at 0x0
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;|----------------------------------------------------------------------------------|
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;| - APB Bridge  (System Peripheral)                                               |
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;|----------------------------------------------------------------------------------|
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APB1_base_addr     EQU   0xC0000000          ; APB Bridge1 Base Address
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APB2_base_addr     EQU   0xE0000000          ; APB Bridge2 Base Address
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CKDIS_off_addr     EQU   0x10                ; APB Bridge1 - Clock Disable  Register
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SWRES_off_addr     EQU   0x14                ; APB Bridge1 - Software Reset Register
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CKDIS1_config_all  EQU   0x27FB              ; To enable/disable clock of all APB1's peripherals
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SWRES1_config_all  EQU   0x27FB              ; To reset all APB1's peripherals
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CKDIS2_config_all  EQU   0x7FDD              ; To enable/disable clock of all APB2's peripherals
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SWRES2_config_all  EQU   0x7FDD              ; To reset all APB2's peripherals
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;---------------------------------------------------------------
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; ?program_start
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;---------------------------------------------------------------
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                MODULE  ?program_start
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                SECTION IRQ_STACK:DATA:NOROOT(3)
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                SECTION FIQ_STACK:DATA:NOROOT(3)
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                SECTION UND_STACK:DATA:NOROOT(3)
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                SECTION ABT_STACK:DATA:NOROOT(3)
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                SECTION SVC_STACK:DATA:NOROOT(3)
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                SECTION CSTACK:DATA:NOROOT(3)
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                SECTION .text:CODE(2)
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                PUBLIC  __iar_program_start
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                EXTERN  ?main
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                EXTERN  ?main
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                CODE32
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99
 
100
;*******************************************************************************
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;*******                         -- MACROS --                            *******
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;*******************************************************************************
103
;*******************************************************************************
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;* Macro Name     : EMI_INIT
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;* Description    : This macro Initialize EMI bank 1: 16-bit 7 wait state
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;* Input          : None.
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;* Output         : None.
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;*******************************************************************************
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EMI_INIT  MACRO
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        LDR     r0, =GPIO2_Base_addr      ; Configure P2.0 -> 3 in AF_PP mode
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        LDR     r2, [r0, #PC0_off_addr]
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        ORR     r2, r2,#0x0000000F
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        STR     r2, [r0, #PC0_off_addr]
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        LDR     r2, [r0, #PC1_off_addr]
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        ORR     r2, r2,#0x0000000F
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        STR     r2, [r0, #PC1_off_addr]
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        LDR     r2, [r0, #PC2_off_addr]
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        ORR     r2, r2,#0x0000000F
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        STR     r2, [r0, #PC2_off_addr]
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        LDR     r0, =EMI_Base_addr
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        LDR     r1, =0x18|EMI_ENABLE|EMI_SIZE_16
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        STR     r1, [r0, #BCON1_off_addr] ; Enable bank 1 16-bit 7 wait state
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        ENDM
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;*******************************************************************************
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;* Macro Name     : EIC_INIT
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;* Description    : This macro Initialize the EIC as following :
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;                 - IRQ disabled
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;                 - FIQ disabled
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;                 - IVR contain the load PC opcode (0xE59FFXXX)
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;                 - Current priority level equal to 0
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;                 - All channels are disabled
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;                 - All channels priority equal to 0
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;                 - All SIR registers contain offset to the related IRQ
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;                   table entry
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;* Input          : None.
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;* Output         : None.
137
;*******************************************************************************
138
EIC_INIT   MACRO
139
 
140
        LDR     r3, =EIC_Base_addr
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        LDR     r4, =0xE59F0000
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        STR     r4, [r3, #IVR_off_addr]; Write the LDR pc,[pc,#offset]
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                                       ; instruction code in IVR[31:16]
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        LDR     r2, =32                ; 32 Channel to initialize
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        LDR     r0, =T0TIMI_Addr       ; Read the address of the IRQs
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                                       ; address table
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        LDR     r1, =0x00000FFF
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        AND     r0,r0,r1
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        LDR     r5, =SIR0_off_addr     ; Read SIR0 address
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        SUB     r4,r0,#8               ; subtract 8 for prefetch
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        LDR     r1, =0xF7E8            ; Add the offset from IVR to 0x00000000
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                                       ; address(IVR address + 7E8 = 0x00000000)
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                                       ; 0xF7E8 used to complete the
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                                       ; LDR pc,[pc,#offset] opcode (0xE59FFXXX)
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        ADD     r1,r4,r1               ; Compute the jump offset from IVR to the
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                                       ; IRQ table entry.
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EIC_INI MOV     r4, r1, LSL #16        ; Left shift the result
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        STR     r4, [r3, r5]           ; Store the result in SIRx register
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        ADD     r1, r1, #4             ; Next IRQ address
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        ADD     r5, r5, #4             ; Next SIR
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        SUBS    r2, r2, #1             ; Decrement the number of SIR registers
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                                       ; to initialize
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        BNE     EIC_INI                ; If more then continue
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        ENDM
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;*******************************************************************************
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;* Macro Name     : PERIPHERAL_INIT
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;* Description    : This macro reset all device peripherals.
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;* Input          : None.
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;* Output         : None.
170
;*******************************************************************************
171
PERIPHERAL_INIT MACRO
172
 
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        LDR     r1, =APB1_base_addr      ; r0= APB1 base address
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        LDR     r2, =APB2_base_addr      ; r0= APB2 base address
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        LDR     r0, =CKDIS1_config_all
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        STRH    r0, [r1, #CKDIS_off_addr]; Clock Disabling for all APB1 peripherals
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        LDR     r0, =CKDIS2_config_all
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        STRH    r0, [r2, #CKDIS_off_addr]; Clock Disabling for all APB2 peripherals
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        LDR     r0, =SWRES1_config_all
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        STRH    r0, [r1, #SWRES_off_addr]; Keep all APB1 peripherals under reset
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        LDR     r0, =SWRES2_config_all
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        STRH    r0, [r2, #SWRES_off_addr]; Keep all APB2 peripherals under reset
183
        MOV     r7, #10                  ; Wait that the selected macrocells exit from reset
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loop1   SUBS    r7, r7, #1
185
        BNE     loop1
186
        MOV     r0, #0
187
        STRH    r0, [r1, #SWRES_off_addr]; Enable all all APB1 peripherals
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        STRH    r0, [r2, #SWRES_off_addr]; Enable all all APB2 peripherals
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        STRH    r0, [r1, #CKDIS_off_addr]; Clock Enabling for all APB1 peripherals
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        STRH    r0, [r2, #CKDIS_off_addr]; Clock Enabling for all APB2 peripherals
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        MOV     r7, #10                  ; Wait that the selected macrocells exit from reset
192
loop2   SUBS    r7, r7, #1
193
        BNE     loop2
194
        ENDM
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;********************************************************************************************
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197
; define remapping
198
; If you need to remap memory before entring the main program
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; uncomment next ligne
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;            #define   remapping
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202
; Then define which memory to remap to address 0x00000000
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;  Uncomment next line if you want to remap RAM
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;         #define  remap_ram
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;  Uncomment next line if you want to remap FLASH
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;         #define remap_flash
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        IMPORT  T0TIMI_Addr
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__iar_program_start
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         LDR     pc, =NextInst
213
NextInst
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                NOP             ; Wait for OSC stabilization
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                NOP
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                NOP
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                NOP
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                NOP
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                NOP
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                NOP
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                NOP
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                NOP
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        MSR     CPSR_c, #Mode_ABT|F_Bit|I_Bit
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        ldr      sp,=SFE(ABT_STACK)     ; End of ABT_STACK
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        MSR     CPSR_c, #Mode_UNDEF|F_Bit|I_Bit
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        ldr      sp,=SFE(UND_STACK)     ; End of UNDEF_STACK
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        MSR     CPSR_c, #Mode_SVC|F_Bit|I_Bit
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       ldr      sp,=SFE(SVC_STACK)      ; End of SVC_STACK
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; Uncomment next ligne if you need to reset all device pripherals
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 ;      PERIPHERAL_INIT           ; Reset all device peripherals
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; Uncomment next ligne if you need to enable the EMI Bank 1
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   ;    EMI_INIT                  ; Initialize EIM Bank 1
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;Uncomment next ligne if you need to initialize the EIC
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        EIC_INIT                  ; Initialize EIC
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;******************************************************************************
245
;REMAPPING
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;Description  : Remapping  memory whether RAM,FLASH
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;               at Address 0x0 after the application has started executing.
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;               Remapping is generally done to allow RAM  to replace FLASH
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;               at 0x0.
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;               the remapping of RAM allow copying of vector table into RAM
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;               To enable the memory remapping uncomment: (see above)
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;               #define  remapping to enable memory remapping
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;                  AND
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;               #define  remap_ram to remap RAM
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;                  OR
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;               #define  remap_flash to remap FLASH
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;******************************************************************************
258
#ifdef remapping
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    #ifdef remap_flash
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        MOV     r0, #FLASH_mask
261
    #endif
262
    #ifdef remap_ram
263
        MOV     r0, #RAM_mask
264
    #endif
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266
        LDR     r1, =CPM_Base_addr
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        LDRH    r2, [r1, #BOOTCR_off_addr]; Read BOOTCR Register
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        BIC     r2, r2, #0x03             ; Reset the two LSB bits of BOOTCR
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        ORR     r2, r2, r0                ; change the two LSB bits of BOOTCR
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        STRH    r2, [r1, #BOOTCR_off_addr]; Write BOOTCR Register
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#endif
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273
        MSR     CPSR_c, #Mode_FIQ|I_Bit; Change to FIQ mode
274
        ldr      sp,=SFE(FIQ_STACK)      ; End of FIQ_STACK
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        MSR     CPSR_c, #Mode_IRQ|I_Bit; Change to IRQ mode
277
        ldr      sp,=SFE(IRQ_STACK)    ; End of IRQ_STACK
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279
        MSR     CPSR_c, #Mode_SYS         ; Change to system mode, Enable IRQ and FIQ
280
       ldr     sp,=SFE(CSTACK)        ; End of CSTACK(user)
281
 
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283
 
284
; --- Now branches to a C lib function that copies RO data from their
285
;     load region to their execute region, create the RW and ZI regions
286
;     then jumps to user C main program.
287
 
288
                ; main() must be called from Supervisor mode
289
                MSR     CPSR_c, #Mode_SVC|F_Bit|I_Bit
290
 
291
        b ?main   ; Note : use B not BL, because an application will
292
                         ; never return this way
293
 
294
        LTORG
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296
        END
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;******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****

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