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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [ARM7_STR71x_IAR/] [71x_vect.s] - Blame information for rev 615

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1 577 jeremybenn
#include "FreeRTOSConfig.h"
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;******************** (C) COPYRIGHT 2003 STMicroelectronics ********************
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;* File Name          : 71x_vect.s
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;* Author             : MCD Application Team
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;* Date First Issued  : 16/05/2003
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;* Description        : This file used to initialize the exception and IRQ
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;*                      vectors, and to enter/return to/from exceptions handlers.
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;*******************************************************************************
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;* History:
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;*  13/01/2006 : V3.1
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;*  24/05/2005 : V3.0
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;*  30/11/2004 : V2.0
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;*  14/07/2004 : V1.3
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;*  01/01/2004 : V1.2
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;*******************************************************************************
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; THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
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; CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
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; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
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; OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
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; OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
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; CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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;*******************************************************************************/
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                MODULE  ?RESET
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                SECTION .intvec:CODE(2)
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                CODE32
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EIC_base_addr        EQU    0xFFFFF800; EIC base address.
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CICR_off_addr        EQU    0x04      ; Current Interrupt Channel Register.
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IVR_off_addr         EQU    0x18      ; Interrupt Vector Register.
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IPR_off_addr         EQU    0x40      ; Interrupt Pending Register.
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;*******************************************************************************
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;              Import  the __iar_program_start address from 71x_init.s
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;*******************************************************************************
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        IMPORT  __iar_program_start
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;*******************************************************************************
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;                      Import exception handlers
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;*******************************************************************************
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        IMPORT  Undefined_Handler
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        IMPORT  Prefetch_Handler
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        IMPORT  Abort_Handler
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        IMPORT  FIQ_Handler
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;*******************************************************************************
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;                   Import IRQ handlers from 71x_it.c
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;*******************************************************************************
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        IMPORT  Default_Handler
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                IMPORT  vPortYieldProcessor
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                IMPORT  vSerialISREntry
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                IMPORT  vPortPreemptiveTickISR
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                IMPORT  vPortNonPreemptiveTick
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;*******************************************************************************
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;            Export Peripherals IRQ handlers table address
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;*******************************************************************************
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        EXPORT  T0TIMI_Addr
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;*******************************************************************************
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;                        Exception vectors
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;*******************************************************************************
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IVR_ADDR                 DEFINE    0xFFFFF818
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                LDR     PC, Reset_Addr
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        LDR     PC, Undefined_Addr
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        LDR     PC, SWI_Addr
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        LDR     PC, Prefetch_Addr
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        LDR     PC, Abort_Addr
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        NOP                             ; Reserved vector
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        LDR     PC, =IVR_ADDR
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        LDR     PC, FIQ_Addr
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;*******************************************************************************
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;               Exception handlers address table
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;*******************************************************************************
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Reset_Addr      DCD     __iar_program_start
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Undefined_Addr  DCD     UndefinedHandler
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SWI_Addr        DCD     vPortYieldProcessor
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Prefetch_Addr   DCD     PrefetchAbortHandler
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Abort_Addr      DCD     DataAbortHandler
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                DCD     0               ; Reserved vector
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IRQ_Addr        DCD     0                            ; Direct vectors are used.  See the STR75x demo for an alternative implementation
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FIQ_Addr        DCD     FIQHandler
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;*******************************************************************************
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;              Peripherals IRQ handlers address table
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;*******************************************************************************
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T0TIMI_Addr     DCD  Default_Handler
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FLASH_Addr      DCD  Default_Handler
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RCCU_Addr       DCD  Default_Handler
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RTC_Addr        DCD  Default_Handler
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#if configUSE_PREEMPTION == 0
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WDG_Addr        DCD  vPortNonPreemptiveTick     ; Tick ISR if the cooperative scheduler is used.
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#else
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WDG_Addr                DCD  vPortPreemptiveTickISR     ; Tick ISR if the preemptive scheduler is used.
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#endif
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XTI_Addr        DCD  Default_Handler
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USBHP_Addr      DCD  Default_Handler
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I2C0ITERR_Addr  DCD  Default_Handler
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I2C1ITERR_ADDR  DCD  Default_Handler
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UART0_Addr      DCD  vSerialISREntry
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UART1_Addr      DCD  Default_Handler
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UART2_ADDR      DCD  Default_Handler
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UART3_ADDR      DCD  Default_Handler
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BSPI0_ADDR      DCD  Default_Handler
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BSPI1_Addr      DCD  Default_Handler
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I2C0_Addr       DCD  Default_Handler
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I2C1_Addr       DCD  Default_Handler
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CAN_Addr        DCD  Default_Handler
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ADC12_Addr      DCD  Default_Handler
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T1TIMI_Addr     DCD  Default_Handler
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T2TIMI_Addr     DCD  Default_Handler
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T3TIMI_Addr     DCD  Default_Handler
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                DCD  0                  ; reserved
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                DCD  0                  ; reserved
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                DCD  0                  ; reserved
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HDLC_Addr       DCD  Default_Handler
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USBLP_Addr      DCD  Default_Handler
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                DCD  0                  ; reserved
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                DCD  0                  ; reserved
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T0TOI_Addr      DCD  Default_Handler
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T0OC1_Addr      DCD  Default_Handler
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T0OC2_Addr      DCD  Default_Handler
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;*******************************************************************************
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;                         Exception Handlers
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;*******************************************************************************
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;*******************************************************************************
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;* Macro Name     : SaveContext
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;* Description    : This macro used to save the context before entering
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;                   an exception handler.
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;* Input          : The range of registers to store.
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;* Output         : none
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;*******************************************************************************
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SaveContext MACRO reg1,reg2
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        STMFD  sp!,{reg1-reg2,lr} ; Save The workspace plus the current return
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                              ; address lr_ mode into the stack.
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        MRS    r1,spsr        ; Save the spsr_mode into r1.
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        STMFD  sp!,{r1}       ; Save spsr.
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        ENDM
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;*******************************************************************************
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;* Macro Name     : RestoreContext
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;* Description    : This macro used to restore the context to return from
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;                   an exception handler and continue the program execution.
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;* Input          : The range of registers to restore.
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;* Output         : none
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;*******************************************************************************
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RestoreContext MACRO reg1,reg2
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        LDMFD   sp!,{r1}        ; Restore the saved spsr_mode into r1.
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        MSR     spsr_cxsf,r1    ; Restore spsr_mode.
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        LDMFD   sp!,{reg1-reg2,pc}^; Return to the instruction following...
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                                ; ...the exception interrupt.
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        ENDM
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;*******************************************************************************
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;* Function Name  : UndefinedHandler
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;* Description    : This function called when undefined instruction
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;                   exception is entered.
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;* Input          : none
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;* Output         : none
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;*******************************************************************************
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UndefinedHandler
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        SaveContext r0,r12           ; Save the workspace plus the current
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                                     ; return address lr_ und and spsr_und.
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        ldr r0,=Undefined_Handler
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        ldr lr,=Undefined_Handler_end
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        bx r0                        ; Branch to Undefined_Handler
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Undefined_Handler_end:
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        RestoreContext r0,r12        ; Return to the instruction following...
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                                     ; ...the undefined instruction.
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;*******************************************************************************
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;* Function Name  : PrefetchAbortHandler
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;* Description    : This function called when Prefetch Abort
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;                   exception is entered.
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;* Input          : none
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;* Output         : none
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;*******************************************************************************
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PrefetchAbortHandler
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        SUB    lr,lr,#4       ; Update the link register.
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        SaveContext r0,r12    ; Save the workspace plus the current
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                              ; return address lr_abt and spsr_abt.
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        ldr r0,=Prefetch_Handler
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        ldr lr,=Prefetch_Handler_end
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        bx r0                 ; Branch to Prefetch_Handler.
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Prefetch_Handler_end:
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        RestoreContext r0,r12 ; Return to the instruction following that...
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                              ; ...has generated the prefetch abort exception.
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;*******************************************************************************
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;* Function Name  : DataAbortHandler
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;* Description    : This function is called when Data Abort
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;                   exception is entered.
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;* Input          : none
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;* Output         : none
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;*******************************************************************************
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DataAbortHandler
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        SUB    lr,lr,#8       ; Update the link register.
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        SaveContext r0,r12    ; Save the workspace plus the current
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                              ; return address lr_ abt and spsr_abt.
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        ldr r0,=Abort_Handler
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        ldr lr,=Abort_Handler_end
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        bx r0                 ; Branch to Abort_Handler.
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Abort_Handler_end:
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        RestoreContext r0,r12 ; Return to the instruction following that...
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                              ; ...has generated the data abort exception.
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;*******************************************************************************
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;* Function Name  : FIQHandler
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;* Description    : This function is called when FIQ
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;                   exception is entered.
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;* Input          : none
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;* Output         : none
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;*******************************************************************************
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FIQHandler
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        SUB    lr,lr,#4       ; Update the link register.
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        SaveContext r0,r7     ; Save the workspace plus the current
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                              ; return address lr_ fiq and spsr_fiq.
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        ldr r0,=FIQ_Handler
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        ldr lr,=FIQ_Handler_end
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        bx r0                 ; Branch to FIQ_Handler.
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FIQ_Handler_end:
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        RestoreContext r0,r7  ; Restore the context and return to the...
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                              ; ...program execution.
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                LTORG
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  END
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;******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****

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