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/******************** (C) COPYRIGHT 2003 STMicroelectronics ********************
* File Name          : 71x_map.h
* Author             : MCD Application Team
* Date First Issued  : 05/16/2003
* Description        : Peripherals memory mapping and registers structures
********************************************************************************
* History:
*  30/11/2004 : V2.0
*  14/07/2004 : V1.3
*  01/01/2004 : V1.2
*******************************************************************************
 THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
 CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
 AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
 OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
 OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
 CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
 
#ifndef __71x_map_H
#define __71x_map_H
 
#ifndef EXT
  #define EXT extern
#endif
 
#include "71x_conf.h"
#include "71x_type.h"
 
 
/* IP registers structures */
 
typedef volatile struct
{
  vu16 DATA0;
  vu16 EMPTY1[3];
  vu16 DATA1;
  vu16 EMPTY2[3];
  vu16 DATA2;
  vu16 EMPTY3[3];
  vu16 DATA3;
  vu16 EMPTY4[3];
  vu16 CSR;
  vu16 EMPTY5[7];
  vu16 CPR;
} ADC12_TypeDef;
 
typedef volatile struct
{
  vu32 CKDIS;
  vu32 SWRES;
} APB_TypeDef;
 
typedef volatile struct
{
  vu16 RXR;
  vu16 EMPTY1;
  vu16 TXR;
  vu16 EMPTY2;
  vu16 CSR1;
  vu16 EMPTY3;
  vu16 CSR2;
  vu16 EMPTY4;
  vu16 CLK;
} BSPI_TypeDef;
 
typedef volatile struct
{
  vu16 CRR;
  vu16 EMPTY1;
  vu16 CMR;
  vu16 EMPTY2;
  vu16 M1R;
  vu16 EMPTY3;
  vu16 M2R;
  vu16 EMPTY4;
  vu16 A1R;
  vu16 EMPTY5;
  vu16 A2R;
  vu16 EMPTY6;
  vu16 MCR;
  vu16 EMPTY7;
  vu16 DA1R;
  vu16 EMPTY8;
  vu16 DA2R;
  vu16 EMPTY9;
  vu16 DB1R;
  vu16 EMPTY10;
  vu16 DB2R;
  vu16 EMPTY11[27];
} CAN_MsgObj_TypeDef;
 
typedef volatile struct
{
  vu16 CR;
  vu16 EMPTY1;
  vu16 SR;
  vu16 EMPTY2;
  vu16 ERR;
  vu16 EMPTY3;
  vu16 BTR;
  vu16 EMPTY4;
  vu16 IDR;
  vu16 EMPTY5;
  vu16 TESTR;
  vu16 EMPTY6;
  vu16 BRPR;
  vu16 EMPTY7[3];
  CAN_MsgObj_TypeDef sMsgObj[2];
  vu16 EMPTY8[16];
  vu16 TR1R;
  vu16 EMPTY9;
  vu16 TR2R;
  vu16 EMPTY10[13];
  vu16 ND1R;
  vu16 EMPTY11;
  vu16 ND2R;
  vu16 EMPTY12[13];
  vu16 IP1R;
  vu16 EMPTY13;
  vu16 IP2R;
  vu16 EMPTY14[13];
  vu16 MV1R;
  vu16 EMPTY15;
  vu16 MV2R;
  vu16 EMPTY16;
} CAN_TypeDef;
 
typedef volatile struct
{
  vu32 ICR;
  vu32 CICR;
  vu32 CIPR;
  vu32 EMPTY1[3];
  vu32 IVR;
  vu32 FIR;
  vu32 IER;
  vu32 EMPTY2[7];
  vu32 IPR;
  vu32 EMPTY3[7];
  vu32 SIR[32];
} EIC_TypeDef;
 
typedef volatile struct
{
  vu16 BCON0;
  vu16 EMPTY1;
  vu16 BCON1;
  vu16 EMPTY2;
  vu16 BCON2;
  vu16 EMPTY3;
  vu16 BCON3;
  vu16 EMPTY4;
} EMI_TypeDef;
 
typedef volatile struct
{
  vu32 CR0;
  vu32 CR1;
  vu32 DR0;
  vu32 DR1;
  vu32 AR;
  vu32 ER;
} FLASHR_TypeDef;
 
typedef volatile struct
{
  vu32 NVWPAR;
  vu32 EMPTY;
  vu32 NVAPR0;
  vu32 NVAPR1;
} FLASHPR_TypeDef;
 
typedef volatile struct
{
  vu16 PC0;
  vu16 EMPTY1;
  vu16 PC1;
  vu16 EMPTY2;
  vu16 PC2;
  vu16 EMPTY3;
  vu16 PD;
  vu16 EMPTY4;
} GPIO_TypeDef;
 
typedef volatile struct
{
  vu8  CR;
  vu8  EMPTY1[3];
  vu8  SR1;
  vu8  EMPTY2[3];
  vu8  SR2;
  vu8  EMPTY3[3];
  vu8  CCR;
  vu8  EMPTY4[3];
  vu8  OAR1;
  vu8  EMPTY5[3];
  vu8  OAR2;
  vu8  EMPTY6[3];
  vu8  DR;
  vu8  EMPTY7[3];
  vu8  ECCR;
} I2C_TypeDef;
 
typedef volatile struct
{
  vu32 CCR;
  vu32 EMPTY1;
  vu32 CFR;
  vu32 EMPTY2[3];
  vu32 PLL1CR;
  vu32 PER;
  vu32 SMR;
} RCCU_TypeDef;
 
typedef volatile struct
{
  vu16 MDIVR;
  vu16 EMPTY1;
  vu16 PDIVR;
  vu16 EMPTY2;
  vu16 RSTR;
  vu16 EMPTY3;
  vu16 PLL2CR;
  vu16 EMPTY4;
  vu16 BOOTCR;
  vu16 EMPTY5;
  vu16 PWRCR;
} PCU_TypeDef;
 
typedef volatile struct
{
  vu16 CRH;
  vu16 EMPTY1;
  vu16 CRL;
  vu16 EMPTY2;
  vu16 PRLH;
  vu16 EMPTY3;
  vu16 PRLL;
  vu16 EMPTY4;
  vu16 DIVH;
  vu16 EMPTY5;
  vu16 DIVL;
  vu16 EMPTY6;
  vu16 CNTH;
  vu16 EMPTY7;
  vu16 CNTL;
  vu16 EMPTY8;
  vu16 ALRH;
  vu16 EMPTY9;
  vu16 ALRL;
} RTC_TypeDef;
 
typedef volatile struct
{
  vu16 ICAR;
  vu16 EMPTY1;
  vu16 ICBR;
  vu16 EMPTY2;
  vu16 OCAR;
  vu16 EMPTY3;
  vu16 OCBR;
  vu16 EMPTY4;
  vu16 CNTR;
  vu16 EMPTY5;
  vu16 CR1;
  vu16 EMPTY6;
  vu16 CR2;
  vu16 EMPTY7;
  vu16 SR;
} TIM_TypeDef;
 
typedef volatile struct
{
  vu16 BR;
  vu16 EMPTY1;
  vu16 TxBUFR;
  vu16 EMPTY2;
  vu16 RxBUFR;
  vu16 EMPTY3;
  vu16 CR;
  vu16 EMPTY4;
  vu16 IER;
  vu16 EMPTY5;
  vu16 SR;
  vu16 EMPTY6;
  vu16 GTR;
  vu16 EMPTY7;
  vu16 TOR;
  vu16 EMPTY8;
  vu16 TxRSTR;
  vu16 EMPTY9;
  vu16 RxRSTR;
} UART_TypeDef;
 
typedef volatile struct
{
  vu32 EP0R;
  vu32 EP1R;
  vu32 EP2R;
  vu32 EP3R;
  vu32 EP4R;
  vu32 EP5R;
  vu32 EP6R;
  vu32 EP7R;
  vu32 EP8R;
  vu32 EP9R;
  vu32 EP10R;
  vu32 EP11R;
  vu32 EP12R;
  vu32 EP13R;
  vu32 EP14R;
  vu32 EP15R;
  vu32 CNTR;
  vu32 ISTR;
  vu32 FNR;
  vu32 DADDR;
  vu32 BTABLE;
} USB_TypeDef;
 
typedef volatile struct
{
  vu16 CR;
  vu16 EMPTY1;
  vu16 PR;
  vu16 EMPTY2;
  vu16 VR;
  vu16 EMPTY3;
  vu16 CNT;
  vu16 EMPTY4;
  vu16 SR;
  vu16 EMPTY5;
  vu16 MR;
  vu16 EMPTY6;
  vu16 KR;
} WDG_TypeDef;
 
typedef volatile struct
{
  vu8  SR;
  vu8  EMPTY1[7];
  vu8  CTRL;
  vu8  EMPTY2[3];
  vu8  MRH;
  vu8  EMPTY3[3];
  vu8  MRL;
  vu8  EMPTY4[3];
  vu8  TRH;
  vu8  EMPTY5[3];
  vu8  TRL;
  vu8  EMPTY6[3];
  vu8  PRH;
  vu8  EMPTY7[3];
  vu8  PRL;
} XTI_TypeDef;
 
 
/* IRQ vectors */
typedef volatile struct
{
  vu32 T0TIMI_IRQHandler;
  vu32 FLASH_IRQHandler;
  vu32 RCCU_IRQHandler;
  vu32 RTC_IRQHandler;
  vu32 WDG_IRQHandler;
  vu32 XTI_IRQHandler;
  vu32 USBHP_IRQHandler;
  vu32 I2C0ITERR_IRQHandler;
  vu32 I2C1ITERR_IRQHandler;
  vu32 UART0_IRQHandler;
  vu32 UART1_IRQHandler;
  vu32 UART2_IRQHandler;
  vu32 UART3_IRQHandler;
  vu32 BSPI0_IRQHandler;
  vu32 BSPI1_IRQHandler;
  vu32 I2C0_IRQHandler;
  vu32 I2C1_IRQHandler;
  vu32 CAN_IRQHandler;
  vu32 ADC12_IRQHandler;
  vu32 T1TIMI_IRQHandler;
  vu32 T2TIMI_IRQHandler;
  vu32 T3TIMI_IRQHandler;
  vu32 EMPTY1[3];
  vu32 HDLC_IRQHandler;
  vu32 USBLP_IRQHandler;
  vu32 EMPTY2[2];
  vu32 T0TOI_IRQHandler;
  vu32 T0OC1_IRQHandler;
  vu32 T0OC2_IRQHandler;
} IRQVectors_TypeDef;
 
/*===================================================================*/
 
/* Memory mapping */
 
#define RAM_BASE        0x20000000
 
#define FLASHR_BASE     0x40100000
#define FLASHPR_BASE    0x4010DFB0
 
#define EXTMEM_BASE     0x60000000
#define RCCU_BASE       0xA0000000
#define PCU_BASE        0xA0000040
#define APB1_BASE       0xC0000000
#define APB2_BASE       0xE0000000
#define EIC_BASE        0xFFFFF800
 
#define I2C0_BASE       (APB1_BASE + 0x1000)
#define I2C1_BASE       (APB1_BASE + 0x2000)
#define UART0_BASE      (APB1_BASE + 0x4000)
#define UART1_BASE      (APB1_BASE + 0x5000)
#define UART2_BASE      (APB1_BASE + 0x6000)
#define UART3_BASE      (APB1_BASE + 0x7000)
#define CAN_BASE        (APB1_BASE + 0x9000)
#define BSPI0_BASE      (APB1_BASE + 0xA000)
#define BSPI1_BASE      (APB1_BASE + 0xB000)
#define USB_BASE        (APB1_BASE + 0x8800)
 
#define XTI_BASE        (APB2_BASE + 0x101C)
#define GPIO0_BASE      (APB2_BASE + 0x3000)
#define GPIO1_BASE      (APB2_BASE + 0x4000)
#define GPIO2_BASE      (APB2_BASE + 0x5000)
#define ADC12_BASE      (APB2_BASE + 0x7000)
#define TIM0_BASE       (APB2_BASE + 0x9000)
#define TIM1_BASE       (APB2_BASE + 0xA000)
#define TIM2_BASE       (APB2_BASE + 0xB000)
#define TIM3_BASE       (APB2_BASE + 0xC000)
#define RTC_BASE        (APB2_BASE + 0xD000)
#define WDG_BASE        (APB2_BASE + 0xE000)
 
#define EMI_BASE        (EXTMEM_BASE + 0x0C000000)
 
/*===================================================================*/
 
/* IP data access */
 
#ifndef DEBUG
  #define ADC12 ((ADC12_TypeDef *)ADC12_BASE)
 
  #define APB1  ((APB_TypeDef *)APB1_BASE)
  #define APB2  ((APB_TypeDef *)APB2_BASE+0x10)
 
  #define BSPI0 ((BSPI_TypeDef *)BSPI0_BASE)
  #define BSPI1 ((BSPI_TypeDef *)BSPI1_BASE)
 
  #define CAN   ((CAN_TypeDef *)CAN_BASE)
 
  #define EIC   ((EIC_TypeDef *)EIC_BASE)
 
  #define EMI   ((EMI_TypeDef *)EMI_BASE)
 
  #define FLASHR  ((FLASHR_TypeDef *)FLASHR_BASE)
  #define FLASHPR ((FLASHPR_TypeDef *)FLASHPR_BASE)
 
  #define GPIO0 ((GPIO_TypeDef *)GPIO0_BASE)
  #define GPIO1 ((GPIO_TypeDef *)GPIO1_BASE)
  #define GPIO2 ((GPIO_TypeDef *)GPIO2_BASE)
 
  #define I2C0  ((I2C_TypeDef *)I2C0_BASE)
  #define I2C1  ((I2C_TypeDef *)I2C1_BASE)
 
  #define PCU   ((PCU_TypeDef *)PCU_BASE)
 
  #define RCCU  ((RCCU_TypeDef *)RCCU_BASE)
 
  #define RTC   ((RTC_TypeDef *)RTC_BASE)
 
  #define TIM0  ((TIM_TypeDef *)TIM0_BASE)
  #define TIM1  ((TIM_TypeDef *)TIM1_BASE)
  #define TIM2  ((TIM_TypeDef *)TIM2_BASE)
  #define TIM3  ((TIM_TypeDef *)TIM3_BASE)
 
  #define UART0 ((UART_TypeDef *)UART0_BASE)
  #define UART1 ((UART_TypeDef *)UART1_BASE)
  #define UART2 ((UART_TypeDef *)UART2_BASE)
  #define UART3 ((UART_TypeDef *)UART3_BASE)
 
  #define USB   ((USB_TypeDef *)USB_BASE)
 
  #define WDG   ((WDG_TypeDef *)WDG_BASE)
 
  #define XTI   ((XTI_TypeDef *)XTI_BASE)
 
  #define IRQVectors ((IRQVectors_TypeDef *)&T0TIMI_Addr)
 
#else   /* DEBUG */
 
  #ifdef _ADC12
  EXT ADC12_TypeDef *ADC12;
  #endif
 
  #ifdef _APB
  #ifdef _APB1
  EXT APB_TypeDef *APB1;
  #endif
  #ifdef _APB2
  EXT APB_TypeDef *APB2;
  #endif
  #endif
 
  #ifdef _BSPI
  #ifdef _BSPI0
  EXT BSPI_TypeDef *BSPI0;
  #endif
  #ifdef _BSPI1
  EXT BSPI_TypeDef *BSPI1;
  #endif
  #endif
 
  #ifdef _CAN
  EXT CAN_TypeDef *CAN;
  #endif
 
  #ifdef _EIC
  EXT EIC_TypeDef *EIC;
  #endif
 
  #ifdef _EMI
  EXT EMI_TypeDef *EMI;
  #endif
 
  #ifdef _FLASH
  EXT FLASHR_TypeDef *FLASHR;
  EXT FLASHPR_TypeDef *FLASHPR;
  #endif
 
  #ifdef _GPIO
  #ifdef _GPIO0
  EXT GPIO_TypeDef *GPIO0;
  #endif
  #ifdef _GPIO1
  EXT GPIO_TypeDef *GPIO1;
  #endif
  #ifdef _GPIO2
  EXT GPIO_TypeDef *GPIO2;
  #endif
  #endif
 
  #ifdef _I2C
  #ifdef _I2C0
  EXT I2C_TypeDef *I2C0;
  #endif
  #ifdef _I2C1
  EXT I2C_TypeDef *I2C1;
  #endif
  #endif
 
  #ifdef _PCU
  EXT PCU_TypeDef *PCU;
  #endif
 
  #ifdef _RCCU
  EXT RCCU_TypeDef *RCCU;
  #endif
 
  #ifdef _RTC
  EXT RTC_TypeDef *RTC;
  #endif
 
  #ifdef _TIM
  #ifdef _TIM0
  EXT TIM_TypeDef *TIM0;
  #endif
  #ifdef _TIM1
  EXT TIM_TypeDef *TIM1;
  #endif
  #ifdef _TIM2
  EXT TIM_TypeDef *TIM2;
  #endif
  #ifdef _TIM3
  EXT TIM_TypeDef *TIM3;
  #endif
  #endif
 
  #ifdef _UART
  #ifdef _UART0
  EXT UART_TypeDef *UART0;
  #endif
  #ifdef _UART1
  EXT UART_TypeDef *UART1;
  #endif
  #ifdef _UART2
  EXT UART_TypeDef *UART2;
  #endif
  #ifdef _UART3
  EXT UART_TypeDef *UART3;
  #endif
  #endif
 
  #ifdef _USB
  EXT USB_TypeDef *USB;
  #endif
 
  #ifdef _WDG
  EXT WDG_TypeDef *WDG;
  #endif
 
  #ifdef _XTI
  EXT XTI_TypeDef *XTI;
  #endif
 
  #ifdef _IRQVectors
  EXT IRQVectors_TypeDef *IRQVectors;
  #endif
 
#endif  /* DEBUG */
 
#endif  /* __71x_map_H */
 
/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/

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Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [ARM7_STR71x_IAR/] [Library/] [include/] [71x_map.h] - Blame information for rev 597

Line No.	Rev	Author	Line
1	577	jeremybenn	`/****************** (C) COPYRIGHT 2003 STMicroelectronics ******************`
2			`* File Name : 71x_map.h`
3			`* Author : MCD Application Team`
4			`* Date First Issued : 05/16/2003`
5			`* Description : Peripherals memory mapping and registers structures`
6			`********************************************************************************`
7			`* History:`
8			`* 30/11/2004 : V2.0`
9			`* 14/07/2004 : V1.3`
10			`* 01/01/2004 : V1.2`
11			`*******************************************************************************`
12			`THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH`
13			`CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.`
14			`AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT`
15			`OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT`
16			`OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION`
17			`CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.`
18			`*******************************************************************************/`
19
20			`#ifndef __71x_map_H`
21			`#define __71x_map_H`
22
23			`#ifndef EXT`
24			`#define EXT extern`
25			`#endif`
26
27			`#include "71x_conf.h"`
28			`#include "71x_type.h"`
29
30
31			`/* IP registers structures */`
32
33			`typedef volatile struct`
34			`{`
35			`vu16 DATA0;`
36			`vu16 EMPTY1[3];`
37			`vu16 DATA1;`
38			`vu16 EMPTY2[3];`
39			`vu16 DATA2;`
40			`vu16 EMPTY3[3];`
41			`vu16 DATA3;`
42			`vu16 EMPTY4[3];`
43			`vu16 CSR;`
44			`vu16 EMPTY5[7];`
45			`vu16 CPR;`
46			`} ADC12_TypeDef;`
47
48			`typedef volatile struct`
49			`{`
50			`vu32 CKDIS;`
51			`vu32 SWRES;`
52			`} APB_TypeDef;`
53
54			`typedef volatile struct`
55			`{`
56			`vu16 RXR;`
57			`vu16 EMPTY1;`
58			`vu16 TXR;`
59			`vu16 EMPTY2;`
60			`vu16 CSR1;`
61			`vu16 EMPTY3;`
62			`vu16 CSR2;`
63			`vu16 EMPTY4;`
64			`vu16 CLK;`
65			`} BSPI_TypeDef;`
66
67			`typedef volatile struct`
68			`{`
69			`vu16 CRR;`
70			`vu16 EMPTY1;`
71			`vu16 CMR;`
72			`vu16 EMPTY2;`
73			`vu16 M1R;`
74			`vu16 EMPTY3;`
75			`vu16 M2R;`
76			`vu16 EMPTY4;`
77			`vu16 A1R;`
78			`vu16 EMPTY5;`
79			`vu16 A2R;`
80			`vu16 EMPTY6;`
81			`vu16 MCR;`
82			`vu16 EMPTY7;`
83			`vu16 DA1R;`
84			`vu16 EMPTY8;`
85			`vu16 DA2R;`
86			`vu16 EMPTY9;`
87			`vu16 DB1R;`
88			`vu16 EMPTY10;`
89			`vu16 DB2R;`
90			`vu16 EMPTY11[27];`
91			`} CAN_MsgObj_TypeDef;`
92
93			`typedef volatile struct`
94			`{`
95			`vu16 CR;`
96			`vu16 EMPTY1;`
97			`vu16 SR;`
98			`vu16 EMPTY2;`
99			`vu16 ERR;`
100			`vu16 EMPTY3;`
101			`vu16 BTR;`
102			`vu16 EMPTY4;`
103			`vu16 IDR;`
104			`vu16 EMPTY5;`
105			`vu16 TESTR;`
106			`vu16 EMPTY6;`
107			`vu16 BRPR;`
108			`vu16 EMPTY7[3];`
109			`CAN_MsgObj_TypeDef sMsgObj[2];`
110			`vu16 EMPTY8[16];`
111			`vu16 TR1R;`
112			`vu16 EMPTY9;`
113			`vu16 TR2R;`
114			`vu16 EMPTY10[13];`
115			`vu16 ND1R;`
116			`vu16 EMPTY11;`
117			`vu16 ND2R;`
118			`vu16 EMPTY12[13];`
119			`vu16 IP1R;`
120			`vu16 EMPTY13;`
121			`vu16 IP2R;`
122			`vu16 EMPTY14[13];`
123			`vu16 MV1R;`
124			`vu16 EMPTY15;`
125			`vu16 MV2R;`
126			`vu16 EMPTY16;`
127			`} CAN_TypeDef;`
128
129			`typedef volatile struct`
130			`{`
131			`vu32 ICR;`
132			`vu32 CICR;`
133			`vu32 CIPR;`
134			`vu32 EMPTY1[3];`
135			`vu32 IVR;`
136			`vu32 FIR;`
137			`vu32 IER;`
138			`vu32 EMPTY2[7];`
139			`vu32 IPR;`
140			`vu32 EMPTY3[7];`
141			`vu32 SIR[32];`
142			`} EIC_TypeDef;`
143
144			`typedef volatile struct`
145			`{`
146			`vu16 BCON0;`
147			`vu16 EMPTY1;`
148			`vu16 BCON1;`
149			`vu16 EMPTY2;`
150			`vu16 BCON2;`
151			`vu16 EMPTY3;`
152			`vu16 BCON3;`
153			`vu16 EMPTY4;`
154			`} EMI_TypeDef;`
155
156			`typedef volatile struct`
157			`{`
158			`vu32 CR0;`
159			`vu32 CR1;`
160			`vu32 DR0;`
161			`vu32 DR1;`
162			`vu32 AR;`
163			`vu32 ER;`
164			`} FLASHR_TypeDef;`
165
166			`typedef volatile struct`
167			`{`
168			`vu32 NVWPAR;`
169			`vu32 EMPTY;`
170			`vu32 NVAPR0;`
171			`vu32 NVAPR1;`
172			`} FLASHPR_TypeDef;`
173
174			`typedef volatile struct`
175			`{`
176			`vu16 PC0;`
177			`vu16 EMPTY1;`
178			`vu16 PC1;`
179			`vu16 EMPTY2;`
180			`vu16 PC2;`
181			`vu16 EMPTY3;`
182			`vu16 PD;`
183			`vu16 EMPTY4;`
184			`} GPIO_TypeDef;`
185
186			`typedef volatile struct`
187			`{`
188			`vu8 CR;`
189			`vu8 EMPTY1[3];`
190			`vu8 SR1;`
191			`vu8 EMPTY2[3];`
192			`vu8 SR2;`
193			`vu8 EMPTY3[3];`
194			`vu8 CCR;`
195			`vu8 EMPTY4[3];`
196			`vu8 OAR1;`
197			`vu8 EMPTY5[3];`
198			`vu8 OAR2;`
199			`vu8 EMPTY6[3];`
200			`vu8 DR;`
201			`vu8 EMPTY7[3];`
202			`vu8 ECCR;`
203			`} I2C_TypeDef;`
204
205			`typedef volatile struct`
206			`{`
207			`vu32 CCR;`
208			`vu32 EMPTY1;`
209			`vu32 CFR;`
210			`vu32 EMPTY2[3];`
211			`vu32 PLL1CR;`
212			`vu32 PER;`
213			`vu32 SMR;`
214			`} RCCU_TypeDef;`
215
216			`typedef volatile struct`
217			`{`
218			`vu16 MDIVR;`
219			`vu16 EMPTY1;`
220			`vu16 PDIVR;`
221			`vu16 EMPTY2;`
222			`vu16 RSTR;`
223			`vu16 EMPTY3;`
224			`vu16 PLL2CR;`
225			`vu16 EMPTY4;`
226			`vu16 BOOTCR;`
227			`vu16 EMPTY5;`
228			`vu16 PWRCR;`
229			`} PCU_TypeDef;`
230
231			`typedef volatile struct`
232			`{`
233			`vu16 CRH;`
234			`vu16 EMPTY1;`
235			`vu16 CRL;`
236			`vu16 EMPTY2;`
237			`vu16 PRLH;`
238			`vu16 EMPTY3;`
239			`vu16 PRLL;`
240			`vu16 EMPTY4;`
241			`vu16 DIVH;`
242			`vu16 EMPTY5;`
243			`vu16 DIVL;`
244			`vu16 EMPTY6;`
245			`vu16 CNTH;`
246			`vu16 EMPTY7;`
247			`vu16 CNTL;`
248			`vu16 EMPTY8;`
249			`vu16 ALRH;`
250			`vu16 EMPTY9;`
251			`vu16 ALRL;`
252			`} RTC_TypeDef;`
253
254			`typedef volatile struct`
255			`{`
256			`vu16 ICAR;`
257			`vu16 EMPTY1;`
258			`vu16 ICBR;`
259			`vu16 EMPTY2;`
260			`vu16 OCAR;`
261			`vu16 EMPTY3;`
262			`vu16 OCBR;`
263			`vu16 EMPTY4;`
264			`vu16 CNTR;`
265			`vu16 EMPTY5;`
266			`vu16 CR1;`
267			`vu16 EMPTY6;`
268			`vu16 CR2;`
269			`vu16 EMPTY7;`
270			`vu16 SR;`
271			`} TIM_TypeDef;`
272
273			`typedef volatile struct`
274			`{`
275			`vu16 BR;`
276			`vu16 EMPTY1;`
277			`vu16 TxBUFR;`
278			`vu16 EMPTY2;`
279			`vu16 RxBUFR;`
280			`vu16 EMPTY3;`
281			`vu16 CR;`
282			`vu16 EMPTY4;`
283			`vu16 IER;`
284			`vu16 EMPTY5;`
285			`vu16 SR;`
286			`vu16 EMPTY6;`
287			`vu16 GTR;`
288			`vu16 EMPTY7;`
289			`vu16 TOR;`
290			`vu16 EMPTY8;`
291			`vu16 TxRSTR;`
292			`vu16 EMPTY9;`
293			`vu16 RxRSTR;`
294			`} UART_TypeDef;`
295
296			`typedef volatile struct`
297			`{`
298			`vu32 EP0R;`
299			`vu32 EP1R;`
300			`vu32 EP2R;`
301			`vu32 EP3R;`
302			`vu32 EP4R;`
303			`vu32 EP5R;`
304			`vu32 EP6R;`
305			`vu32 EP7R;`
306			`vu32 EP8R;`
307			`vu32 EP9R;`
308			`vu32 EP10R;`
309			`vu32 EP11R;`
310			`vu32 EP12R;`
311			`vu32 EP13R;`
312			`vu32 EP14R;`
313			`vu32 EP15R;`
314			`vu32 CNTR;`
315			`vu32 ISTR;`
316			`vu32 FNR;`
317			`vu32 DADDR;`
318			`vu32 BTABLE;`
319			`} USB_TypeDef;`
320
321			`typedef volatile struct`
322			`{`
323			`vu16 CR;`
324			`vu16 EMPTY1;`
325			`vu16 PR;`
326			`vu16 EMPTY2;`
327			`vu16 VR;`
328			`vu16 EMPTY3;`
329			`vu16 CNT;`
330			`vu16 EMPTY4;`
331			`vu16 SR;`
332			`vu16 EMPTY5;`
333			`vu16 MR;`
334			`vu16 EMPTY6;`
335			`vu16 KR;`
336			`} WDG_TypeDef;`
337
338			`typedef volatile struct`
339			`{`
340			`vu8 SR;`
341			`vu8 EMPTY1[7];`
342			`vu8 CTRL;`
343			`vu8 EMPTY2[3];`
344			`vu8 MRH;`
345			`vu8 EMPTY3[3];`
346			`vu8 MRL;`
347			`vu8 EMPTY4[3];`
348			`vu8 TRH;`
349			`vu8 EMPTY5[3];`
350			`vu8 TRL;`
351			`vu8 EMPTY6[3];`
352			`vu8 PRH;`
353			`vu8 EMPTY7[3];`
354			`vu8 PRL;`
355			`} XTI_TypeDef;`
356
357
358			`/* IRQ vectors */`
359			`typedef volatile struct`
360			`{`
361			`vu32 T0TIMI_IRQHandler;`
362			`vu32 FLASH_IRQHandler;`
363			`vu32 RCCU_IRQHandler;`
364			`vu32 RTC_IRQHandler;`
365			`vu32 WDG_IRQHandler;`
366			`vu32 XTI_IRQHandler;`
367			`vu32 USBHP_IRQHandler;`
368			`vu32 I2C0ITERR_IRQHandler;`
369			`vu32 I2C1ITERR_IRQHandler;`
370			`vu32 UART0_IRQHandler;`
371			`vu32 UART1_IRQHandler;`
372			`vu32 UART2_IRQHandler;`
373			`vu32 UART3_IRQHandler;`
374			`vu32 BSPI0_IRQHandler;`
375			`vu32 BSPI1_IRQHandler;`
376			`vu32 I2C0_IRQHandler;`
377			`vu32 I2C1_IRQHandler;`
378			`vu32 CAN_IRQHandler;`
379			`vu32 ADC12_IRQHandler;`
380			`vu32 T1TIMI_IRQHandler;`
381			`vu32 T2TIMI_IRQHandler;`
382			`vu32 T3TIMI_IRQHandler;`
383			`vu32 EMPTY1[3];`
384			`vu32 HDLC_IRQHandler;`
385			`vu32 USBLP_IRQHandler;`
386			`vu32 EMPTY2[2];`
387			`vu32 T0TOI_IRQHandler;`
388			`vu32 T0OC1_IRQHandler;`
389			`vu32 T0OC2_IRQHandler;`
390			`} IRQVectors_TypeDef;`
391
392			`/===================================================================/`
393
394			`/* Memory mapping */`
395
396			`#define RAM_BASE 0x20000000`
397
398			`#define FLASHR_BASE 0x40100000`
399			`#define FLASHPR_BASE 0x4010DFB0`
400
401			`#define EXTMEM_BASE 0x60000000`
402			`#define RCCU_BASE 0xA0000000`
403			`#define PCU_BASE 0xA0000040`
404			`#define APB1_BASE 0xC0000000`
405			`#define APB2_BASE 0xE0000000`
406			`#define EIC_BASE 0xFFFFF800`
407
408			`#define I2C0_BASE (APB1_BASE + 0x1000)`
409			`#define I2C1_BASE (APB1_BASE + 0x2000)`
410			`#define UART0_BASE (APB1_BASE + 0x4000)`
411			`#define UART1_BASE (APB1_BASE + 0x5000)`
412			`#define UART2_BASE (APB1_BASE + 0x6000)`
413			`#define UART3_BASE (APB1_BASE + 0x7000)`
414			`#define CAN_BASE (APB1_BASE + 0x9000)`
415			`#define BSPI0_BASE (APB1_BASE + 0xA000)`
416			`#define BSPI1_BASE (APB1_BASE + 0xB000)`
417			`#define USB_BASE (APB1_BASE + 0x8800)`
418
419			`#define XTI_BASE (APB2_BASE + 0x101C)`
420			`#define GPIO0_BASE (APB2_BASE + 0x3000)`
421			`#define GPIO1_BASE (APB2_BASE + 0x4000)`
422			`#define GPIO2_BASE (APB2_BASE + 0x5000)`
423			`#define ADC12_BASE (APB2_BASE + 0x7000)`
424			`#define TIM0_BASE (APB2_BASE + 0x9000)`
425			`#define TIM1_BASE (APB2_BASE + 0xA000)`
426			`#define TIM2_BASE (APB2_BASE + 0xB000)`
427			`#define TIM3_BASE (APB2_BASE + 0xC000)`
428			`#define RTC_BASE (APB2_BASE + 0xD000)`
429			`#define WDG_BASE (APB2_BASE + 0xE000)`
430
431			`#define EMI_BASE (EXTMEM_BASE + 0x0C000000)`
432
433			`/===================================================================/`
434
435			`/* IP data access */`
436
437			`#ifndef DEBUG`
438			`#define ADC12 ((ADC12_TypeDef *)ADC12_BASE)`
439
440			`#define APB1 ((APB_TypeDef *)APB1_BASE)`
441			`#define APB2 ((APB_TypeDef *)APB2_BASE+0x10)`
442
443			`#define BSPI0 ((BSPI_TypeDef *)BSPI0_BASE)`
444			`#define BSPI1 ((BSPI_TypeDef *)BSPI1_BASE)`
445
446			`#define CAN ((CAN_TypeDef *)CAN_BASE)`
447
448			`#define EIC ((EIC_TypeDef *)EIC_BASE)`
449
450			`#define EMI ((EMI_TypeDef *)EMI_BASE)`
451
452			`#define FLASHR ((FLASHR_TypeDef *)FLASHR_BASE)`
453			`#define FLASHPR ((FLASHPR_TypeDef *)FLASHPR_BASE)`
454
455			`#define GPIO0 ((GPIO_TypeDef *)GPIO0_BASE)`
456			`#define GPIO1 ((GPIO_TypeDef *)GPIO1_BASE)`
457			`#define GPIO2 ((GPIO_TypeDef *)GPIO2_BASE)`
458
459			`#define I2C0 ((I2C_TypeDef *)I2C0_BASE)`
460			`#define I2C1 ((I2C_TypeDef *)I2C1_BASE)`
461
462			`#define PCU ((PCU_TypeDef *)PCU_BASE)`
463
464			`#define RCCU ((RCCU_TypeDef *)RCCU_BASE)`
465
466			`#define RTC ((RTC_TypeDef *)RTC_BASE)`
467
468			`#define TIM0 ((TIM_TypeDef *)TIM0_BASE)`
469			`#define TIM1 ((TIM_TypeDef *)TIM1_BASE)`
470			`#define TIM2 ((TIM_TypeDef *)TIM2_BASE)`
471			`#define TIM3 ((TIM_TypeDef *)TIM3_BASE)`
472
473			`#define UART0 ((UART_TypeDef *)UART0_BASE)`
474			`#define UART1 ((UART_TypeDef *)UART1_BASE)`
475			`#define UART2 ((UART_TypeDef *)UART2_BASE)`
476			`#define UART3 ((UART_TypeDef *)UART3_BASE)`
477
478			`#define USB ((USB_TypeDef *)USB_BASE)`
479
480			`#define WDG ((WDG_TypeDef *)WDG_BASE)`
481
482			`#define XTI ((XTI_TypeDef *)XTI_BASE)`
483
484			`#define IRQVectors ((IRQVectors_TypeDef *)&T0TIMI_Addr)`
485
486			`#else /* DEBUG */`
487
488			`#ifdef _ADC12`
489			`EXT ADC12_TypeDef *ADC12;`
490			`#endif`
491
492			`#ifdef _APB`
493			`#ifdef _APB1`
494			`EXT APB_TypeDef *APB1;`
495			`#endif`
496			`#ifdef _APB2`
497			`EXT APB_TypeDef *APB2;`
498			`#endif`
499			`#endif`
500
501			`#ifdef _BSPI`
502			`#ifdef _BSPI0`
503			`EXT BSPI_TypeDef *BSPI0;`
504			`#endif`
505			`#ifdef _BSPI1`
506			`EXT BSPI_TypeDef *BSPI1;`
507			`#endif`
508			`#endif`
509
510			`#ifdef _CAN`
511			`EXT CAN_TypeDef *CAN;`
512			`#endif`
513
514			`#ifdef _EIC`
515			`EXT EIC_TypeDef *EIC;`
516			`#endif`
517
518			`#ifdef _EMI`
519			`EXT EMI_TypeDef *EMI;`
520			`#endif`
521
522			`#ifdef _FLASH`
523			`EXT FLASHR_TypeDef *FLASHR;`
524			`EXT FLASHPR_TypeDef *FLASHPR;`
525			`#endif`
526
527			`#ifdef _GPIO`
528			`#ifdef _GPIO0`
529			`EXT GPIO_TypeDef *GPIO0;`
530			`#endif`
531			`#ifdef _GPIO1`
532			`EXT GPIO_TypeDef *GPIO1;`
533			`#endif`
534			`#ifdef _GPIO2`
535			`EXT GPIO_TypeDef *GPIO2;`
536			`#endif`
537			`#endif`
538
539			`#ifdef _I2C`
540			`#ifdef _I2C0`
541			`EXT I2C_TypeDef *I2C0;`
542			`#endif`
543			`#ifdef _I2C1`
544			`EXT I2C_TypeDef *I2C1;`
545			`#endif`
546			`#endif`
547
548			`#ifdef _PCU`
549			`EXT PCU_TypeDef *PCU;`
550			`#endif`
551
552			`#ifdef _RCCU`
553			`EXT RCCU_TypeDef *RCCU;`
554			`#endif`
555
556			`#ifdef _RTC`
557			`EXT RTC_TypeDef *RTC;`
558			`#endif`
559
560			`#ifdef _TIM`
561			`#ifdef _TIM0`
562			`EXT TIM_TypeDef *TIM0;`
563			`#endif`
564			`#ifdef _TIM1`
565			`EXT TIM_TypeDef *TIM1;`
566			`#endif`
567			`#ifdef _TIM2`
568			`EXT TIM_TypeDef *TIM2;`
569			`#endif`
570			`#ifdef _TIM3`
571			`EXT TIM_TypeDef *TIM3;`
572			`#endif`
573			`#endif`
574
575			`#ifdef _UART`
576			`#ifdef _UART0`
577			`EXT UART_TypeDef *UART0;`
578			`#endif`
579			`#ifdef _UART1`
580			`EXT UART_TypeDef *UART1;`
581			`#endif`
582			`#ifdef _UART2`
583			`EXT UART_TypeDef *UART2;`
584			`#endif`
585			`#ifdef _UART3`
586			`EXT UART_TypeDef *UART3;`
587			`#endif`
588			`#endif`
589
590			`#ifdef _USB`
591			`EXT USB_TypeDef *USB;`
592			`#endif`
593
594			`#ifdef _WDG`
595			`EXT WDG_TypeDef *WDG;`
596			`#endif`
597
598			`#ifdef _XTI`
599			`EXT XTI_TypeDef *XTI;`
600			`#endif`
601
602			`#ifdef _IRQVectors`
603			`EXT IRQVectors_TypeDef *IRQVectors;`
604			`#endif`
605
606			`#endif /* DEBUG */`
607
608			`#endif /* __71x_map_H */`
609
610			`/***************** (C) COPYRIGHT 2003 STMicroelectronics *END OF FILE**/`