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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [ARM7_STR75x_GCC/] [STLibrary/] [inc/] [75x_map.h] - Blame information for rev 605

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/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
* File Name          : 75x_map.h
* Author             : MCD Application Team
* Date First Issued  : 03/10/2006
* Description        : This file contains all the peripheral register's definitions
*                      and memory mapping.
********************************************************************************
* History:
* 07/17/2006 : V1.0
* 03/10/2006 : V0.1
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
 
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __75x_MAP_H
#define __75x_MAP_H
 
#ifndef EXT
  #define EXT extern
#endif /* EXT */
 
/* Includes ------------------------------------------------------------------*/
#include "75x_conf.h"
#include "75x_type.h"
 
/* Exported types ------------------------------------------------------------*/
/******************************************************************************/
/*                          IP registers structures                           */
/******************************************************************************/
 
/*------------------------ Analog to Digital Converter -----------------------*/
typedef struct
{
  vu16 CLR0;
  u16  EMPTY1;
  vu16 CLR1;
  u16  EMPTY2;
  vu16 CLR2;
  u16  EMPTY3;
  vu16 CLR3;
  u16  EMPTY4;
  vu16 CLR4;
  u16  EMPTY5;
  vu16 TRA0;
  u16  EMPTY6;
  vu16 TRA1;
  u16  EMPTY7;
  vu16 TRA2;
  u16  EMPTY8;
  vu16 TRA3;
  u16  EMPTY9;
  vu16 TRB0;
  u16  EMPTY10;
  vu16 TRB1;
  u16  EMPTY11;
  vu16 TRB2;
  u16  EMPTY12;
  vu16 TRB3;
  u16  EMPTY13;
  vu16 DMAR;
  u16  EMPTY14[7];
  vu16 DMAE;
  u16  EMPTY15 ;
  vu16 PBR;
  u16  EMPTY16;
  vu16 IMR;
  u16  EMPTY17;
  vu16 D0;
  u16  EMPTY18;
  vu16 D1;
  u16  EMPTY19;
  vu16 D2;
  u16  EMPTY20;
  vu16 D3;
  u16  EMPTY21;
  vu16 D4;
  u16  EMPTY22;
  vu16 D5;
  u16  EMPTY23;
  vu16 D6;
  u16  EMPTY24;
  vu16 D7;
  u16  EMPTY25;
  vu16 D8;
  u16  EMPTY26;
  vu16 D9;
  u16  EMPTY27;
  vu16 D10;
  u16  EMPTY28;
  vu16 D11;
  u16  EMPTY29;
  vu16 D12;
  u16  EMPTY30;
  vu16 D13;
  u16  EMPTY31;
  vu16 D14;
  u16  EMPTY32;
  vu16 D15;
  u16  EMPTY33;
} ADC_TypeDef;
 
/*------------------------ Controller Area Network ---------------------------*/
typedef struct
{
  vu16 CRR;
  u16  EMPTY1;
  vu16 CMR;
  u16  EMPTY2;
  vu16 M1R;
  u16  EMPTY3;
  vu16 M2R;
  u16  EMPTY4;
  vu16 A1R;
  u16  EMPTY5;
  vu16 A2R;
  u16  EMPTY6;
  vu16 MCR;
  u16  EMPTY7;
  vu16 DA1R;
  u16  EMPTY8;
  vu16 DA2R;
  u16  EMPTY9;
  vu16 DB1R;
  u16  EMPTY10;
  vu16 DB2R;
  u16  EMPTY11[27];
} CAN_MsgObj_TypeDef;
 
typedef struct
{
  vu16 CR;
  u16  EMPTY1;
  vu16 SR;
  u16  EMPTY2;
  vu16 ERR;
  u16  EMPTY3;
  vu16 BTR;
  u16  EMPTY4;
  vu16 IDR;
  u16  EMPTY5;
  vu16 TESTR;
  u16  EMPTY6;
  vu16 BRPR;
  u16  EMPTY7[3];
  CAN_MsgObj_TypeDef sMsgObj[2];
  u16  EMPTY8[16];
  vu16 TXR1R;
  u16  EMPTY9;
  vu16 TXR2R;
  u16  EMPTY10[13];
  vu16 ND1R;
  u16  EMPTY11;
  vu16 ND2R;
  u16  EMPTY12[13];
  vu16 IP1R;
  u16  EMPTY13;
  vu16 IP2R;
  u16  EMPTY14[13];
  vu16 MV1R;
  u16  EMPTY15;
  vu16 MV2R;
  u16  EMPTY16;
} CAN_TypeDef;
 
/*--------------------------- Configuration Register -------------------------*/
typedef struct
{
  vu32 GLCONF;
} CFG_TypeDef;
 
/*-------------------------------- DMA Controller ----------------------------*/
typedef struct
{
  vu16  SOURCEL;
  u16   EMPTY1;
  vu16  SOURCEH;
  u16   EMPTY2;
  vu16  DESTL;
  u16   EMPTY3;
  vu16  DESTH;
  u16   EMPTY4;
  vu16  MAX;
  u16   EMPTY5;
  vu16  CTRL;
  u16   EMPTY6;
  vuc16 SOCURRH;
  u16   EMPTY7;
  vuc16 SOCURRL;
  u16   EMPTY8;
  vuc16 DECURRH;
  u16   EMPTY9;
  vuc16 DECURRL;
  u16   EMPTY10;
  vuc16 TCNT;
  u16   EMPTY11;
  vu16  LUBUFF;
  u16   EMPTY12;
} DMA_Stream_TypeDef;
 
typedef struct
{
  vu16 MASK;
  u16  EMPTY4;
  vu16 CLR;
  u16  EMPTY5;
  vuc16 STATUS;
  u16  EMPTY6;
  vu16 LAST;
  u16  EMPTY7;
} DMA_TypeDef;
 
/*----------------------- Enhanced Interrupt Controller ----------------------*/
typedef struct
{
  vu32 ICR;
  vuc32 CICR;
  vu32 CIPR;
  u32  EMPTY1;
  vu32 FIER;
  vu32 FIPR;
  vu32 IVR;
  vu32 FIR;
  vu32 IER;
  u32  EMPTY2[7];
  vu32 IPR;
  u32  EMPTY3[7];
  vu32 SIRn[32];
} EIC_TypeDef;
 
/*------------------------- External Interrupt Controller --------------------*/
typedef struct
{
  vu32 MR;
  vu32 TSR;
  vu32 SWIR;
  vu32 PR;
} EXTIT_TypeDef;
 
/*-------------------------- General Purpose IO ports ------------------------*/
typedef struct
{
  vu32 PC0;
  vu32 PC1;
  vu32 PC2;
  vu32 PD;
  vu32 PM;
} GPIO_TypeDef;
 
typedef struct
{
  vu32 REMAP0R;
  vu32 REMAP1R;
} GPIOREMAP_TypeDef;
 
/*--------------------------------- I2C interface ----------------------------*/
typedef struct
{
  vu8 CR;
  u8  EMPTY1[3];
  vu8 SR1;
  u8  EMPTY2[3];
  vu8 SR2;
  u8  EMPTY3[3];
  vu8 CCR;
  u8  EMPTY4[3];
  vu8 OAR1;
  u8  EMPTY5[3];
  vu8 OAR2;
  u8  EMPTY6[3];
  vu8 DR;
  u8  EMPTY7[3];
  vu8 ECCR;
  u8  EMPTY8[3];
} I2C_TypeDef;
 
/*---------------------------- Power, Reset and Clocks -----------------------*/
typedef  struct
{
  vu32 CLKCTL;
  vu32 RFSR;
  vu32 PWRCTRL;
  u32  EMPTY1;
  vu32 PCLKEN;
  vu32 PSWRES;
  u32  EMPTY2[2];
  vu32 BKP0;
  vu32 BKP1;
} MRCC_TypeDef;
 
/*-------------------------------- Real Time Clock ---------------------------*/
typedef struct
{
  vu16 CRH;
  u16  EMPTY;
  vu16 CRL;
  u16  EMPTY1;
  vu16 PRLH;
  u16  EMPTY2;
  vu16 PRLL;
  u16  EMPTY3;
  vu16 DIVH;
  u16  EMPTY4;
  vu16 DIVL;
  u16  EMPTY5;
  vu16 CNTH;
  u16  EMPTY6;
  vu16 CNTL;
  u16  EMPTY7;
  vu16 ALRH;
  u16  EMPTY8;
  vu16 ALRL;
  u16  EMPTY9;
} RTC_TypeDef;
 
/*---------------------------- Serial Memory Interface -----------------------*/
typedef struct
{
  vu32 CR1;
  vu32 CR2;
  vu32 SR;
  vu32 TR;
  vuc32 RR;
} SMI_TypeDef;
 
/*--------------------------------- Timer Base -------------------------------*/
typedef struct
{
  vu16 CR;
  u16  EMPTY1;
  vu16 SCR;
  u16  EMPTY2;
  vu16 IMCR;
  u16  EMPTY3[7];
  vu16 RSR;
  u16  EMPTY4;
  vu16 RER;
  u16  EMPTY5;
  vu16 ISR;
  u16  EMPTY6;
  vu16 CNT;
  u16  EMPTY7;
  vu16 PSC;
  u16  EMPTY8[3];
  vu16 ARR;
  u16  EMPTY9[13];
  vu16 ICR1;
  u16  EMPTY10;
} TB_TypeDef;
 
/*------------------------------------ TIM -----------------------------------*/
typedef struct
{
  vu16 CR;
  u16  EMPTY1;
  vu16 SCR;
  u16  EMPTY2;
  vu16 IMCR;
  u16  EMPTY3;
  vu16 OMR1;
  u16  EMPTY4[5];
  vu16 RSR;
  u16  EMPTY5;
  vu16 RER;
  u16  EMPTY6;
  vu16 ISR;
  u16  EMPTY7;
  vu16 CNT;
  u16  EMPTY8;
  vu16 PSC;
  u16  EMPTY9[3];
  vu16 ARR;
  u16  EMPTY10;
  vu16 OCR1;
  u16  EMPTY11;
  vu16 OCR2;
  u16  EMPTY12[9];
  vu16 ICR1;
  u16  EMPTY13;
  vu16 ICR2;
  u16  EMPTY14[9];
  vu16 DMAB;
  u16  EMPTY15;
} TIM_TypeDef;
 
/*------------------------------------ PWM -----------------------------------*/
typedef struct
{
  vu16 CR;
  u16  EMPTY1;
  vu16 SCR;
  u16  EMPTY2[3];
  vu16 OMR1;
  u16  EMPTY3;
  vu16 OMR2;
  u16  EMPTY4[3];
  vu16 RSR;
  u16  EMPTY5;
  vu16 RER;
  u16  EMPTY6;
  vu16 ISR;
  u16  EMPTY7;
  vu16 CNT;
  u16  EMPTY8;
  vu16 PSC;
  u16  EMPTY9;
  vu16 RCR;
  u16  EMPTY10;
  vu16 ARR;
  u16  EMPTY11;
  vu16 OCR1;
  u16  EMPTY12;
  vu16 OCR2;
  u16  EMPTY13;
  vu16 OCR3;
  u16  EMPTY14[15];
  vu16 DTR;
  u16  EMPTY15;
  vu16 DMAB;
  u16  EMPTY16;
} PWM_TypeDef;
 
/*----------------------- Synchronous Serial Peripheral ----------------------*/
typedef struct
{
  vu32 CR0;
  vu32 CR1;
  vu32 DR;
  vu32 SR;
  vu32 PR;
  vu32 IMSCR;
  vu32 RISR;
  vu32 MISR;
  vu32 ICR;
  vu32 DMACR;
} SSP_TypeDef;
 
/*---------------- Universal Asynchronous Receiver Transmitter ---------------*/
typedef struct
{
  vu16 DR;
  u16  EMPTY;
  vu16 RSR;
  u16  EMPTY1[9];
  vu16 FR;
  u16  EMPTY2;
  vu16 BKR;
  u16  EMPTY3[3];
  vu16 IBRD;
  u16  EMPTY4;
  vu16 FBRD;
  u16  EMPTY5;
  vu16 LCR;
  u16  EMPTY6;
  vu16 CR;
  u16  EMPTY7;
  vu16 IFLS;
  u16  EMPTY8;
  vu16 IMSC;
  u16  EMPTY9;
  vu16 RIS;
  u16  EMPTY10;
  vu16 MIS;
  u16  EMPTY11;
  vu16 ICR;
  u16  EMPTY12;
  vu16 DMACR;
  u16  EMPTY13;
} UART_TypeDef;
 
/*---------------------------------- WATCHDOG --------------------------------*/
typedef struct
{
  vu16 CR;
  u16  EMPTY1;
  vu16 PR;
  u16 EMPTY2;
  vu16 VR;
  u16  EMPTY3;
  vu16 CNT;
  u16  EMPTY4;
  vu16 SR;
  u16  EMPTY5;
  vu16 MR;
  u16  EMPTY6;
  vu16 KR;
  u16  EMPTY7;
} WDG_TypeDef;
 
/*******************************************************************************
*                      Peripherals' Base addresses
*******************************************************************************/
 
#define SRAM_BASE      0x40000000
 
#define CONFIG_BASE    0x60000000
 
#define SMIR_BASE      0x90000000
 
#define PERIPH_BASE    0xFFFF0000
 
#define CFG_BASE            (CONFIG_BASE + 0x0010)
#define MRCC_BASE           (CONFIG_BASE + 0x0020)
#define ADC_BASE            (PERIPH_BASE + 0x8400)
#define TB_BASE             (PERIPH_BASE + 0x8800)
#define TIM0_BASE           (PERIPH_BASE + 0x8C00)
#define TIM1_BASE           (PERIPH_BASE + 0x9000)
#define TIM2_BASE           (PERIPH_BASE + 0x9400)
#define PWM_BASE            (PERIPH_BASE + 0x9800)
#define WDG_BASE            (PERIPH_BASE + 0xB000)
#define SSP0_BASE           (PERIPH_BASE + 0xB800)
#define SSP1_BASE           (PERIPH_BASE + 0xBC00)
#define CAN_BASE            (PERIPH_BASE + 0xC400)
#define I2C_BASE            (PERIPH_BASE + 0xCC00)
#define UART0_BASE          (PERIPH_BASE + 0xD400)
#define UART1_BASE          (PERIPH_BASE + 0xD800)
#define UART2_BASE          (PERIPH_BASE + 0xDC00)
#define GPIO0_BASE          (PERIPH_BASE + 0xE400)
#define GPIOREMAP_BASE      (PERIPH_BASE + 0xE420)
#define GPIO1_BASE          (PERIPH_BASE + 0xE440)
#define GPIO2_BASE          (PERIPH_BASE + 0xE480)
#define DMA_BASE            (PERIPH_BASE + 0xECF0)
#define DMA_Stream0_BASE    (PERIPH_BASE + 0xEC00)
#define DMA_Stream1_BASE    (PERIPH_BASE + 0xEC40)
#define DMA_Stream2_BASE    (PERIPH_BASE + 0xEC80)
#define DMA_Stream3_BASE    (PERIPH_BASE + 0xECC0)
#define RTC_BASE            (PERIPH_BASE + 0xF000)
#define EXTIT_BASE          (PERIPH_BASE + 0xF400)
#define EIC_BASE            (PERIPH_BASE + 0xF800)
 
/*******************************************************************************
                            IPs' declaration
*******************************************************************************/
 
/*------------------- Non Debug Mode -----------------------------------------*/
 
#ifndef DEBUG
  #define SMI            ((SMI_TypeDef *)           SMIR_BASE)
  #define CFG            ((CFG_TypeDef *)           CFG_BASE)
  #define MRCC           ((MRCC_TypeDef *)          MRCC_BASE)
  #define ADC            ((ADC_TypeDef *)           ADC_BASE)
  #define TB             ((TB_TypeDef *)            TB_BASE)
  #define TIM0           ((TIM_TypeDef *)           TIM0_BASE)
  #define TIM1           ((TIM_TypeDef *)           TIM1_BASE)
  #define TIM2           ((TIM_TypeDef *)           TIM2_BASE)
  #define PWM            ((PWM_TypeDef *)           PWM_BASE)
  #define WDG            ((WDG_TypeDef *)           WDG_BASE)
  #define SSP0           ((SSP_TypeDef *)           SSP0_BASE)
  #define SSP1           ((SSP_TypeDef *)           SSP1_BASE)
  #define CAN            ((CAN_TypeDef *)           CAN_BASE)
  #define I2C            ((I2C_TypeDef *)           I2C_BASE)
  #define UART0          ((UART_TypeDef *)          UART0_BASE)
  #define UART1          ((UART_TypeDef *)          UART1_BASE)
  #define UART2          ((UART_TypeDef *)          UART2_BASE)
  #define GPIO0          ((GPIO_TypeDef *)          GPIO0_BASE)
  #define GPIOREMAP      ((GPIOREMAP_TypeDef *)     GPIOREMAP_BASE)
  #define GPIO1          ((GPIO_TypeDef *)          GPIO1_BASE)
  #define GPIO2          ((GPIO_TypeDef *)          GPIO2_BASE)
  #define DMA            ((DMA_TypeDef *)           DMA_BASE)
  #define DMA_Stream0    ((DMA_Stream_TypeDef *)    DMA_Stream0_BASE)
  #define DMA_Stream1    ((DMA_Stream_TypeDef *)    DMA_Stream1_BASE)
  #define DMA_Stream2    ((DMA_Stream_TypeDef *)    DMA_Stream2_BASE)
  #define DMA_Stream3    ((DMA_Stream_TypeDef *)    DMA_Stream3_BASE)
  #define RTC            ((RTC_TypeDef *)           RTC_BASE)
  #define EXTIT          ((EXTIT_TypeDef *)         EXTIT_BASE)
  #define EIC            ((EIC_TypeDef *)           EIC_BASE)
#else   /* DEBUG */
  #ifdef _SMI
    EXT SMI_TypeDef           *SMI;
  #endif /*_SMI */
 
  #ifdef _CFG
    EXT CFG_TypeDef           *CFG;
  #endif /*_CFG */
 
  #ifdef _MRCC
    EXT MRCC_TypeDef          *MRCC;
  #endif /*_MRCC */
 
  #ifdef _ADC
    EXT ADC_TypeDef           *ADC;
  #endif /*_ADC */  
 
  #ifdef _TB
    EXT TB_TypeDef            *TB;
  #endif /*_TB */
 
  #ifdef _TIM0
    EXT TIM_TypeDef           *TIM0;
  #endif /*_TIM0 */
 
  #ifdef _TIM1
    EXT TIM_TypeDef           *TIM1;
  #endif /*_TIM1 */
 
  #ifdef _TIM2
    EXT TIM_TypeDef           *TIM2;
  #endif /*_TIM2 */
 
  #ifdef _PWM
    EXT PWM_TypeDef           *PWM;
  #endif /*_PWM */
 
  #ifdef _WDG
    EXT WDG_TypeDef           *WDG;
  #endif /*_WDG */
 
  #ifdef _SSP0
    EXT SSP_TypeDef           *SSP0;
  #endif /*_SSP0 */
 
  #ifdef _SSP1
    EXT SSP_TypeDef           *SSP1;
  #endif /*_SSP1 */
 
  #ifdef _CAN
    EXT CAN_TypeDef           *CAN;
  #endif /*_CAN */
 
  #ifdef _I2C
    EXT I2C_TypeDef           *I2C;
  #endif /*_I2C */
 
  #ifdef _UART0
    EXT UART_TypeDef          *UART0;
  #endif /*_UART0 */
 
  #ifdef _UART1
    EXT UART_TypeDef          *UART1;
  #endif /*_UART1 */
 
  #ifdef _UART2
    EXT UART_TypeDef          *UART2;
  #endif /*_UART2 */
 
  #ifdef _GPIO0
    EXT GPIO_TypeDef          *GPIO0;
  #endif /*_GPIO0 */
 
  #ifdef _GPIOREMAP
    EXT GPIOREMAP_TypeDef     *GPIOREMAP;
  #endif /*_GPIOREMAP */
 
  #ifdef _GPIO1
    EXT GPIO_TypeDef          *GPIO1;
  #endif /*_GPIO1 */
 
  #ifdef _GPIO2
    EXT GPIO_TypeDef          *GPIO2;
  #endif /*_GPIO2 */
 
  #ifdef _DMA
    EXT DMA_TypeDef           *DMA;
  #endif /*_DMA */
 
  #ifdef _DMA_Stream0
    EXT DMA_Stream_TypeDef    *DMA_Stream0;
  #endif /*_DMA_Stream0 */
 
  #ifdef _DMA_Stream1
    EXT DMA_Stream_TypeDef    *DMA_Stream1;
  #endif /*_DMA_Stream1 */
 
  #ifdef _DMA_Stream2
    EXT DMA_Stream_TypeDef    *DMA_Stream2;
  #endif /*_DMA_Stream2 */
 
  #ifdef _DMA_Stream3
    EXT DMA_Stream_TypeDef    *DMA_Stream3;
  #endif /*_DMA_Stream3 */
 
  #ifdef _RTC
    EXT RTC_TypeDef           *RTC;
  #endif /*_RTC */
 
  #ifdef _EXTIT
    EXT EXTIT_TypeDef         *EXTIT;
  #endif /*_EXTIT */
 
  #ifdef _EIC
    EXT EIC_TypeDef           *EIC;
  #endif /*_EIC */
 
#endif  /* DEBUG */
 
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
 
#endif /* __75x_MAP_H */
 
/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/

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Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [ARM7_STR75x_GCC/] [STLibrary/] [inc/] [75x_map.h] - Blame information for rev 605

Line No.	Rev	Author	Line
1	577	jeremybenn	`/****************** (C) COPYRIGHT 2006 STMicroelectronics ******************`
2			`* File Name : 75x_map.h`
3			`* Author : MCD Application Team`
4			`* Date First Issued : 03/10/2006`
5			`* Description : This file contains all the peripheral register's definitions`
6			`* and memory mapping.`
7			`********************************************************************************`
8			`* History:`
9			`* 07/17/2006 : V1.0`
10			`* 03/10/2006 : V0.1`
11			`********************************************************************************`
12			`* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS`
13			`* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.`
14			`* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,`
15			`* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE`
16			`* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING`
17			`* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.`
18			`*******************************************************************************/`
19
20			`/* Define to prevent recursive inclusion -------------------------------------*/`
21			`#ifndef __75x_MAP_H`
22			`#define __75x_MAP_H`
23
24			`#ifndef EXT`
25			`#define EXT extern`
26			`#endif /* EXT */`
27
28			`/* Includes ------------------------------------------------------------------*/`
29			`#include "75x_conf.h"`
30			`#include "75x_type.h"`
31
32			`/* Exported types ------------------------------------------------------------*/`
33			`/******************************************************************************/`
34			`/* IP registers structures */`
35			`/******************************************************************************/`
36
37			`/------------------------ Analog to Digital Converter -----------------------/`
38			`typedef struct`
39			`{`
40			`vu16 CLR0;`
41			`u16 EMPTY1;`
42			`vu16 CLR1;`
43			`u16 EMPTY2;`
44			`vu16 CLR2;`
45			`u16 EMPTY3;`
46			`vu16 CLR3;`
47			`u16 EMPTY4;`
48			`vu16 CLR4;`
49			`u16 EMPTY5;`
50			`vu16 TRA0;`
51			`u16 EMPTY6;`
52			`vu16 TRA1;`
53			`u16 EMPTY7;`
54			`vu16 TRA2;`
55			`u16 EMPTY8;`
56			`vu16 TRA3;`
57			`u16 EMPTY9;`
58			`vu16 TRB0;`
59			`u16 EMPTY10;`
60			`vu16 TRB1;`
61			`u16 EMPTY11;`
62			`vu16 TRB2;`
63			`u16 EMPTY12;`
64			`vu16 TRB3;`
65			`u16 EMPTY13;`
66			`vu16 DMAR;`
67			`u16 EMPTY14[7];`
68			`vu16 DMAE;`
69			`u16 EMPTY15 ;`
70			`vu16 PBR;`
71			`u16 EMPTY16;`
72			`vu16 IMR;`
73			`u16 EMPTY17;`
74			`vu16 D0;`
75			`u16 EMPTY18;`
76			`vu16 D1;`
77			`u16 EMPTY19;`
78			`vu16 D2;`
79			`u16 EMPTY20;`
80			`vu16 D3;`
81			`u16 EMPTY21;`
82			`vu16 D4;`
83			`u16 EMPTY22;`
84			`vu16 D5;`
85			`u16 EMPTY23;`
86			`vu16 D6;`
87			`u16 EMPTY24;`
88			`vu16 D7;`
89			`u16 EMPTY25;`
90			`vu16 D8;`
91			`u16 EMPTY26;`
92			`vu16 D9;`
93			`u16 EMPTY27;`
94			`vu16 D10;`
95			`u16 EMPTY28;`
96			`vu16 D11;`
97			`u16 EMPTY29;`
98			`vu16 D12;`
99			`u16 EMPTY30;`
100			`vu16 D13;`
101			`u16 EMPTY31;`
102			`vu16 D14;`
103			`u16 EMPTY32;`
104			`vu16 D15;`
105			`u16 EMPTY33;`
106			`} ADC_TypeDef;`
107
108			`/------------------------ Controller Area Network ---------------------------/`
109			`typedef struct`
110			`{`
111			`vu16 CRR;`
112			`u16 EMPTY1;`
113			`vu16 CMR;`
114			`u16 EMPTY2;`
115			`vu16 M1R;`
116			`u16 EMPTY3;`
117			`vu16 M2R;`
118			`u16 EMPTY4;`
119			`vu16 A1R;`
120			`u16 EMPTY5;`
121			`vu16 A2R;`
122			`u16 EMPTY6;`
123			`vu16 MCR;`
124			`u16 EMPTY7;`
125			`vu16 DA1R;`
126			`u16 EMPTY8;`
127			`vu16 DA2R;`
128			`u16 EMPTY9;`
129			`vu16 DB1R;`
130			`u16 EMPTY10;`
131			`vu16 DB2R;`
132			`u16 EMPTY11[27];`
133			`} CAN_MsgObj_TypeDef;`
134
135			`typedef struct`
136			`{`
137			`vu16 CR;`
138			`u16 EMPTY1;`
139			`vu16 SR;`
140			`u16 EMPTY2;`
141			`vu16 ERR;`
142			`u16 EMPTY3;`
143			`vu16 BTR;`
144			`u16 EMPTY4;`
145			`vu16 IDR;`
146			`u16 EMPTY5;`
147			`vu16 TESTR;`
148			`u16 EMPTY6;`
149			`vu16 BRPR;`
150			`u16 EMPTY7[3];`
151			`CAN_MsgObj_TypeDef sMsgObj[2];`
152			`u16 EMPTY8[16];`
153			`vu16 TXR1R;`
154			`u16 EMPTY9;`
155			`vu16 TXR2R;`
156			`u16 EMPTY10[13];`
157			`vu16 ND1R;`
158			`u16 EMPTY11;`
159			`vu16 ND2R;`
160			`u16 EMPTY12[13];`
161			`vu16 IP1R;`
162			`u16 EMPTY13;`
163			`vu16 IP2R;`
164			`u16 EMPTY14[13];`
165			`vu16 MV1R;`
166			`u16 EMPTY15;`
167			`vu16 MV2R;`
168			`u16 EMPTY16;`
169			`} CAN_TypeDef;`
170
171			`/--------------------------- Configuration Register -------------------------/`
172			`typedef struct`
173			`{`
174			`vu32 GLCONF;`
175			`} CFG_TypeDef;`
176
177			`/-------------------------------- DMA Controller ----------------------------/`
178			`typedef struct`
179			`{`
180			`vu16 SOURCEL;`
181			`u16 EMPTY1;`
182			`vu16 SOURCEH;`
183			`u16 EMPTY2;`
184			`vu16 DESTL;`
185			`u16 EMPTY3;`
186			`vu16 DESTH;`
187			`u16 EMPTY4;`
188			`vu16 MAX;`
189			`u16 EMPTY5;`
190			`vu16 CTRL;`
191			`u16 EMPTY6;`
192			`vuc16 SOCURRH;`
193			`u16 EMPTY7;`
194			`vuc16 SOCURRL;`
195			`u16 EMPTY8;`
196			`vuc16 DECURRH;`
197			`u16 EMPTY9;`
198			`vuc16 DECURRL;`
199			`u16 EMPTY10;`
200			`vuc16 TCNT;`
201			`u16 EMPTY11;`
202			`vu16 LUBUFF;`
203			`u16 EMPTY12;`
204			`} DMA_Stream_TypeDef;`
205
206			`typedef struct`
207			`{`
208			`vu16 MASK;`
209			`u16 EMPTY4;`
210			`vu16 CLR;`
211			`u16 EMPTY5;`
212			`vuc16 STATUS;`
213			`u16 EMPTY6;`
214			`vu16 LAST;`
215			`u16 EMPTY7;`
216			`} DMA_TypeDef;`
217
218			`/----------------------- Enhanced Interrupt Controller ----------------------/`
219			`typedef struct`
220			`{`
221			`vu32 ICR;`
222			`vuc32 CICR;`
223			`vu32 CIPR;`
224			`u32 EMPTY1;`
225			`vu32 FIER;`
226			`vu32 FIPR;`
227			`vu32 IVR;`
228			`vu32 FIR;`
229			`vu32 IER;`
230			`u32 EMPTY2[7];`
231			`vu32 IPR;`
232			`u32 EMPTY3[7];`
233			`vu32 SIRn[32];`
234			`} EIC_TypeDef;`
235
236			`/------------------------- External Interrupt Controller --------------------/`
237			`typedef struct`
238			`{`
239			`vu32 MR;`
240			`vu32 TSR;`
241			`vu32 SWIR;`
242			`vu32 PR;`
243			`} EXTIT_TypeDef;`
244
245			`/-------------------------- General Purpose IO ports ------------------------/`
246			`typedef struct`
247			`{`
248			`vu32 PC0;`
249			`vu32 PC1;`
250			`vu32 PC2;`
251			`vu32 PD;`
252			`vu32 PM;`
253			`} GPIO_TypeDef;`
254
255			`typedef struct`
256			`{`
257			`vu32 REMAP0R;`
258			`vu32 REMAP1R;`
259			`} GPIOREMAP_TypeDef;`
260
261			`/--------------------------------- I2C interface ----------------------------/`
262			`typedef struct`
263			`{`
264			`vu8 CR;`
265			`u8 EMPTY1[3];`
266			`vu8 SR1;`
267			`u8 EMPTY2[3];`
268			`vu8 SR2;`
269			`u8 EMPTY3[3];`
270			`vu8 CCR;`
271			`u8 EMPTY4[3];`
272			`vu8 OAR1;`
273			`u8 EMPTY5[3];`
274			`vu8 OAR2;`
275			`u8 EMPTY6[3];`
276			`vu8 DR;`
277			`u8 EMPTY7[3];`
278			`vu8 ECCR;`
279			`u8 EMPTY8[3];`
280			`} I2C_TypeDef;`
281
282			`/---------------------------- Power, Reset and Clocks -----------------------/`
283			`typedef struct`
284			`{`
285			`vu32 CLKCTL;`
286			`vu32 RFSR;`
287			`vu32 PWRCTRL;`
288			`u32 EMPTY1;`
289			`vu32 PCLKEN;`
290			`vu32 PSWRES;`
291			`u32 EMPTY2[2];`
292			`vu32 BKP0;`
293			`vu32 BKP1;`
294			`} MRCC_TypeDef;`
295
296			`/-------------------------------- Real Time Clock ---------------------------/`
297			`typedef struct`
298			`{`
299			`vu16 CRH;`
300			`u16 EMPTY;`
301			`vu16 CRL;`
302			`u16 EMPTY1;`
303			`vu16 PRLH;`
304			`u16 EMPTY2;`
305			`vu16 PRLL;`
306			`u16 EMPTY3;`
307			`vu16 DIVH;`
308			`u16 EMPTY4;`
309			`vu16 DIVL;`
310			`u16 EMPTY5;`
311			`vu16 CNTH;`
312			`u16 EMPTY6;`
313			`vu16 CNTL;`
314			`u16 EMPTY7;`
315			`vu16 ALRH;`
316			`u16 EMPTY8;`
317			`vu16 ALRL;`
318			`u16 EMPTY9;`
319			`} RTC_TypeDef;`
320
321			`/---------------------------- Serial Memory Interface -----------------------/`
322			`typedef struct`
323			`{`
324			`vu32 CR1;`
325			`vu32 CR2;`
326			`vu32 SR;`
327			`vu32 TR;`
328			`vuc32 RR;`
329			`} SMI_TypeDef;`
330
331			`/--------------------------------- Timer Base -------------------------------/`
332			`typedef struct`
333			`{`
334			`vu16 CR;`
335			`u16 EMPTY1;`
336			`vu16 SCR;`
337			`u16 EMPTY2;`
338			`vu16 IMCR;`
339			`u16 EMPTY3[7];`
340			`vu16 RSR;`
341			`u16 EMPTY4;`
342			`vu16 RER;`
343			`u16 EMPTY5;`
344			`vu16 ISR;`
345			`u16 EMPTY6;`
346			`vu16 CNT;`
347			`u16 EMPTY7;`
348			`vu16 PSC;`
349			`u16 EMPTY8[3];`
350			`vu16 ARR;`
351			`u16 EMPTY9[13];`
352			`vu16 ICR1;`
353			`u16 EMPTY10;`
354			`} TB_TypeDef;`
355
356			`/------------------------------------ TIM -----------------------------------/`
357			`typedef struct`
358			`{`
359			`vu16 CR;`
360			`u16 EMPTY1;`
361			`vu16 SCR;`
362			`u16 EMPTY2;`
363			`vu16 IMCR;`
364			`u16 EMPTY3;`
365			`vu16 OMR1;`
366			`u16 EMPTY4[5];`
367			`vu16 RSR;`
368			`u16 EMPTY5;`
369			`vu16 RER;`
370			`u16 EMPTY6;`
371			`vu16 ISR;`
372			`u16 EMPTY7;`
373			`vu16 CNT;`
374			`u16 EMPTY8;`
375			`vu16 PSC;`
376			`u16 EMPTY9[3];`
377			`vu16 ARR;`
378			`u16 EMPTY10;`
379			`vu16 OCR1;`
380			`u16 EMPTY11;`
381			`vu16 OCR2;`
382			`u16 EMPTY12[9];`
383			`vu16 ICR1;`
384			`u16 EMPTY13;`
385			`vu16 ICR2;`
386			`u16 EMPTY14[9];`
387			`vu16 DMAB;`
388			`u16 EMPTY15;`
389			`} TIM_TypeDef;`
390
391			`/------------------------------------ PWM -----------------------------------/`
392			`typedef struct`
393			`{`
394			`vu16 CR;`
395			`u16 EMPTY1;`
396			`vu16 SCR;`
397			`u16 EMPTY2[3];`
398			`vu16 OMR1;`
399			`u16 EMPTY3;`
400			`vu16 OMR2;`
401			`u16 EMPTY4[3];`
402			`vu16 RSR;`
403			`u16 EMPTY5;`
404			`vu16 RER;`
405			`u16 EMPTY6;`
406			`vu16 ISR;`
407			`u16 EMPTY7;`
408			`vu16 CNT;`
409			`u16 EMPTY8;`
410			`vu16 PSC;`
411			`u16 EMPTY9;`
412			`vu16 RCR;`
413			`u16 EMPTY10;`
414			`vu16 ARR;`
415			`u16 EMPTY11;`
416			`vu16 OCR1;`
417			`u16 EMPTY12;`
418			`vu16 OCR2;`
419			`u16 EMPTY13;`
420			`vu16 OCR3;`
421			`u16 EMPTY14[15];`
422			`vu16 DTR;`
423			`u16 EMPTY15;`
424			`vu16 DMAB;`
425			`u16 EMPTY16;`
426			`} PWM_TypeDef;`
427
428			`/----------------------- Synchronous Serial Peripheral ----------------------/`
429			`typedef struct`
430			`{`
431			`vu32 CR0;`
432			`vu32 CR1;`
433			`vu32 DR;`
434			`vu32 SR;`
435			`vu32 PR;`
436			`vu32 IMSCR;`
437			`vu32 RISR;`
438			`vu32 MISR;`
439			`vu32 ICR;`
440			`vu32 DMACR;`
441			`} SSP_TypeDef;`
442
443			`/---------------- Universal Asynchronous Receiver Transmitter ---------------/`
444			`typedef struct`
445			`{`
446			`vu16 DR;`
447			`u16 EMPTY;`
448			`vu16 RSR;`
449			`u16 EMPTY1[9];`
450			`vu16 FR;`
451			`u16 EMPTY2;`
452			`vu16 BKR;`
453			`u16 EMPTY3[3];`
454			`vu16 IBRD;`
455			`u16 EMPTY4;`
456			`vu16 FBRD;`
457			`u16 EMPTY5;`
458			`vu16 LCR;`
459			`u16 EMPTY6;`
460			`vu16 CR;`
461			`u16 EMPTY7;`
462			`vu16 IFLS;`
463			`u16 EMPTY8;`
464			`vu16 IMSC;`
465			`u16 EMPTY9;`
466			`vu16 RIS;`
467			`u16 EMPTY10;`
468			`vu16 MIS;`
469			`u16 EMPTY11;`
470			`vu16 ICR;`
471			`u16 EMPTY12;`
472			`vu16 DMACR;`
473			`u16 EMPTY13;`
474			`} UART_TypeDef;`
475
476			`/---------------------------------- WATCHDOG --------------------------------/`
477			`typedef struct`
478			`{`
479			`vu16 CR;`
480			`u16 EMPTY1;`
481			`vu16 PR;`
482			`u16 EMPTY2;`
483			`vu16 VR;`
484			`u16 EMPTY3;`
485			`vu16 CNT;`
486			`u16 EMPTY4;`
487			`vu16 SR;`
488			`u16 EMPTY5;`
489			`vu16 MR;`
490			`u16 EMPTY6;`
491			`vu16 KR;`
492			`u16 EMPTY7;`
493			`} WDG_TypeDef;`
494
495			`/*******************************************************************************`
496			`* Peripherals' Base addresses`
497			`*******************************************************************************/`
498
499			`#define SRAM_BASE 0x40000000`
500
501			`#define CONFIG_BASE 0x60000000`
502
503			`#define SMIR_BASE 0x90000000`
504
505			`#define PERIPH_BASE 0xFFFF0000`
506
507			`#define CFG_BASE (CONFIG_BASE + 0x0010)`
508			`#define MRCC_BASE (CONFIG_BASE + 0x0020)`
509			`#define ADC_BASE (PERIPH_BASE + 0x8400)`
510			`#define TB_BASE (PERIPH_BASE + 0x8800)`
511			`#define TIM0_BASE (PERIPH_BASE + 0x8C00)`
512			`#define TIM1_BASE (PERIPH_BASE + 0x9000)`
513			`#define TIM2_BASE (PERIPH_BASE + 0x9400)`
514			`#define PWM_BASE (PERIPH_BASE + 0x9800)`
515			`#define WDG_BASE (PERIPH_BASE + 0xB000)`
516			`#define SSP0_BASE (PERIPH_BASE + 0xB800)`
517			`#define SSP1_BASE (PERIPH_BASE + 0xBC00)`
518			`#define CAN_BASE (PERIPH_BASE + 0xC400)`
519			`#define I2C_BASE (PERIPH_BASE + 0xCC00)`
520			`#define UART0_BASE (PERIPH_BASE + 0xD400)`
521			`#define UART1_BASE (PERIPH_BASE + 0xD800)`
522			`#define UART2_BASE (PERIPH_BASE + 0xDC00)`
523			`#define GPIO0_BASE (PERIPH_BASE + 0xE400)`
524			`#define GPIOREMAP_BASE (PERIPH_BASE + 0xE420)`
525			`#define GPIO1_BASE (PERIPH_BASE + 0xE440)`
526			`#define GPIO2_BASE (PERIPH_BASE + 0xE480)`
527			`#define DMA_BASE (PERIPH_BASE + 0xECF0)`
528			`#define DMA_Stream0_BASE (PERIPH_BASE + 0xEC00)`
529			`#define DMA_Stream1_BASE (PERIPH_BASE + 0xEC40)`
530			`#define DMA_Stream2_BASE (PERIPH_BASE + 0xEC80)`
531			`#define DMA_Stream3_BASE (PERIPH_BASE + 0xECC0)`
532			`#define RTC_BASE (PERIPH_BASE + 0xF000)`
533			`#define EXTIT_BASE (PERIPH_BASE + 0xF400)`
534			`#define EIC_BASE (PERIPH_BASE + 0xF800)`
535
536			`/*******************************************************************************`
537			`IPs' declaration`
538			`*******************************************************************************/`
539
540			`/------------------- Non Debug Mode -----------------------------------------/`
541
542			`#ifndef DEBUG`
543			`#define SMI ((SMI_TypeDef *) SMIR_BASE)`
544			`#define CFG ((CFG_TypeDef *) CFG_BASE)`
545			`#define MRCC ((MRCC_TypeDef *) MRCC_BASE)`
546			`#define ADC ((ADC_TypeDef *) ADC_BASE)`
547			`#define TB ((TB_TypeDef *) TB_BASE)`
548			`#define TIM0 ((TIM_TypeDef *) TIM0_BASE)`
549			`#define TIM1 ((TIM_TypeDef *) TIM1_BASE)`
550			`#define TIM2 ((TIM_TypeDef *) TIM2_BASE)`
551			`#define PWM ((PWM_TypeDef *) PWM_BASE)`
552			`#define WDG ((WDG_TypeDef *) WDG_BASE)`
553			`#define SSP0 ((SSP_TypeDef *) SSP0_BASE)`
554			`#define SSP1 ((SSP_TypeDef *) SSP1_BASE)`
555			`#define CAN ((CAN_TypeDef *) CAN_BASE)`
556			`#define I2C ((I2C_TypeDef *) I2C_BASE)`
557			`#define UART0 ((UART_TypeDef *) UART0_BASE)`
558			`#define UART1 ((UART_TypeDef *) UART1_BASE)`
559			`#define UART2 ((UART_TypeDef *) UART2_BASE)`
560			`#define GPIO0 ((GPIO_TypeDef *) GPIO0_BASE)`
561			`#define GPIOREMAP ((GPIOREMAP_TypeDef *) GPIOREMAP_BASE)`
562			`#define GPIO1 ((GPIO_TypeDef *) GPIO1_BASE)`
563			`#define GPIO2 ((GPIO_TypeDef *) GPIO2_BASE)`
564			`#define DMA ((DMA_TypeDef *) DMA_BASE)`
565			`#define DMA_Stream0 ((DMA_Stream_TypeDef *) DMA_Stream0_BASE)`
566			`#define DMA_Stream1 ((DMA_Stream_TypeDef *) DMA_Stream1_BASE)`
567			`#define DMA_Stream2 ((DMA_Stream_TypeDef *) DMA_Stream2_BASE)`
568			`#define DMA_Stream3 ((DMA_Stream_TypeDef *) DMA_Stream3_BASE)`
569			`#define RTC ((RTC_TypeDef *) RTC_BASE)`
570			`#define EXTIT ((EXTIT_TypeDef *) EXTIT_BASE)`
571			`#define EIC ((EIC_TypeDef *) EIC_BASE)`
572			`#else /* DEBUG */`
573			`#ifdef _SMI`
574			`EXT SMI_TypeDef *SMI;`
575			`#endif /_SMI /`
576
577			`#ifdef _CFG`
578			`EXT CFG_TypeDef *CFG;`
579			`#endif /_CFG /`
580
581			`#ifdef _MRCC`
582			`EXT MRCC_TypeDef *MRCC;`
583			`#endif /_MRCC /`
584
585			`#ifdef _ADC`
586			`EXT ADC_TypeDef *ADC;`
587			`#endif /_ADC /`
588
589			`#ifdef _TB`
590			`EXT TB_TypeDef *TB;`
591			`#endif /_TB /`
592
593			`#ifdef _TIM0`
594			`EXT TIM_TypeDef *TIM0;`
595			`#endif /_TIM0 /`
596
597			`#ifdef _TIM1`
598			`EXT TIM_TypeDef *TIM1;`
599			`#endif /_TIM1 /`
600
601			`#ifdef _TIM2`
602			`EXT TIM_TypeDef *TIM2;`
603			`#endif /_TIM2 /`
604
605			`#ifdef _PWM`
606			`EXT PWM_TypeDef *PWM;`
607			`#endif /_PWM /`
608
609			`#ifdef _WDG`
610			`EXT WDG_TypeDef *WDG;`
611			`#endif /_WDG /`
612
613			`#ifdef _SSP0`
614			`EXT SSP_TypeDef *SSP0;`
615			`#endif /_SSP0 /`
616
617			`#ifdef _SSP1`
618			`EXT SSP_TypeDef *SSP1;`
619			`#endif /_SSP1 /`
620
621			`#ifdef _CAN`
622			`EXT CAN_TypeDef *CAN;`
623			`#endif /_CAN /`
624
625			`#ifdef _I2C`
626			`EXT I2C_TypeDef *I2C;`
627			`#endif /_I2C /`
628
629			`#ifdef _UART0`
630			`EXT UART_TypeDef *UART0;`
631			`#endif /_UART0 /`
632
633			`#ifdef _UART1`
634			`EXT UART_TypeDef *UART1;`
635			`#endif /_UART1 /`
636
637			`#ifdef _UART2`
638			`EXT UART_TypeDef *UART2;`
639			`#endif /_UART2 /`
640
641			`#ifdef _GPIO0`
642			`EXT GPIO_TypeDef *GPIO0;`
643			`#endif /_GPIO0 /`
644
645			`#ifdef _GPIOREMAP`
646			`EXT GPIOREMAP_TypeDef *GPIOREMAP;`
647			`#endif /_GPIOREMAP /`
648
649			`#ifdef _GPIO1`
650			`EXT GPIO_TypeDef *GPIO1;`
651			`#endif /_GPIO1 /`
652
653			`#ifdef _GPIO2`
654			`EXT GPIO_TypeDef *GPIO2;`
655			`#endif /_GPIO2 /`
656
657			`#ifdef _DMA`
658			`EXT DMA_TypeDef *DMA;`
659			`#endif /_DMA /`
660
661			`#ifdef _DMA_Stream0`
662			`EXT DMA_Stream_TypeDef *DMA_Stream0;`
663			`#endif /_DMA_Stream0 /`
664
665			`#ifdef _DMA_Stream1`
666			`EXT DMA_Stream_TypeDef *DMA_Stream1;`
667			`#endif /_DMA_Stream1 /`
668
669			`#ifdef _DMA_Stream2`
670			`EXT DMA_Stream_TypeDef *DMA_Stream2;`
671			`#endif /_DMA_Stream2 /`
672
673			`#ifdef _DMA_Stream3`
674			`EXT DMA_Stream_TypeDef *DMA_Stream3;`
675			`#endif /_DMA_Stream3 /`
676
677			`#ifdef _RTC`
678			`EXT RTC_TypeDef *RTC;`
679			`#endif /_RTC /`
680
681			`#ifdef _EXTIT`
682			`EXT EXTIT_TypeDef *EXTIT;`
683			`#endif /_EXTIT /`
684
685			`#ifdef _EIC`
686			`EXT EIC_TypeDef *EIC;`
687			`#endif /_EIC /`
688
689			`#endif /* DEBUG */`
690
691			`/* Exported constants --------------------------------------------------------*/`
692			`/* Exported macro ------------------------------------------------------------*/`
693			`/* Exported functions ------------------------------------------------------- */`
694
695			`#endif /* __75x_MAP_H */`
696
697			`/***************** (C) COPYRIGHT 2006 STMicroelectronics *END OF FILE**/`