OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [ARM7_STR75x_GCC/] [STLibrary/] [inc/] [75x_uart.h] - Blame information for rev 590

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 577 jeremybenn
/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
2
* File Name          : 75x_uart.h
3
* Author             : MCD Application Team
4
* Date First Issued  : 03/10/2006
5
* Description        : This file contains all the functions prototypes for the
6
*                      UART software library.
7
********************************************************************************
8
* History:
9
* 07/17/2006 : V1.0
10
* 03/10/2006 : V0.1
11
********************************************************************************
12
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
13
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
14
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
15
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
16
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
17
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
18
*******************************************************************************/
19
 
20
/* Define to prevent recursive inclusion -------------------------------------*/
21
#ifndef __75x_UART_H
22
#define __75x_UART_H
23
 
24
/* Includes ------------------------------------------------------------------*/
25
#include "75x_map.h"
26
 
27
/* Exported types ------------------------------------------------------------*/
28
/* UART FIFO Level enumeration */
29
typedef enum
30
{
31
  UART_FIFOLevel_1_8 = 0x0000,  /* FIFO size 16 bytes, FIFO level 2 bytes */
32
  UART_FIFOLevel_1_4 = 0x0001,  /* FIFO size 16 bytes, FIFO level 4 bytes */
33
  UART_FIFOLevel_1_2 = 0x0002,  /* FIFO size 16 bytes, FIFO level 8 bytes */
34
  UART_FIFOLevel_3_4 = 0x0003,  /* FIFO size 16 bytes, FIFO level 12 bytes */
35
  UART_FIFOLevel_7_8 = 0x0004   /* FIFO size 16 bytes, FIFO level 14 bytes */
36
}UART_FIFOLevel;
37
 
38
/* UART Init Structure definition */
39
typedef struct
40
{
41
  u16 UART_WordLength;
42
  u16 UART_StopBits;
43
  u16 UART_Parity;
44
  u32 UART_BaudRate;
45
  u16 UART_HardwareFlowControl;
46
  u16 UART_Mode;
47
  u16 UART_FIFO;
48
  UART_FIFOLevel UART_TxFIFOLevel;
49
  UART_FIFOLevel UART_RxFIFOLevel;
50
}UART_InitTypeDef;
51
 
52
 
53
/* UART RTS enumeration */
54
typedef enum
55
{
56
  RTSRESET = 1,
57
  RTSSET
58
}UART_RTSTypeDef;
59
 
60
 
61
/* Exported constants --------------------------------------------------------*/
62
/* UART Data Length */
63
#define UART_WordLength_5D          0x0000  /* 5 bits Data */
64
#define UART_WordLength_6D          0x0020  /* 6 bits Data */
65
#define UART_WordLength_7D          0x0040  /* 7 bits Data */
66
#define UART_WordLength_8D          0x0060  /* 8 bits Data */
67
 
68
/* UART Stop Bits */
69
#define UART_StopBits_1             0xFFF7  /* One stop bit is transmitted at 
70
                                               the end of frame */
71
#define UART_StopBits_2             0x0008  /* Tow stop bits are transmitted 
72
                                               at the end of frame */
73
 
74
/* UART Parity */
75
#define UART_Parity_No              0x0000  /* Parity Disable */
76
#define UART_Parity_Even            0x0006  /* Even Parity */
77
#define UART_Parity_Odd             0x0002  /* Odd Parity */
78
#define UART_Parity_OddStick        0x0082  /* 1 is transmitted as bit parity */
79
#define UART_Parity_EvenStick       0x0086  /* 0 is transmitted as bit parity */
80
 
81
/* UART Hardware Flow Control */
82
#define UART_HardwareFlowControl_None       0x0000/* HFC Disable */
83
#define UART_HardwareFlowControl_RTS        0x4000/* RTS Enable */
84
#define UART_HardwareFlowControl_CTS        0x8000/* CTS Enable */
85
#define UART_HardwareFlowControl_RTS_CTS    0xC000/* CTS and RTS Enable */
86
 
87
/* UART Mode */
88
#define UART_Mode_Rx                0x0200  /* UART Rx Enabled */
89
#define UART_Mode_Tx                0x0100  /* UART Tx Enbled */
90
#define UART_Mode_Tx_Rx             0x0300  /* UART Tx and Rx Enabled */
91
 
92
/* UART FIFO */
93
#define UART_FIFO_Disable           0xFFEF  /* FIFOs Disable */
94
#define UART_FIFO_Enable            0x0010  /* FIFOs Enable */
95
 
96
/* UART Interrupt definition */
97
#define UART_IT_OverrunError        0x0400  /* Overrun Error interrupt */
98
#define UART_IT_BreakError          0x0200  /* Break Error interrupt */
99
#define UART_IT_ParityError         0x0100  /* Parity Error interrupt */
100
#define UART_IT_FrameError          0x0080  /* Frame Error interrupt */
101
#define UART_IT_ReceiveTimeOut      0x0040  /* Receive Time Out interrupt */
102
#define UART_IT_Transmit            0x0020  /* Transmit interrupt */
103
#define UART_IT_Receive             0x0010  /* Receive interrupt */
104
#define UART_IT_CTS                 0x0002  /* CTS interrupt */
105
 
106
/* UART0 DMA transfer */
107
#define UART0_DMATransfer_Single    0xFFF7  /* Single DMA transfer */
108
#define UART0_DMATransfer_Burst     0x0008  /* Burst DMA transfer */
109
 
110
/* UART0 DMA On Error */
111
#define UART0_DMAOnError_Enable     0xFFFB  /* DMA receive request enabled
112
                                                when the UART0 error interrupt
113
                                                is asserted. */
114
#define UART0_DMAOnError_Disable    0x0004  /* DMA receive request disabled
115
                                                when the UART0 error interrupt
116
                                                is asserted. */
117
 
118
/* UART0 DMA Request */
119
#define UART0_DMAReq_Tx             0x0002  /* Transmit DMA Enable */
120
#define UART0_DMAReq_Rx             0x0001  /* Receive DMA Enable */
121
 
122
/* UART FLAG */
123
#define UART_FLAG_OverrunError      0x23    /* Overrun error flag */
124
#define UART_FLAG_Break             0x22    /* break error flag */
125
#define UART_FLAG_ParityError       0x21    /* parity error flag */
126
#define UART_FLAG_FrameError        0x20    /* frame error flag */
127
#define UART_FLAG_TxFIFOEmpty       0x47    /* Transmit FIFO Empty flag */
128
#define UART_FLAG_RxFIFOFull        0x46    /* Receive FIFO Full flag */
129
#define UART_FLAG_TxFIFOFull        0x45    /* Transmit FIFO Full flag */
130
#define UART_FLAG_RxFIFOEmpty       0x44    /* Receive FIFO Empty flag */
131
#define UART_FLAG_Busy              0x43    /* UART Busy flag */
132
#define UART_FLAG_CTS               0x40    /* CTS flag */
133
#define UART_RawIT_OverrunError     0x6A    /* Overrun Error Masked IT flag */
134
#define UART_RawIT_BreakError       0x69    /* Break Error Masked IT flag */
135
#define UART_RawIT_ParityError      0x68    /* Parity Error Masked IT flag */
136
#define UART_RawIT_FrameError       0x67    /* Frame Error Masked IT flag */
137
#define UART_RawIT_ReceiveTimeOut   0x66    /* ReceiveTimeOut Masked IT flag */
138
#define UART_RawIT_Transmit         0x65    /* Transmit Masked IT flag */
139
#define UART_RawIT_Receive          0x64    /* Receive Masked IT flag */
140
#define UART_RawIT_CTS              0x61    /* CTS Masked IT flag */
141
 
142
/* UART LIN break length */
143
#define UART_LINBreakLength_10      0x0000  /* 10 low bits */
144
#define UART_LINBreakLength_11      0x0200  /* 11 low bits */
145
#define UART_LINBreakLength_12      0x0400  /* 12 low bits */
146
#define UART_LINBreakLength_13      0x0600  /* 13 low bits */
147
#define UART_LINBreakLength_14      0x0800  /* 14 low bits */
148
#define UART_LINBreakLength_15      0x0A00  /* 15 low bits */
149
#define UART_LINBreakLength_16      0x0C00  /* 16 low bits */
150
#define UART_LINBreakLength_17      0x0E00  /* 17 low bits */
151
#define UART_LINBreakLength_18      0x1000  /* 18 low bits */
152
#define UART_LINBreakLength_19      0x1200  /* 19 low bits */
153
#define UART_LINBreakLength_20      0x1400  /* 20 low bits */
154
/* Exported macro ------------------------------------------------------------*/
155
/* Exported functions ------------------------------------------------------- */
156
 
157
void UART_DeInit(UART_TypeDef* UARTx);
158
void UART_Init(UART_TypeDef* UARTx, UART_InitTypeDef* UART_InitStruct);
159
void UART_StructInit(UART_InitTypeDef* UART_InitStruct);
160
void UART_Cmd(UART_TypeDef* UARTx, FunctionalState NewState);
161
void UART_ITConfig(UART_TypeDef* UARTx, u16 UART_IT, FunctionalState NewState);
162
void UART_DMAConfig(u16 UART0_DMATransfer, u16 UART0_DMAOnError);
163
void UART_DMACmd(u16 UART0_DMAReq, FunctionalState NewState);
164
void UART_LoopBackConfig(UART_TypeDef* UARTx, FunctionalState NewState);
165
void UART_LINConfig(UART_TypeDef* UARTx, u16 UART_LINBreakLength);
166
void UART_LINCmd(UART_TypeDef* UARTx, FunctionalState NewState);
167
void UART_SendData(UART_TypeDef* UARTx, u8 Data);
168
u8 UART_ReceiveData(UART_TypeDef* UARTx);
169
void UART_SendBreak(UART_TypeDef* UARTx);
170
void UART_RTSConfig(UART_TypeDef* UARTx,UART_RTSTypeDef RTSState);
171
FlagStatus UART_GetFlagStatus(UART_TypeDef* UARTx, u16 UART_FLAG);
172
void UART_ClearFlag(UART_TypeDef* UARTx, u16 UART_FLAG);
173
ITStatus UART_GetITStatus(UART_TypeDef* UARTx, u16 UART_IT);
174
void UART_ClearITPendingBit(UART_TypeDef* UARTx, u16 UART_IT);
175
 
176
#endif /* __75x_UART_H */
177
 
178
/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.