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jeremybenn |
/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
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* File Name : 75x_pwm.c
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* Author : MCD Application Team
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* Date First Issued : 03/10/2006
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* Description : This file provides all the PWM software functions.
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********************************************************************************
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* History:
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* 07/17/2006 : V1.0
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* 03/10/2006 : V0.1
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********************************************************************************
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* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
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* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
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* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
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* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
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* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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*******************************************************************************/
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/* Includes ------------------------------------------------------------------*/
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#include "75x_pwm.h"
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#include "75x_mrcc.h"
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/* Private typedef -----------------------------------------------------------*/
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/* Private define ------------------------------------------------------------*/
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/* Private macro -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* PWM interrupt masks */
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#define PWM_IT_Clear_Mask 0x7FFF
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#define PWM_IT_Enable_Mask 0xEFFF
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/* PWM_CR Masks bit */
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#define PWM_CounterMode_Mask 0xFF8F
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#define PWM_DBASE_Mask 0x077F
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#define PWM_MasterModeSelection_Mask 0xFC7F
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/* PWM Update flag selection Set/Reset value */
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#define PWM_UFS_Reset 0xFFFE
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#define PWM_UFS_Set 0x0001
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/* PWM Counter value */
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#define PWM_COUNTER_Reset 0x0002
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#define PWM_COUNTER_Start 0x0004
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#define PWM_COUNTER_Stop 0xFFFB
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/* PWM Debug Mode Set/Reset value */
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#define PWM_DBGC_Set 0x0400
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#define PWM_DBGC_Reset 0xFBFF
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/* PWM Output Compare Polarity Set/Reset value */
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#define PWM_OC1P_Set 0x0020
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#define PWM_OC1P_Reset 0xFFDF
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#define PWM_OC1NP_Set 0x0080
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#define PWM_OC1NP_Reset 0xFF7F
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#define PWM_OC2P_Set 0x2000
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#define PWM_OC2P_Reset 0xDFFF
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#define PWM_OC2NP_Set 0x8000
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#define PWM_OC2NP_Reset 0x7FFF
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#define PWM_OC3P_Set 0x0020
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#define PWM_OC3P_Reset 0xFFDF
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#define PWM_OC3NP_Set 0x0080
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#define PWM_OC3NP_Reset 0xFF7F
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/* PWM Output Compare control mode constant */
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#define PWM_OCControl_PWM 0x000C
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#define PWM_OCControl_OCToggle 0x0006
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#define PWM_OCControl_OCInactive 0x0004
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#define PWM_OCControl_OCActive 0x0002
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#define PWM_OCControl_OCTiming 0x0000
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/* PWM Output Compare mode Enable value */
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#define PWM_OC1_Enable 0x0010
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#define PWM_OC2_Enable 0x1000
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#define PWM_OC3_Enable 0x0010
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#define PWM_OC1_Disable 0xFFEF
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#define PWM_OC2_Disable 0xEFFF
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#define PWM_OC3_Disable 0xFFEF
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#define PWM_OC1N_Enable 0x0040
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#define PWM_OC2N_Enable 0x4000
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#define PWM_OC3N_Enable 0x0040
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#define PWM_OC1N_Disable 0xFFBF
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#define PWM_OC2N_Disable 0xBFFF
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#define PWM_OC3N_Disable 0xFFBF
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/* PWM Output Compare mode Mask value */
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#define PWM_OC1C_Mask 0xFFF1
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#define PWM_OC2C_Mask 0xF1FF
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#define PWM_OC3C_Mask 0xFFF1
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/* PWM Preload bit Set/Reset value */
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#define PWM_PLD1_Set 0x0001
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#define PWM_PLD2_Set 0x0100
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#define PWM_PLD3_Set 0x0001
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/* PWM OCRM Set/Reset value */
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#define PWM_OCMR_Set 0x0080
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#define PWM_OCMR_Reset 0xFF7F
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/* PWM_DTR bit Masks value */
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#define PWM_DTR_Mask 0xFC00
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#define PWM_LOCK_Mask 0xF3FF
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/* PWM MOE Set value */
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#define PWM_MOE_Set 0x8000
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#define PWM_MOE_Reset 0x7FFF
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/* PWM OSSR bit Set/Reset value */
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#define PWM_OSSR_Set 0x4000
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#define PWM_OSSR_Reset 0xBFFF
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/* Reset Register Masks */
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#define PWM_Prescaler_Reset_Mask 0x0000
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#define PWM_Pulse1_Reset_Mask 0x0000
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#define PWM_Pulse2_Reset_Mask 0x0000
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#define PWM_Pulse3_Reset_Mask 0x0000
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#define PWM_Period_Reset_Mask 0xFFFF
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#define PWM_RepetitionCounter_Reset_Mask 0x0000
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#define PWM_DeadTime_Reset_Mask 0x0000
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/* Private function prototypes -----------------------------------------------*/
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static void OCM_ModuleConfig(PWM_InitTypeDef* PWM_InitStruct);
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/* Private functions ---------------------------------------------------------*/
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/******************************************************************************
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* Function Name : PWM_DeInit
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* Description : Deinitializes PWM peripheral registers to their default reset
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* values.
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* Input : None
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* Output : None
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* Return : None
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*******************************************************************************/
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void PWM_DeInit(void)
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{
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/* Enters and exits the PWM peripheral to and from reset */
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MRCC_PeripheralSWResetConfig(MRCC_Peripheral_PWM,ENABLE);
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MRCC_PeripheralSWResetConfig(MRCC_Peripheral_PWM,DISABLE);
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}
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/*******************************************************************************
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* Function Name : PWM_Init
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* Description : Initializes the PWM peripheral according to the specified
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* parameters in the PWM_InitStruct .
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* Input : PWM_InitStruct: pointer to a PWM_InitTypeDef structure that
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* contains the configuration information for the PWM peripheral.
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* Output : None
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* Return : None
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*******************************************************************************/
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void PWM_Init(PWM_InitTypeDef* PWM_InitStruct)
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{
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/* Sets the prescaler value */
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PWM->PSC = PWM_InitStruct->PWM_Prescaler;
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/* Selects the counter mode */
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PWM->CR &= PWM_CounterMode_Mask;
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PWM->CR |= PWM_InitStruct->PWM_CounterMode;
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/* Sets the period value */
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PWM->ARR = PWM_InitStruct->PWM_Period;
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/* Sets the repetition counter */
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PWM->RCR &= PWM_RepetitionCounter_Reset_Mask;
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PWM->RCR |= PWM_InitStruct->PWM_RepetitionCounter;
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/* Configures the PWM according to the PWM_InitTypeDef structure parameters */
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OCM_ModuleConfig(PWM_InitStruct);
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}
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/*******************************************************************************
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* Function Name : PWM_StructInit
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* Description : Fills each PWM_InitStruct member with its default value.
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* Input : PWM_InitStruct : pointer to a PWM_InitTypeDef structure which
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* will be initialized.
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* Output : None
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* Return : None.
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*******************************************************************************/
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void PWM_StructInit(PWM_InitTypeDef *PWM_InitStruct)
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{
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/* Sets the default configuration */
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PWM_InitStruct->PWM_Mode = PWM_Mode_OCTiming;
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PWM_InitStruct->PWM_Prescaler = PWM_Prescaler_Reset_Mask;
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PWM_InitStruct->PWM_CounterMode = PWM_CounterMode_Up;
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PWM_InitStruct->PWM_Period = PWM_Period_Reset_Mask;
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PWM_InitStruct->PWM_Complementary = PWM_Complementary_Disable;
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PWM_InitStruct->PWM_OCState = PWM_OCState_Disable;
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PWM_InitStruct->PWM_OCNState = PWM_OCNState_Disable;
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PWM_InitStruct->PWM_Channel = PWM_Channel_1;
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PWM_InitStruct->PWM_Pulse1 = PWM_Pulse1_Reset_Mask;
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PWM_InitStruct->PWM_Pulse2 = PWM_Pulse2_Reset_Mask;
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PWM_InitStruct->PWM_Pulse3 = PWM_Pulse3_Reset_Mask;
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PWM_InitStruct->PWM_Polarity1 = PWM_Polarity1_High;
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PWM_InitStruct->PWM_Polarity2 = PWM_Polarity2_High;
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PWM_InitStruct->PWM_Polarity3 = PWM_Polarity3_High;
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PWM_InitStruct->PWM_Polarity1N = PWM_Polarity1N_High;
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PWM_InitStruct->PWM_Polarity2N = PWM_Polarity2N_High;
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PWM_InitStruct->PWM_Polarity3N = PWM_Polarity3N_High;
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PWM_InitStruct->PWM_DTRAccess = PWM_DTRAccess_Disable;
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PWM_InitStruct->PWM_DeadTime = PWM_DeadTime_Reset_Mask;
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PWM_InitStruct->PWM_Emergency = PWM_Emergency_Disable;
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PWM_InitStruct->PWM_LOCKLevel = PWM_LOCKLevel_OFF;
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PWM_InitStruct->PWM_OSSIState = PWM_OSSIState_Disable;
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PWM_InitStruct->PWM_RepetitionCounter = PWM_RepetitionCounter_Reset_Mask;
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}
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/*******************************************************************************
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* Function Name : PWM_Cmd
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* Description : Enables or disables the PWM peripheral.
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* Input : Newstate: new state of the PWM peripheral.
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* This parameter can be: ENABLE or DISABLE.
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* Output : None
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* Return : None
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*******************************************************************************/
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void PWM_Cmd(FunctionalState Newstate)
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{
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if(Newstate == ENABLE)
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{
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PWM->CR |= PWM_COUNTER_Start;
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}
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else
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{
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PWM->CR &= PWM_COUNTER_Stop;
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}
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}
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/*******************************************************************************
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* Function Name : PWM_CtrlPWMOutputs
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* Description : Enables or disables PWM peripheral Main Outputs.
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* Input : Newstate: new state of the PWM peripheral Main Outputs.
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* This parameter can be: ENABLE or DISABLE.
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* Output : None
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* Return : None
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*******************************************************************************/
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void PWM_CtrlPWMOutputs(FunctionalState Newstate)
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{
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if(Newstate == ENABLE)
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{
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PWM->DTR |= PWM_MOE_Set;
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}
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else
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{
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PWM->DTR &= PWM_MOE_Reset;
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}
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}
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/*******************************************************************************
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* Function Name : PWM_ITConfig
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* Description : Enables or disables the PWM interrupts.
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* Input : - PWM_IT: specifies the PWM interrupts sources to be enabled
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* or disabled.
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* This parameter can be any combination of the following values:
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* - PWM_IT_OC1: PWM Output Compare 1 Interrupt source
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* - PWM_IT_OC2: PWM Output Compare 2 Interrupt source
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* - PWM_IT_OC3: PWM Output Compare 3 Interrupt source
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* - PWM_IT_Update: PWM update Interrupt source
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* - PWM_IT_Emergency: PWM Emergency interrupt source
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* - PWM_IT_GlobalUpdate: PWM global update Interrupt
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* source
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* - Newstate: new state of PWM interrupts.
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* This parameter can be: ENABLE or DISABLE.
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* Output : None
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* Return : None
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*******************************************************************************/
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void PWM_ITConfig(u16 PWM_IT, FunctionalState Newstate)
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{
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u16 PWM_IT_Enable = 0;
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PWM_IT_Enable = PWM_IT & PWM_IT_Enable_Mask;
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if(Newstate == ENABLE)
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{
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/* Update interrupt global source: overflow/undeflow, counter reset operation
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or slave mode controller in reset mode */
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if ((PWM_IT & PWM_IT_GlobalUpdate) == PWM_IT_GlobalUpdate)
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{
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PWM->CR &= PWM_UFS_Reset;
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}
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/* Update interrupt source: counter overflow/underflow */
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else if ((PWM_IT & PWM_IT_Update) == PWM_IT_Update)
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{
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PWM->CR |= PWM_UFS_Set;
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}
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/* Select and enable the interrupts requests */
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PWM->RSR |= PWM_IT_Enable;
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PWM->RER |= PWM_IT_Enable;
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}
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/* Disable the interrupts requests */
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else
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{
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PWM->RSR &= ~PWM_IT_Enable;
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PWM->RER &= ~PWM_IT_Enable;
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}
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}
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/*******************************************************************************
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* Function Name : PWM_DMAConfig
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* Description : Configures the PWM’s DMA interface.
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* Input : - PWM_DMASources: specifies the DMA Request sources.
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* This parameter can be any combination of the following values:
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* - PWM_DMASource_OC1: PWM Output Compare 1 DMA source
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* - PWM_DMASource_OC2: PWM Output Compare 2 DMA source
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* - PWM_DMASource_OC3: PWM Output Compare 3 DMA source
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* - PWM_DMASource_Update: PWM Update DMA source
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* - PWM_OCRMState: the state of output compare request mode.
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* This parameter can be one of the following values:
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* - PWM_OCRMState_Enable
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* - PWM_OCRMState_Disable
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* - PWM_DMABase:DMA Base address.
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* This parameter can be one of the following values:
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* PWM_DMABase_CR, PWM_DMABase_SCR, PWM_DMABase_OMR1,
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* PWM_DMABase_OMR2, PWM_DMABase_RSR, PWM_DMABase_RER,
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* PWM_DMABase_ISR, PWM_DMABase_CNT, PWM_DMABase_PSC,
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* PWM_DMABase_RCR, PWM_DMABase_ARR, PWM_DMABase_OCR1,
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* PWM_DMABase_OCR2, PWM_DMABase_OCR3 ,PWM_DMABase_DTR.
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* Output : None
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* Return : None
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*******************************************************************************/
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void PWM_DMAConfig(u16 PWM_DMASources, u16 PWM_OCRMState, u16 PWM_DMABase)
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{
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/* Select the DMA requests */
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PWM->RSR &= ~PWM_DMASources;
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328 |
|
|
|
329 |
|
|
/* Sets the OCRM state */
|
330 |
|
|
if(PWM_OCRMState == PWM_OCRMState_Enable)
|
331 |
|
|
{
|
332 |
|
|
PWM->RSR |= PWM_OCMR_Set;
|
333 |
|
|
}
|
334 |
|
|
else
|
335 |
|
|
{
|
336 |
|
|
PWM->RSR &= PWM_OCMR_Reset;
|
337 |
|
|
}
|
338 |
|
|
|
339 |
|
|
/* Sets the DMA Base address */
|
340 |
|
|
PWM->CR &= PWM_DBASE_Mask;
|
341 |
|
|
PWM->CR |= PWM_DMABase;
|
342 |
|
|
}
|
343 |
|
|
|
344 |
|
|
/*******************************************************************************
|
345 |
|
|
* Function Name : PWM_DMACmd
|
346 |
|
|
* Description : Enables or disables the PWM’s DMA interface.
|
347 |
|
|
* Input : - PWM_DMASources: specifies the DMA Request sources.
|
348 |
|
|
* This parameter can be any combination of the following values:
|
349 |
|
|
* - PWM_DMASource_OC1: PWM Output Compare 1 DMA source
|
350 |
|
|
* - PWM_DMASource_OC2: PWM Output Compare 2 DMA source
|
351 |
|
|
* - PWM_DMASource_OC3: PWM Output Compare 3 DMA source
|
352 |
|
|
* - PWM_DMASource_Update: PWM Update DMA source
|
353 |
|
|
* - Newstate: new state of the DMA Request sources.
|
354 |
|
|
* This parameter can be: ENABLE or DISABLE.
|
355 |
|
|
* Output : None
|
356 |
|
|
* Return : None
|
357 |
|
|
*******************************************************************************/
|
358 |
|
|
void PWM_DMACmd(u16 PWM_DMASources, FunctionalState Newstate)
|
359 |
|
|
{
|
360 |
|
|
if(Newstate == ENABLE)
|
361 |
|
|
{
|
362 |
|
|
PWM->RER |= PWM_DMASources;
|
363 |
|
|
}
|
364 |
|
|
else
|
365 |
|
|
{
|
366 |
|
|
PWM->RER &= ~PWM_DMASources;
|
367 |
|
|
}
|
368 |
|
|
}
|
369 |
|
|
|
370 |
|
|
/*******************************************************************************
|
371 |
|
|
* Function Name : PWM_SetPrescaler
|
372 |
|
|
* Description : Sets the PWM prescaler value.
|
373 |
|
|
* Input : Prescaler: PWM prescaler new value.
|
374 |
|
|
* Output : None
|
375 |
|
|
* Return : None
|
376 |
|
|
*******************************************************************************/
|
377 |
|
|
void PWM_SetPrescaler(u16 Prescaler)
|
378 |
|
|
{
|
379 |
|
|
PWM->PSC = Prescaler;
|
380 |
|
|
}
|
381 |
|
|
|
382 |
|
|
/*******************************************************************************
|
383 |
|
|
* Function Name : PWM_SetPeriod
|
384 |
|
|
* Description : Sets the PWM period value.
|
385 |
|
|
* Input : Period: PWM period new value.
|
386 |
|
|
* Output : None
|
387 |
|
|
* Return : None
|
388 |
|
|
*******************************************************************************/
|
389 |
|
|
void PWM_SetPeriod(u16 Period)
|
390 |
|
|
{
|
391 |
|
|
PWM->ARR = Period;
|
392 |
|
|
}
|
393 |
|
|
|
394 |
|
|
/*******************************************************************************
|
395 |
|
|
* Function Name : PWM_SetPulse
|
396 |
|
|
* Description : Sets the PWM pulse value.
|
397 |
|
|
* Input : - PWM_Channel: specifies the PWM channel to be used.
|
398 |
|
|
* This parameter can be one of the following values:
|
399 |
|
|
* - PWM_Channel_1: PWM Channel 1 is used
|
400 |
|
|
* - PWM_Channel_2: PWM Channel 2 is used
|
401 |
|
|
* - PWM_Channel_3: PWM Channel 3 is used
|
402 |
|
|
* - PWM_Channel_ALL: PWM Channel 1, Channel 2 and 3 are used
|
403 |
|
|
* - Pulse: PWM pulse new value.
|
404 |
|
|
* Output : None
|
405 |
|
|
* Return : None
|
406 |
|
|
*******************************************************************************/
|
407 |
|
|
void PWM_SetPulse(u16 PWM_Channel, u16 Pulse)
|
408 |
|
|
{
|
409 |
|
|
/* Sets Channel 1 pulse value */
|
410 |
|
|
if(PWM_Channel == PWM_Channel_1)
|
411 |
|
|
{
|
412 |
|
|
PWM->OCR1 = Pulse;
|
413 |
|
|
}
|
414 |
|
|
/* Sets Channel 2 pulse value */
|
415 |
|
|
else if(PWM_Channel == PWM_Channel_2)
|
416 |
|
|
{
|
417 |
|
|
PWM->OCR2 = Pulse;
|
418 |
|
|
}
|
419 |
|
|
/* Sets Channel 3 pulse value */
|
420 |
|
|
else if(PWM_Channel == PWM_Channel_3)
|
421 |
|
|
{
|
422 |
|
|
PWM->OCR3 = Pulse;
|
423 |
|
|
}
|
424 |
|
|
/* Sets Channel 1, Channel 2 and Channel 3 pulse values */
|
425 |
|
|
else if(PWM_Channel == PWM_Channel_ALL)
|
426 |
|
|
{
|
427 |
|
|
PWM->OCR1 = Pulse;
|
428 |
|
|
PWM->OCR2 = Pulse;
|
429 |
|
|
PWM->OCR3 = Pulse;
|
430 |
|
|
}
|
431 |
|
|
}
|
432 |
|
|
|
433 |
|
|
/*******************************************************************************
|
434 |
|
|
* Function Name : PWM_SetPulse1
|
435 |
|
|
* Description : Sets the PWM Channel 1 pulse value.
|
436 |
|
|
* Input : - Pulse: PWM Channel 1 pulse new value.
|
437 |
|
|
* Output : None
|
438 |
|
|
* Return : None
|
439 |
|
|
*******************************************************************************/
|
440 |
|
|
void PWM_SetPulse1(u16 Pulse)
|
441 |
|
|
{
|
442 |
|
|
PWM->OCR1 = Pulse;
|
443 |
|
|
}
|
444 |
|
|
|
445 |
|
|
/*******************************************************************************
|
446 |
|
|
* Function Name : PWM_SetPulse2
|
447 |
|
|
* Description : Sets the PWM Channel 2 pulse value.
|
448 |
|
|
* Input : - Pulse: PWM Channel 2 pulse new value.
|
449 |
|
|
* Output : None
|
450 |
|
|
* Return : None
|
451 |
|
|
*******************************************************************************/
|
452 |
|
|
void PWM_SetPulse2(u16 Pulse)
|
453 |
|
|
{
|
454 |
|
|
PWM->OCR2 = Pulse;
|
455 |
|
|
}
|
456 |
|
|
|
457 |
|
|
/*******************************************************************************
|
458 |
|
|
* Function Name : PWM_SetPulse3
|
459 |
|
|
* Description : Sets the PWM Channel 3 pulse value.
|
460 |
|
|
* Input : - Pulse: PWM Channel 3 pulse new value.
|
461 |
|
|
* Output : None
|
462 |
|
|
* Return : None
|
463 |
|
|
*******************************************************************************/
|
464 |
|
|
void PWM_SetPulse3(u16 Pulse)
|
465 |
|
|
{
|
466 |
|
|
PWM->OCR3 = Pulse;
|
467 |
|
|
}
|
468 |
|
|
|
469 |
|
|
/*******************************************************************************
|
470 |
|
|
* Function Name : PWM_DebugCmd
|
471 |
|
|
* Description : Enables or disables PWM peripheral Debug control.
|
472 |
|
|
* Input : Newstate: new state of the PWM Debug control.
|
473 |
|
|
* This parameter can be: ENABLE or DISABLE.
|
474 |
|
|
* Output : None
|
475 |
|
|
* Return : None
|
476 |
|
|
*******************************************************************************/
|
477 |
|
|
void PWM_DebugCmd(FunctionalState Newstate)
|
478 |
|
|
{
|
479 |
|
|
if(Newstate == ENABLE)
|
480 |
|
|
{
|
481 |
|
|
PWM->CR |= PWM_DBGC_Set;
|
482 |
|
|
}
|
483 |
|
|
else
|
484 |
|
|
{
|
485 |
|
|
PWM->CR &= PWM_DBGC_Reset;
|
486 |
|
|
}
|
487 |
|
|
}
|
488 |
|
|
|
489 |
|
|
/*******************************************************************************
|
490 |
|
|
* Function Name : PWM_CounterModeConfig
|
491 |
|
|
* Description : Specifies the Counter Mode to be used.
|
492 |
|
|
* Input : PWM_CounterMode: specifies the Counter Mode to be used
|
493 |
|
|
* This parameter can be one of the following values:
|
494 |
|
|
* - PWM_CounterMode_Up: PWM Up Counting Mode
|
495 |
|
|
* - PWM_CounterMode_Down: PWM Down Counting Mode
|
496 |
|
|
* - PWM_CounterMode_CenterAligned1: PWM Center Aligned1 Mode
|
497 |
|
|
* - PWM_CounterMode_CenterAligned2: PWM Center Aligned2 Mode
|
498 |
|
|
* - PWM_CounterMode_CenterAligned3: PWM Center Aligned3 Mode
|
499 |
|
|
* Output : None
|
500 |
|
|
* Return : None
|
501 |
|
|
*******************************************************************************/
|
502 |
|
|
void PWM_CounterModeConfig(u16 PWM_CounterMode)
|
503 |
|
|
{
|
504 |
|
|
/* Counter mode configuration */
|
505 |
|
|
PWM->CR &= PWM_CounterMode_Mask;
|
506 |
|
|
PWM->CR |= PWM_CounterMode;
|
507 |
|
|
}
|
508 |
|
|
|
509 |
|
|
/*******************************************************************************
|
510 |
|
|
* Function Name : PWM_ForcedOCConfig
|
511 |
|
|
* Description : Forces the PWM output waveform to active or inactive level.
|
512 |
|
|
* Input : - PWM_Channel: specifies the PWM channel to be used.
|
513 |
|
|
* This parameter can be one of the following values:
|
514 |
|
|
* - PWM_Channel_1: PWM Channel 1 is used
|
515 |
|
|
* - PWM_Channel_2: PWM Channel 2 is used
|
516 |
|
|
* - PWM_Channel_3: PWM Channel 3 is used
|
517 |
|
|
* - PWM_Channel_ALL: PWM Channel 1, Channel 2 and 3 are used
|
518 |
|
|
* - PWM_ForcedAction: specifies the forced Action to be set to the
|
519 |
|
|
* output waveform.
|
520 |
|
|
* This parameter can be one of the following values:
|
521 |
|
|
* - PWM_ForcedAction_Active: Force active level on OCxREF
|
522 |
|
|
* - PWM_ForcedAction_InActive: Force inactive level on
|
523 |
|
|
* OCxREF
|
524 |
|
|
* Output : None
|
525 |
|
|
* Return : None
|
526 |
|
|
*******************************************************************************/
|
527 |
|
|
void PWM_ForcedOCConfig(u16 PWM_Channel, u16 PWM_ForcedAction)
|
528 |
|
|
{
|
529 |
|
|
/* Channel 1 Forced Output Compare mode configuration */
|
530 |
|
|
if(PWM_Channel == PWM_Channel_1)
|
531 |
|
|
{
|
532 |
|
|
PWM->OMR1 &= PWM_OC1C_Mask;
|
533 |
|
|
PWM->OMR1 |= PWM_ForcedAction;
|
534 |
|
|
}
|
535 |
|
|
/* Channel 2 Forced Output Compare mode configuration */
|
536 |
|
|
else
|
537 |
|
|
{
|
538 |
|
|
if(PWM_Channel == PWM_Channel_2)
|
539 |
|
|
{
|
540 |
|
|
PWM->OMR1 &= PWM_OC2C_Mask;
|
541 |
|
|
PWM->OMR1 |= (PWM_ForcedAction<<8);
|
542 |
|
|
}
|
543 |
|
|
else
|
544 |
|
|
{
|
545 |
|
|
/* Channel 3 Forced Output Compare mode configuration */
|
546 |
|
|
if(PWM_Channel == PWM_Channel_3)
|
547 |
|
|
{
|
548 |
|
|
PWM->OMR2 &= PWM_OC3C_Mask;
|
549 |
|
|
PWM->OMR2 |= PWM_ForcedAction;
|
550 |
|
|
}
|
551 |
|
|
/* Channel 1, Channel 2 and Channel 3 Forced Output Compare mode
|
552 |
|
|
configuration */
|
553 |
|
|
else
|
554 |
|
|
{
|
555 |
|
|
PWM->OMR1 &= PWM_OC1C_Mask;
|
556 |
|
|
PWM->OMR1 |= PWM_ForcedAction;
|
557 |
|
|
|
558 |
|
|
PWM->OMR1 &= PWM_OC2C_Mask;
|
559 |
|
|
PWM->OMR1 |= (PWM_ForcedAction<<8);
|
560 |
|
|
|
561 |
|
|
PWM->OMR2 &= PWM_OC3C_Mask;
|
562 |
|
|
PWM->OMR2 |= PWM_ForcedAction;
|
563 |
|
|
}
|
564 |
|
|
}
|
565 |
|
|
}
|
566 |
|
|
}
|
567 |
|
|
|
568 |
|
|
/*******************************************************************************
|
569 |
|
|
* Function Name : PWM_SetDeadTime
|
570 |
|
|
* Description : Inserts dead time between the OCx and OCNx.
|
571 |
|
|
* Input : DeadTime: PWM Dead Time value.
|
572 |
|
|
* Output : None
|
573 |
|
|
* Return : None
|
574 |
|
|
*******************************************************************************/
|
575 |
|
|
void PWM_SetDeadTime(u16 DeadTime)
|
576 |
|
|
{
|
577 |
|
|
/* Sets the dead time value */
|
578 |
|
|
PWM->DTR &= PWM_DTR_Mask;
|
579 |
|
|
PWM->DTR |= DeadTime;
|
580 |
|
|
}
|
581 |
|
|
|
582 |
|
|
/*******************************************************************************
|
583 |
|
|
* Function Name : PWM_ResetCounter
|
584 |
|
|
* Description : Re-intializes the PWM counter and generates an update of the
|
585 |
|
|
* registers.
|
586 |
|
|
* Input : None
|
587 |
|
|
* Output : None
|
588 |
|
|
* Return : None
|
589 |
|
|
*******************************************************************************/
|
590 |
|
|
void PWM_ResetCounter(void)
|
591 |
|
|
{
|
592 |
|
|
/* Resets the PWM counter */
|
593 |
|
|
PWM->CR |= PWM_COUNTER_Reset;
|
594 |
|
|
}
|
595 |
|
|
|
596 |
|
|
/*******************************************************************************
|
597 |
|
|
* Function Name : PWM_TRGOSelection
|
598 |
|
|
* Description : Sets the PWM Master Mode selection bits.
|
599 |
|
|
* Input : PWM_TRGOMode: specifies the TRGO source.
|
600 |
|
|
* This parameter can be one of the following values:
|
601 |
|
|
* - PWM_TRGOMode_Enable: The CNT_EN bit is used as TRGO
|
602 |
|
|
* - PWM_TRGOMode_Update: The Update event is used as TRGO
|
603 |
|
|
* - PWM_TRGOMode_Reset: The CNT_RST bit is used as TRGO
|
604 |
|
|
* - PWM_TRGOMode_OC: The OC1 signal is used as TRGO
|
605 |
|
|
* Output : None
|
606 |
|
|
* Return : None
|
607 |
|
|
*******************************************************************************/
|
608 |
|
|
void PWM_TRGOSelection(u16 PWM_TRGOMode)
|
609 |
|
|
{
|
610 |
|
|
/* Sets the synchronization action */
|
611 |
|
|
PWM->CR &= PWM_MasterModeSelection_Mask;
|
612 |
|
|
PWM->CR |= PWM_TRGOMode;
|
613 |
|
|
}
|
614 |
|
|
|
615 |
|
|
/*******************************************************************************
|
616 |
|
|
* Function Name : PWM_GetFlagStatus
|
617 |
|
|
* Description : Checks whether the specified PWM flag is set or not.
|
618 |
|
|
* Input : PWM_FLAG: specifies the flag to check.
|
619 |
|
|
* This parameter can be one of the following values:
|
620 |
|
|
* - PWM_FLAG_OC1: Output Compare 1 Flag
|
621 |
|
|
* - PWM_FLAG_OC2: Output Compare 2 Flag
|
622 |
|
|
* - PWM_FLAG_OC3: Output Compare 3 Flag
|
623 |
|
|
* - PWM_FLAG_Update: PWM update Flag
|
624 |
|
|
* - PWM_FLAG_Emergency: PWM Emergency Flag
|
625 |
|
|
* Output : None
|
626 |
|
|
* Return : The new state of the PWM_FLAG(SET or RESET).
|
627 |
|
|
*******************************************************************************/
|
628 |
|
|
FlagStatus PWM_GetFlagStatus(u16 PWM_FLAG)
|
629 |
|
|
{
|
630 |
|
|
if((PWM->ISR & PWM_FLAG) != RESET )
|
631 |
|
|
{
|
632 |
|
|
return SET;
|
633 |
|
|
}
|
634 |
|
|
else
|
635 |
|
|
{
|
636 |
|
|
return RESET;
|
637 |
|
|
}
|
638 |
|
|
}
|
639 |
|
|
|
640 |
|
|
/*******************************************************************************
|
641 |
|
|
* Function Name : PWM_ClearFlag
|
642 |
|
|
* Description : Clears the PWM’s pending flags.
|
643 |
|
|
* Input : PWM_FLAG: specifies the flag to clear.
|
644 |
|
|
* This parameter can be any combination of the following values:
|
645 |
|
|
* - PWM_FLAG_OC1: Output Compare 1 flag
|
646 |
|
|
* - PWM_FLAG_OC2: Output Compare 2 flag
|
647 |
|
|
* - PWM_FLAG_OC3: Output Compare 3 flag
|
648 |
|
|
* - PWM_FLAG_Update: PWM update flag
|
649 |
|
|
* - PWM_FLAG_Emergency: PWM Emergency flag
|
650 |
|
|
* Output : None
|
651 |
|
|
* Return : None
|
652 |
|
|
*******************************************************************************/
|
653 |
|
|
void PWM_ClearFlag(u16 PWM_FLAG)
|
654 |
|
|
{
|
655 |
|
|
/* Clears the flags */
|
656 |
|
|
PWM->ISR &= ~PWM_FLAG;
|
657 |
|
|
}
|
658 |
|
|
|
659 |
|
|
/*******************************************************************************
|
660 |
|
|
* Function Name : PWM_GetITStatus
|
661 |
|
|
* Description : Checks whether the PWM interrupt has occurred or not.
|
662 |
|
|
* Input : PWM_IT: specifies the PWM interrupt source to check.
|
663 |
|
|
* This parameter can be one of the following values:
|
664 |
|
|
* - PWM_IT_OC1: PWM Output Compare 1 Interrupt source
|
665 |
|
|
* - PWM_IT_OC2: PWM Output Compare 2 Interrupt source
|
666 |
|
|
* - PWM_IT_OC3: PWM Output Compare 3 Interrupt source
|
667 |
|
|
* - PWM_IT_Update: PWM update Interrupt source
|
668 |
|
|
* - PWM_IT_Emergency: PWM Emergency interrupt source
|
669 |
|
|
* - PWM_IT_GlobalUpdate: PWM global update Interrupt
|
670 |
|
|
* source
|
671 |
|
|
* Output : None
|
672 |
|
|
* Return : The new state of the PWM_IT(SET or RESET).
|
673 |
|
|
*******************************************************************************/
|
674 |
|
|
ITStatus PWM_GetITStatus(u16 PWM_IT)
|
675 |
|
|
{
|
676 |
|
|
u16 PWM_IT_Check = 0;
|
677 |
|
|
|
678 |
|
|
/* Calculates the pending bits to be checked */
|
679 |
|
|
PWM_IT_Check = PWM_IT & PWM_IT_Clear_Mask;
|
680 |
|
|
|
681 |
|
|
if((PWM->ISR & PWM_IT_Check) != RESET )
|
682 |
|
|
{
|
683 |
|
|
return SET;
|
684 |
|
|
}
|
685 |
|
|
else
|
686 |
|
|
{
|
687 |
|
|
return RESET;
|
688 |
|
|
}
|
689 |
|
|
}
|
690 |
|
|
|
691 |
|
|
/*******************************************************************************
|
692 |
|
|
* Function Name : PWM_ClearITPendingBit
|
693 |
|
|
* Description : Clears the PWM's interrupt pending bits.
|
694 |
|
|
* Input : PWM_IT: specifies the pending bit to clear.
|
695 |
|
|
* This parameter can be any combination of the following values:
|
696 |
|
|
* - PWM_IT_OC1: PWM Output Compare 1 Interrupt source
|
697 |
|
|
* - PWM_IT_OC2: PWM Output Compare 2 Interrupt source
|
698 |
|
|
* - PWM_IT_OC3: PWM Output Compare 3 Interrupt source
|
699 |
|
|
* - PWM_IT_Update: PWM update Interrupt source
|
700 |
|
|
* - PWM_IT_Emergency: PWM Emergency interrupt source
|
701 |
|
|
* - PWM_IT_GlobalUpdate: PWM global update Interrupt
|
702 |
|
|
* source
|
703 |
|
|
* Output : None
|
704 |
|
|
* Return : None
|
705 |
|
|
*******************************************************************************/
|
706 |
|
|
void PWM_ClearITPendingBit(u16 PWM_IT)
|
707 |
|
|
{
|
708 |
|
|
u16 PWM_IT_Clear = 0;
|
709 |
|
|
|
710 |
|
|
/* Calculates the pending bits to be cleared */
|
711 |
|
|
PWM_IT_Clear = PWM_IT & PWM_IT_Clear_Mask;
|
712 |
|
|
|
713 |
|
|
/* Clears the pending bits */
|
714 |
|
|
PWM->ISR &= ~PWM_IT_Clear;
|
715 |
|
|
|
716 |
|
|
}
|
717 |
|
|
|
718 |
|
|
/*******************************************************************************
|
719 |
|
|
* Function Name : OCM_ModuleConfig
|
720 |
|
|
* Description : Output Compare Module configuration.
|
721 |
|
|
* Input : PWM_InitStruct: pointer to a PWM_InitTypeDef structure that
|
722 |
|
|
* contains the configuration information for the PWM peripheral.
|
723 |
|
|
* Output : None
|
724 |
|
|
* Return : None
|
725 |
|
|
*******************************************************************************/
|
726 |
|
|
static void OCM_ModuleConfig(PWM_InitTypeDef* PWM_InitStruct)
|
727 |
|
|
{
|
728 |
|
|
u16 PWM_OCControl = 0x0000;
|
729 |
|
|
u16 DTR_REG = 0x0000;
|
730 |
|
|
|
731 |
|
|
if(PWM_InitStruct->PWM_Mode == PWM_Mode_OCTiming)
|
732 |
|
|
{
|
733 |
|
|
PWM_OCControl = PWM_OCControl_OCTiming;
|
734 |
|
|
}
|
735 |
|
|
else
|
736 |
|
|
{
|
737 |
|
|
if(PWM_InitStruct->PWM_Mode == PWM_Mode_OCActive)
|
738 |
|
|
{
|
739 |
|
|
PWM_OCControl = PWM_OCControl_OCActive;
|
740 |
|
|
}
|
741 |
|
|
else
|
742 |
|
|
{
|
743 |
|
|
if(PWM_InitStruct->PWM_Mode == PWM_Mode_OCInactive)
|
744 |
|
|
{
|
745 |
|
|
PWM_OCControl = PWM_OCControl_OCInactive;
|
746 |
|
|
}
|
747 |
|
|
else
|
748 |
|
|
{
|
749 |
|
|
if(PWM_InitStruct->PWM_Mode == PWM_Mode_OCToggle)
|
750 |
|
|
{
|
751 |
|
|
PWM_OCControl = PWM_OCControl_OCToggle;
|
752 |
|
|
}
|
753 |
|
|
else
|
754 |
|
|
{
|
755 |
|
|
PWM_OCControl = PWM_OCControl_PWM;
|
756 |
|
|
|
757 |
|
|
}
|
758 |
|
|
}
|
759 |
|
|
}
|
760 |
|
|
}
|
761 |
|
|
|
762 |
|
|
/* Read DTR register */
|
763 |
|
|
DTR_REG = PWM->DTR & 0x8000;
|
764 |
|
|
|
765 |
|
|
/*Channel 1 Configuration-----------------------------------------------------*/
|
766 |
|
|
if(PWM_InitStruct->PWM_Channel == PWM_Channel_1)
|
767 |
|
|
{
|
768 |
|
|
/* PWM Output Complementary Configuration */
|
769 |
|
|
if(PWM_InitStruct->PWM_Complementary == PWM_Complementary_Enable)
|
770 |
|
|
{
|
771 |
|
|
/* Configures Channel 1 on Output Compare mode */
|
772 |
|
|
PWM->OMR1 &= PWM_OC1C_Mask;
|
773 |
|
|
PWM->OMR1 |= PWM_OCControl|PWM_OC1_Enable|PWM_OC1N_Enable|PWM_PLD1_Set;
|
774 |
|
|
PWM->OCR1 = PWM_InitStruct->PWM_Pulse1;
|
775 |
|
|
|
776 |
|
|
/* Sets the OC1 wave polarity */
|
777 |
|
|
if(PWM_InitStruct->PWM_Polarity1 == PWM_Polarity1_Low)
|
778 |
|
|
{
|
779 |
|
|
PWM->OMR1 |= PWM_OC1P_Set;
|
780 |
|
|
}
|
781 |
|
|
else
|
782 |
|
|
{
|
783 |
|
|
PWM->OMR1 &= PWM_OC1P_Reset;
|
784 |
|
|
}
|
785 |
|
|
|
786 |
|
|
/* Sets the OC1N wave polarity */
|
787 |
|
|
if(PWM_InitStruct->PWM_Polarity1N == PWM_Polarity1N_Low)
|
788 |
|
|
{
|
789 |
|
|
PWM->OMR1 |= PWM_OC1NP_Set;
|
790 |
|
|
}
|
791 |
|
|
else
|
792 |
|
|
{
|
793 |
|
|
PWM->OMR1 &= PWM_OC1NP_Reset;
|
794 |
|
|
}
|
795 |
|
|
}/* End complementary case */
|
796 |
|
|
/* Single PWM Output configuratuion */
|
797 |
|
|
else
|
798 |
|
|
{
|
799 |
|
|
switch(PWM_InitStruct->PWM_OCState)
|
800 |
|
|
{
|
801 |
|
|
case PWM_OCState_Enable:
|
802 |
|
|
{
|
803 |
|
|
/* Configures Channel 1 on Output Compare mode */
|
804 |
|
|
PWM->OMR1 &= PWM_OC1C_Mask;
|
805 |
|
|
PWM->OMR1 |= PWM_OCControl|PWM_OC1_Enable;
|
806 |
|
|
PWM->OMR1 |= PWM_PLD1_Set;
|
807 |
|
|
PWM->OCR1 = PWM_InitStruct->PWM_Pulse1;
|
808 |
|
|
|
809 |
|
|
/* Sets the OC1 wave polarity */
|
810 |
|
|
if(PWM_InitStruct->PWM_Polarity1 == PWM_Polarity1_Low)
|
811 |
|
|
{
|
812 |
|
|
PWM->OMR1 |= PWM_OC1P_Set;
|
813 |
|
|
}
|
814 |
|
|
else
|
815 |
|
|
{
|
816 |
|
|
PWM->OMR1 &= PWM_OC1P_Reset;
|
817 |
|
|
}
|
818 |
|
|
}
|
819 |
|
|
break;
|
820 |
|
|
case PWM_OCState_Disable:
|
821 |
|
|
{
|
822 |
|
|
/* OC1E = 0 and OSSR = 0 sets the polarity */
|
823 |
|
|
PWM->OMR1 &= PWM_OC1_Disable;
|
824 |
|
|
DTR_REG &= PWM_OSSR_Reset;
|
825 |
|
|
}
|
826 |
|
|
break;
|
827 |
|
|
case PWM_OCState_OffState:
|
828 |
|
|
{
|
829 |
|
|
/* OC1E = 0 and OSSR = 1 and sets the polarity */
|
830 |
|
|
PWM->OMR1 &= PWM_OC1_Disable;
|
831 |
|
|
DTR_REG |= PWM_OSSR_Set;
|
832 |
|
|
|
833 |
|
|
/* Sets the OC1 wave polarity */
|
834 |
|
|
if(PWM_InitStruct->PWM_Polarity1 == PWM_Polarity1_Low)
|
835 |
|
|
{
|
836 |
|
|
PWM->OMR1 |= PWM_OC1P_Set;
|
837 |
|
|
}
|
838 |
|
|
else
|
839 |
|
|
{
|
840 |
|
|
PWM->OMR1 &= PWM_OC1P_Reset;
|
841 |
|
|
}
|
842 |
|
|
}
|
843 |
|
|
break;
|
844 |
|
|
}
|
845 |
|
|
|
846 |
|
|
switch(PWM_InitStruct->PWM_OCNState)
|
847 |
|
|
{
|
848 |
|
|
case PWM_OCNState_Enable:
|
849 |
|
|
{
|
850 |
|
|
/* Configures Channel 1N on Output Compare mode */
|
851 |
|
|
PWM->OMR1 &= PWM_OC1C_Mask;
|
852 |
|
|
PWM->OMR1 |= PWM_OCControl |PWM_OC1N_Enable |PWM_PLD1_Set;
|
853 |
|
|
PWM->OCR1 = PWM_InitStruct->PWM_Pulse1;
|
854 |
|
|
|
855 |
|
|
/* Sets the OC1N wave polarity */
|
856 |
|
|
if(PWM_InitStruct->PWM_Polarity1N == PWM_Polarity1N_Low)
|
857 |
|
|
{
|
858 |
|
|
PWM->OMR1 |= PWM_OC1NP_Set;
|
859 |
|
|
}
|
860 |
|
|
else
|
861 |
|
|
{
|
862 |
|
|
PWM->OMR1 &= PWM_OC1NP_Reset;
|
863 |
|
|
}
|
864 |
|
|
}
|
865 |
|
|
break;
|
866 |
|
|
case PWM_OCNState_Disable:
|
867 |
|
|
{
|
868 |
|
|
/* OC1N = 0 OSSR = 0 */
|
869 |
|
|
PWM->OMR1 &= PWM_OC1N_Disable;
|
870 |
|
|
DTR_REG &= PWM_OSSR_Reset;
|
871 |
|
|
}
|
872 |
|
|
break;
|
873 |
|
|
case PWM_OCNState_OffState:
|
874 |
|
|
{
|
875 |
|
|
/* OC1N = 0 OSSR = 1 and sets the polarity */
|
876 |
|
|
PWM->OMR1 &= PWM_OC1N_Disable;
|
877 |
|
|
DTR_REG |= PWM_OSSR_Set;
|
878 |
|
|
|
879 |
|
|
if(PWM_InitStruct->PWM_Polarity1N == PWM_Polarity1N_Low)
|
880 |
|
|
{
|
881 |
|
|
PWM->OMR1 |= PWM_OC1NP_Set;
|
882 |
|
|
}
|
883 |
|
|
else
|
884 |
|
|
{
|
885 |
|
|
PWM->OMR1 &= PWM_OC1NP_Reset;
|
886 |
|
|
}
|
887 |
|
|
}
|
888 |
|
|
break;
|
889 |
|
|
}
|
890 |
|
|
} /* End not complementary case */
|
891 |
|
|
}/* end channel 1 */
|
892 |
|
|
|
893 |
|
|
/*Channel 2 Configuration-----------------------------------------------------*/
|
894 |
|
|
if(PWM_InitStruct->PWM_Channel == PWM_Channel_2)
|
895 |
|
|
{
|
896 |
|
|
/* PWM Output Complementary Configuration */
|
897 |
|
|
if(PWM_InitStruct->PWM_Complementary == PWM_Complementary_Enable)
|
898 |
|
|
{
|
899 |
|
|
/* Configures Channel 2 on Output Compare mode */
|
900 |
|
|
PWM->OMR1 &= PWM_OC2C_Mask;
|
901 |
|
|
PWM->OMR1 |= (PWM_OCControl<<8)|PWM_OC2_Enable|PWM_OC2N_Enable|PWM_PLD2_Set;
|
902 |
|
|
PWM->OCR2 = PWM_InitStruct->PWM_Pulse2;
|
903 |
|
|
|
904 |
|
|
/* Set the OC2 wave polarity */
|
905 |
|
|
if(PWM_InitStruct->PWM_Polarity2 == PWM_Polarity2_Low)
|
906 |
|
|
{
|
907 |
|
|
PWM->OMR1 |= PWM_OC2P_Set;
|
908 |
|
|
}
|
909 |
|
|
else
|
910 |
|
|
{
|
911 |
|
|
PWM->OMR1 &= PWM_OC2P_Reset;
|
912 |
|
|
}
|
913 |
|
|
|
914 |
|
|
/* Sets the OC2N wave polarity */
|
915 |
|
|
if(PWM_InitStruct->PWM_Polarity2N == PWM_Polarity2N_Low)
|
916 |
|
|
{
|
917 |
|
|
PWM->OMR1 |= PWM_OC2NP_Set;
|
918 |
|
|
}
|
919 |
|
|
else
|
920 |
|
|
{
|
921 |
|
|
PWM->OMR1 &= PWM_OC2NP_Reset;
|
922 |
|
|
}
|
923 |
|
|
|
924 |
|
|
}/* End complentary case */
|
925 |
|
|
else
|
926 |
|
|
/* Single PWM Output configuratuion */
|
927 |
|
|
{
|
928 |
|
|
switch(PWM_InitStruct->PWM_OCState)
|
929 |
|
|
{
|
930 |
|
|
case PWM_OCState_Enable:
|
931 |
|
|
{
|
932 |
|
|
/* Configures Channel 2 on Output Compare mode */
|
933 |
|
|
PWM->OMR1 &= PWM_OC2C_Mask;
|
934 |
|
|
PWM->OMR1 |= (PWM_OCControl<<8)|PWM_OC2_Enable|PWM_PLD2_Set;
|
935 |
|
|
PWM->OCR2 = PWM_InitStruct->PWM_Pulse2;
|
936 |
|
|
|
937 |
|
|
/* Sets the OC2 wave polarity */
|
938 |
|
|
if(PWM_InitStruct->PWM_Polarity2 == PWM_Polarity2_Low)
|
939 |
|
|
{
|
940 |
|
|
PWM->OMR1 |= PWM_OC2P_Set;
|
941 |
|
|
}
|
942 |
|
|
else
|
943 |
|
|
{
|
944 |
|
|
PWM->OMR1 &= PWM_OC2P_Reset;
|
945 |
|
|
}
|
946 |
|
|
}
|
947 |
|
|
break;
|
948 |
|
|
case PWM_OCState_Disable:
|
949 |
|
|
{
|
950 |
|
|
/* OC2E = 0 and OSSR = 0 */
|
951 |
|
|
PWM->OMR1 &= PWM_OC2_Disable;
|
952 |
|
|
DTR_REG &= PWM_OSSR_Reset;
|
953 |
|
|
}
|
954 |
|
|
break;
|
955 |
|
|
case PWM_OCState_OffState:
|
956 |
|
|
{
|
957 |
|
|
/* OC2E = 0 and OSSR = 1 sets the polarity */
|
958 |
|
|
PWM->OMR1 &= PWM_OC2_Disable;
|
959 |
|
|
DTR_REG |= PWM_OSSR_Set;
|
960 |
|
|
|
961 |
|
|
/* Sets the OC2 wave polarity */
|
962 |
|
|
if(PWM_InitStruct->PWM_Polarity2 == PWM_Polarity2_Low)
|
963 |
|
|
{
|
964 |
|
|
PWM->OMR1 |= PWM_OC2P_Set;
|
965 |
|
|
}
|
966 |
|
|
else
|
967 |
|
|
{
|
968 |
|
|
PWM->OMR1 &= PWM_OC2P_Reset;
|
969 |
|
|
}
|
970 |
|
|
}
|
971 |
|
|
break;
|
972 |
|
|
}
|
973 |
|
|
switch(PWM_InitStruct->PWM_OCNState)
|
974 |
|
|
{
|
975 |
|
|
case PWM_OCNState_Enable:
|
976 |
|
|
{
|
977 |
|
|
/* Configures Channel 2N on Output Compare mode */
|
978 |
|
|
PWM->OMR1 &= PWM_OC2C_Mask;
|
979 |
|
|
PWM->OMR1 |= (PWM_OCControl<<8)|PWM_OC2N_Enable|PWM_PLD2_Set;
|
980 |
|
|
PWM->OCR2 = PWM_InitStruct->PWM_Pulse2;
|
981 |
|
|
|
982 |
|
|
/* Sets the OC2 wave polarity */
|
983 |
|
|
if(PWM_InitStruct->PWM_Polarity2N == PWM_Polarity2N_Low)
|
984 |
|
|
{
|
985 |
|
|
PWM->OMR1 |= PWM_OC2NP_Set;
|
986 |
|
|
}
|
987 |
|
|
else
|
988 |
|
|
{
|
989 |
|
|
PWM->OMR1 &= PWM_OC2NP_Reset;
|
990 |
|
|
}
|
991 |
|
|
}
|
992 |
|
|
break;
|
993 |
|
|
case PWM_OCNState_Disable:
|
994 |
|
|
{
|
995 |
|
|
/* OC2N = 0 OSSR = 0 */
|
996 |
|
|
PWM->OMR1 &= PWM_OC2N_Disable;
|
997 |
|
|
DTR_REG &= PWM_OSSR_Reset;
|
998 |
|
|
}
|
999 |
|
|
break;
|
1000 |
|
|
case PWM_OCNState_OffState:
|
1001 |
|
|
{
|
1002 |
|
|
/* OC2N = 0 OSSR = 1 and sets the polarity */
|
1003 |
|
|
PWM->OMR1 &= PWM_OC2N_Disable;
|
1004 |
|
|
DTR_REG |= PWM_OSSR_Set;
|
1005 |
|
|
|
1006 |
|
|
if(PWM_InitStruct->PWM_Polarity2N == PWM_Polarity2N_Low)
|
1007 |
|
|
{
|
1008 |
|
|
PWM->OMR1 |= PWM_OC2NP_Set;
|
1009 |
|
|
}
|
1010 |
|
|
else
|
1011 |
|
|
{
|
1012 |
|
|
PWM->OMR1 &= PWM_OC2NP_Reset;
|
1013 |
|
|
}
|
1014 |
|
|
}
|
1015 |
|
|
break;
|
1016 |
|
|
}
|
1017 |
|
|
} /* End not complementary case */
|
1018 |
|
|
}/* end channel 2 */
|
1019 |
|
|
|
1020 |
|
|
/*Channel 3 Configuration-----------------------------------------------------*/
|
1021 |
|
|
if(PWM_InitStruct->PWM_Channel == PWM_Channel_3)
|
1022 |
|
|
{
|
1023 |
|
|
/* PWM Output Complementary Configuration */
|
1024 |
|
|
if(PWM_InitStruct->PWM_Complementary == PWM_Complementary_Enable)
|
1025 |
|
|
{
|
1026 |
|
|
/* Configures Channel 3 on Output Compare mode */
|
1027 |
|
|
PWM->OMR2 &= PWM_OC3C_Mask;
|
1028 |
|
|
PWM->OMR2 |= PWM_OCControl|PWM_OC3_Enable|PWM_OC3N_Enable|PWM_PLD3_Set;
|
1029 |
|
|
PWM->OCR3 = PWM_InitStruct->PWM_Pulse3;
|
1030 |
|
|
|
1031 |
|
|
/* Sets the OC3 wave polarity */
|
1032 |
|
|
if(PWM_InitStruct->PWM_Polarity3 == PWM_Polarity3_Low)
|
1033 |
|
|
{
|
1034 |
|
|
PWM->OMR2 |= PWM_OC3P_Set;
|
1035 |
|
|
}
|
1036 |
|
|
else
|
1037 |
|
|
{
|
1038 |
|
|
PWM->OMR2 &= PWM_OC3P_Reset;
|
1039 |
|
|
}
|
1040 |
|
|
|
1041 |
|
|
/* Sets the OC3N wave polarity */
|
1042 |
|
|
if(PWM_InitStruct->PWM_Polarity3N == PWM_Polarity3N_Low)
|
1043 |
|
|
{
|
1044 |
|
|
PWM->OMR2 |= PWM_OC3NP_Set;
|
1045 |
|
|
}
|
1046 |
|
|
else
|
1047 |
|
|
{
|
1048 |
|
|
PWM->OMR2 &= PWM_OC3NP_Reset;
|
1049 |
|
|
}
|
1050 |
|
|
}/* End complementary case */
|
1051 |
|
|
else
|
1052 |
|
|
/* Single PWM Output configuratuion */
|
1053 |
|
|
{
|
1054 |
|
|
switch(PWM_InitStruct->PWM_OCState)
|
1055 |
|
|
{
|
1056 |
|
|
case PWM_OCState_Enable:
|
1057 |
|
|
{
|
1058 |
|
|
/* Configures Channel 3 on Output Compare mode */
|
1059 |
|
|
PWM->OMR2 &= PWM_OC3C_Mask;
|
1060 |
|
|
PWM->OMR2 |= PWM_OCControl|PWM_OC3_Enable|PWM_PLD3_Set;
|
1061 |
|
|
PWM->OCR3 = PWM_InitStruct->PWM_Pulse3;
|
1062 |
|
|
|
1063 |
|
|
/* Sets the OCC wave polarity */
|
1064 |
|
|
if(PWM_InitStruct->PWM_Polarity3 == PWM_Polarity3_Low)
|
1065 |
|
|
{
|
1066 |
|
|
PWM->OMR2 |= PWM_OC3P_Set;
|
1067 |
|
|
}
|
1068 |
|
|
else
|
1069 |
|
|
{
|
1070 |
|
|
PWM->OMR2 &= PWM_OC3P_Reset;
|
1071 |
|
|
}
|
1072 |
|
|
}
|
1073 |
|
|
break;
|
1074 |
|
|
case PWM_OCState_Disable:
|
1075 |
|
|
{
|
1076 |
|
|
/* OC3E = 0 and OSSR = 0 */
|
1077 |
|
|
PWM->OMR2 &= PWM_OC3_Disable;
|
1078 |
|
|
DTR_REG &= PWM_OSSR_Reset;
|
1079 |
|
|
}
|
1080 |
|
|
break;
|
1081 |
|
|
case PWM_OCState_OffState:
|
1082 |
|
|
{
|
1083 |
|
|
/* OC3E = 0 and OSSR = 1 sets the polarity */
|
1084 |
|
|
PWM->OMR2 &= PWM_OC3_Disable;
|
1085 |
|
|
DTR_REG |= PWM_OSSR_Set;
|
1086 |
|
|
|
1087 |
|
|
if(PWM_InitStruct->PWM_Polarity3 == PWM_Polarity3_Low)
|
1088 |
|
|
{
|
1089 |
|
|
PWM->OMR2 |= PWM_OC3P_Set;
|
1090 |
|
|
}
|
1091 |
|
|
else
|
1092 |
|
|
{
|
1093 |
|
|
PWM->OMR2 &= PWM_OC3P_Reset;
|
1094 |
|
|
}
|
1095 |
|
|
}
|
1096 |
|
|
break;
|
1097 |
|
|
}
|
1098 |
|
|
|
1099 |
|
|
switch(PWM_InitStruct->PWM_OCNState)
|
1100 |
|
|
{
|
1101 |
|
|
case PWM_OCNState_Enable:
|
1102 |
|
|
{
|
1103 |
|
|
/* Configures Channel 3N on Output Compare mode */
|
1104 |
|
|
PWM->OMR2 &= PWM_OC3C_Mask;
|
1105 |
|
|
PWM->OMR2 |= PWM_OCControl |PWM_OC3N_Enable|PWM_PLD3_Set;
|
1106 |
|
|
PWM->OCR3 = PWM_InitStruct->PWM_Pulse3;
|
1107 |
|
|
|
1108 |
|
|
/* Sets the OC3 wave polarity */
|
1109 |
|
|
if(PWM_InitStruct->PWM_Polarity3N == PWM_Polarity3N_Low)
|
1110 |
|
|
{
|
1111 |
|
|
PWM->OMR2 |= PWM_OC3NP_Set;
|
1112 |
|
|
}
|
1113 |
|
|
else
|
1114 |
|
|
{
|
1115 |
|
|
PWM->OMR2 &= PWM_OC3NP_Reset;
|
1116 |
|
|
}
|
1117 |
|
|
}
|
1118 |
|
|
break;
|
1119 |
|
|
case PWM_OCNState_Disable:
|
1120 |
|
|
{
|
1121 |
|
|
/* OC3N = 0 OSSR = 0 */
|
1122 |
|
|
PWM->OMR2 &= PWM_OC3N_Disable;
|
1123 |
|
|
DTR_REG &= PWM_OSSR_Reset;
|
1124 |
|
|
}
|
1125 |
|
|
break;
|
1126 |
|
|
case PWM_OCNState_OffState:
|
1127 |
|
|
{
|
1128 |
|
|
/* OC3N = 0 OSSR = 1 and sets the polarity */
|
1129 |
|
|
PWM->OMR2 &= PWM_OC3N_Disable;
|
1130 |
|
|
DTR_REG |= PWM_OSSR_Set;
|
1131 |
|
|
|
1132 |
|
|
if(PWM_InitStruct->PWM_Polarity3N == PWM_Polarity3N_Low)
|
1133 |
|
|
{
|
1134 |
|
|
PWM->OMR2 |= PWM_OC3NP_Set;
|
1135 |
|
|
}
|
1136 |
|
|
else
|
1137 |
|
|
{
|
1138 |
|
|
PWM->OMR2 &= PWM_OC3NP_Reset;
|
1139 |
|
|
}
|
1140 |
|
|
}
|
1141 |
|
|
break;
|
1142 |
|
|
}
|
1143 |
|
|
} /* End not complementary case */
|
1144 |
|
|
}/* end channel 3 */
|
1145 |
|
|
|
1146 |
|
|
if(PWM_InitStruct->PWM_DTRAccess == PWM_DTRAccess_Enable)
|
1147 |
|
|
{
|
1148 |
|
|
DTR_REG |= PWM_InitStruct->PWM_LOCKLevel | PWM_InitStruct->PWM_Emergency |
|
1149 |
|
|
PWM_InitStruct->PWM_DeadTime | PWM_InitStruct->PWM_OSSIState;
|
1150 |
|
|
PWM->DTR = DTR_REG;
|
1151 |
|
|
}
|
1152 |
|
|
}
|
1153 |
|
|
/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/
|