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jeremybenn |
/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
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* File Name : 75x_tim.c
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* Author : MCD Application Team
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* Date First Issued : 03/10/2006
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* Description : This file provides all the TIM software functions.
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********************************************************************************
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* History:
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* 07/17/2006 : V1.0
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* 03/10/2006 : V0.1
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********************************************************************************
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* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
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* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
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* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
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* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
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* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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*******************************************************************************/
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/* Includes ------------------------------------------------------------------*/
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#include "75x_tim.h"
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#include "75x_mrcc.h"
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/* Private typedef -----------------------------------------------------------*/
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/* Private define ------------------------------------------------------------*/
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/* Private macro -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* TIM interrupt masks */
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#define TIM_IT_Clear_Mask 0x7FFF
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#define TIM_IT_Enable_Mask 0x7FFF
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/* TIM Input Capture Selection Set/Reset */
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#define TIM_IC1S_Set 0x0001
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#define TIM_IC1S_Reset 0x003E
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/* TIM Input Capture Selection Set/Reset */
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#define TIM_IC2S_Set 0x0002
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#define TIM_IC2S_Reset 0x003D
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/* TIM_SCR Masks bit */
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#define TIM_Encoder_Mask 0x731C
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#define TIM_SlaveModeSelection_Mask 0x7307
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#define TIM_TriggerSelection_Mask 0x701F
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#define TIM_InternalTriggerSelection_Mask 0x031F
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/* TIM Encoder mode Set value */
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#define TIM_Encoder1_Set 0x0001
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#define TIM_Encoder2_Set 0x0002
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#define TIM_Encoder3_Set 0x0003
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/* TIM Slave Mode Enable Set/Reset value */
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#define TIM_SME_Reset 0x731B
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#define TIM_SME_Set 0x0004
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/* TIM Internal Trigger Selection value */
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#define TIM_ITS_TIM0 0x1000
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#define TIM_ITS_TIM1 0x2000
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#define TIM_ITS_TIM2 0x3000
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#define TIM_ITS_PWM 0x4000
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/* TIM Trigger Selection value */
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#define TIM_TS_IC1_Set 0x0200
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#define TIM_TS_IC2_Set 0x0300
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/* TIM Slave Mode selction external clock Set value */
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#define TIM_SMS_EXTCLK_Set 0x0008
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#define TIM_SMS_RESETCLK_Set 0x0000
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/* TIM_CR Masks bit */
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#define TIM_DBASE_Mask 0x077F
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#define TIM_MasterModeSelection_Mask 0xFC7F
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#define TIM_CounterMode_Mask 0xFF8F
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/* TIM Update flag selection Set/Reset value */
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#define TIM_UFS_Reset 0xFFFE
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#define TIM_UFS_Set 0x0001
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/* TIM Counter value */
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#define TIM_COUNTER_Reset 0x0002
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#define TIM_COUNTER_Start 0x0004
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#define TIM_COUNTER_Stop 0xFFFB
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/* TIM One pulse Mode set value */
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#define TIM_OPM_Set 0x0008
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#define TIM_OPM_Reset 0xFFF7
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/* TIM Debug Mode Set/Reset value */
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#define TIM_DBGC_Set 0x0400
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#define TIM_DBGC_Reset 0xFB7F
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/* TIM Input Capture Enable/Disable value */
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#define TIM_IC1_Enable 0x0004
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#define TIM_IC2_Enable 0x0010
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/* TIM Input Capture Polarity Set/Reset value */
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#define TIM_IC1P_Set 0x0008
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#define TIM_IC2P_Set 0x0020
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#define TIM_IC1P_Reset 0x0037
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#define TIM_IC2P_Reset 0x001F
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/* TIM Output Compare Polarity Set/Reset value */
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#define TIM_OC1P_Set 0x0020
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#define TIM_OC2P_Set 0x2000
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#define TIM_OC1P_Reset 0x3F1F
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#define TIM_OC2P_Reset 0x1F3F
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/* TIM Output Compare control mode constant */
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#define TIM_OCControl_PWM 0x000C
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#define TIM_OCControl_OCToggle 0x0006
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#define TIM_OCControl_OCInactive 0x0004
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#define TIM_OCControl_OCActive 0x0002
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#define TIM_OCControl_OCTiming 0x0000
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/* TIM Output Compare mode Enable value */
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#define TIM_OC1_Enable 0x0010
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#define TIM_OC2_Enable 0x1000
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/* TIM Output Compare mode Mask value */
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#define TIM_OC1C_Mask 0x3F31
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#define TIM_OC2C_Mask 0x313F
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/* TIM Preload bit Set/Reset value */
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#define TIM_PLD1_Set 0x0001
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#define TIM_PLD1_Reset 0xFFFE
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#define TIM_PLD2_Set 0x0100
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#define TIM_PLD2_Reset 0xFEFF
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/* TIM OCRM Set/Reset value */
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#define TIM_OCRM_Set 0x0080
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#define TIM_OCRM_Reset 0x030D
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/* Reset Register Masks */
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#define TIM_Pulse2_Reset_Mask 0x0000
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#define TIM_Prescaler_Reset_Mask 0x0000
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#define TIM_Pulse1_Reset_Mask 0x0000
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#define TIM_Period_Reset_Mask 0xFFFF
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#define TIM_Counter_Reset 0x0002
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/* Private function prototypes -----------------------------------------------*/
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static void ICAP_ModuleConfig(TIM_TypeDef* TIMx, TIM_InitTypeDef* TIM_InitStruct);
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static void Encoder_ModeConfig(TIM_TypeDef* TIMx, TIM_InitTypeDef* TIM_InitStruct);
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static void OCM_ModuleConfig(TIM_TypeDef* TIMx, TIM_InitTypeDef* TIM_InitStruct);
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/* Private functions ---------------------------------------------------------*/
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/******************************************************************************
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* Function Name : TIM_DeInit
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* Description : Deinitializes TIM peripheral registers to their default reset
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* values.
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* Input : TIMx: where x can be 0, 1 or 2 to select the TIM peripheral.
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* Output : None
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* Return : None
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*******************************************************************************/
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void TIM_DeInit(TIM_TypeDef *TIMx)
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{
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if(TIMx == TIM0)
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{
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MRCC_PeripheralSWResetConfig(MRCC_Peripheral_TIM0,ENABLE);
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MRCC_PeripheralSWResetConfig(MRCC_Peripheral_TIM0,DISABLE);
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}
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else if(TIMx == TIM1)
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{
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MRCC_PeripheralSWResetConfig(MRCC_Peripheral_TIM1,ENABLE);
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MRCC_PeripheralSWResetConfig(MRCC_Peripheral_TIM1,DISABLE);
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}
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else if(TIMx == TIM2)
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{
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MRCC_PeripheralSWResetConfig(MRCC_Peripheral_TIM2,ENABLE);
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MRCC_PeripheralSWResetConfig(MRCC_Peripheral_TIM2,DISABLE);
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}
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}
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/*******************************************************************************
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* Function Name : TIM_Init
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* Description : Initializes the TIMx peripheral according to the specified
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* parameters in the TIM_InitStruct .
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* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral.
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* - TIM_InitStruct: pointer to a TIM_InitTypeDef structure that
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* contains the configuration information for the specified TIM
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* peripheral.
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* Output : None
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* Return : None
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*******************************************************************************/
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void TIM_Init(TIM_TypeDef* TIMx, TIM_InitTypeDef* TIM_InitStruct)
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{
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/* Set the prescaler value */
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TIMx->PSC = TIM_InitStruct->TIM_Prescaler;
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/* Select the clock source */
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TIM_ClockSourceConfig(TIMx, TIM_InitStruct->TIM_ClockSource,
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TIM_InitStruct->TIM_ExtCLKEdge);
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/* Select the counter mode */
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TIMx->CR &= TIM_CounterMode_Mask;
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TIMx->CR |= TIM_InitStruct->TIM_CounterMode;
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/* Set the period value */
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TIMx->ARR = TIM_InitStruct->TIM_Period;
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switch(TIM_InitStruct->TIM_Mode)
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{
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case TIM_Mode_OCTiming: case TIM_Mode_OCActive: case TIM_Mode_OCInactive:
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case TIM_Mode_OCToggle: case TIM_Mode_PWM:
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OCM_ModuleConfig(TIMx, TIM_InitStruct);
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break;
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case TIM_Mode_PWMI: case TIM_Mode_IC:
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ICAP_ModuleConfig(TIMx, TIM_InitStruct);
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break;
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case TIM_Mode_Encoder1: case TIM_Mode_Encoder2: case TIM_Mode_Encoder3:
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Encoder_ModeConfig(TIMx, TIM_InitStruct);
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break;
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case TIM_Mode_OPM_PWM: case TIM_Mode_OPM_Toggle: case TIM_Mode_OPM_Active:
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/* Output module configuration */
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OCM_ModuleConfig(TIMx, TIM_InitStruct);
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/* Input module configuration */
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ICAP_ModuleConfig(TIMx, TIM_InitStruct);
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/* Set the slave mode to trigger Mode */
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TIMx->SCR |= TIM_SynchroMode_Trigger;
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/* Repetitive pulse state selection */
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if(TIM_InitStruct->TIM_RepetitivePulse == TIM_RepetitivePulse_Disable)
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{
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TIMx->CR |= TIM_OPM_Set;
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}
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else
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{
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TIMx->CR &= TIM_OPM_Reset;
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}
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break;
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default:
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break;
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}
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}
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/*******************************************************************************
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* Function Name : TIM_StructInit
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* Description : Fills each TIM_InitStruct member with its default value.
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* Input : TIM_InitStruct : pointer to a TIM_InitTypeDef structure
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* which will be initialized.
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* Output : None
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* Return : None.
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*******************************************************************************/
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void TIM_StructInit(TIM_InitTypeDef *TIM_InitStruct)
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{
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/* Set the default configuration */
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TIM_InitStruct->TIM_Mode = TIM_Mode_OCTiming;
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TIM_InitStruct->TIM_Prescaler = TIM_Prescaler_Reset_Mask;
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TIM_InitStruct->TIM_ClockSource = TIM_ClockSource_Internal;
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TIM_InitStruct->TIM_ExtCLKEdge = TIM_ExtCLKEdge_Rising;
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TIM_InitStruct->TIM_CounterMode = TIM_CounterMode_Up;
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TIM_InitStruct->TIM_Period = TIM_Period_Reset_Mask;
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TIM_InitStruct->TIM_Channel = TIM_Channel_ALL;
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TIM_InitStruct->TIM_Pulse1 = TIM_Pulse1_Reset_Mask;
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TIM_InitStruct->TIM_Pulse2 = TIM_Pulse2_Reset_Mask;
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TIM_InitStruct->TIM_RepetitivePulse = TIM_RepetitivePulse_Disable;
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TIM_InitStruct->TIM_Polarity1 = TIM_Polarity1_Low;
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TIM_InitStruct->TIM_Polarity2 = TIM_Polarity2_Low;
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TIM_InitStruct->TIM_IC1Selection = TIM_IC1Selection_TI1;
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TIM_InitStruct->TIM_IC2Selection = TIM_IC2Selection_TI1;
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TIM_InitStruct->TIM_IC1Polarity = TIM_IC1Polarity_Rising;
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TIM_InitStruct->TIM_IC2Polarity = TIM_IC2Polarity_Rising;
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TIM_InitStruct->TIM_PWMI_ICSelection = TIM_PWMI_ICSelection_TI1;
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TIM_InitStruct->TIM_PWMI_ICPolarity = TIM_PWMI_ICPolarity_Rising;
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}
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/*******************************************************************************
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* Function Name : TIM_Cmd
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* Description : Enables or disables the specified TIM peripheral.
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* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral.
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* - Newstate: new state of the TIMx peripheral.
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* This parameter can be: ENABLE or DISABLE.
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* Output : None
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* Return : None
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*******************************************************************************/
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void TIM_Cmd(TIM_TypeDef *TIMx, FunctionalState Newstate)
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{
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if(Newstate == ENABLE)
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{
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TIMx->CR |= TIM_COUNTER_Start;
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}
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else
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{
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TIMx->CR &= TIM_COUNTER_Stop;
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}
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}
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/*******************************************************************************
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* Function Name : TIM_ITConfig
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* Description : Enables or disables the TIM interrupts.
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* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral.
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* - TIM_IT: specifies the TIM interrupts sources to be enabled
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* or disabled.
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* This parameter can be any combination of the following values:
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* - TIM_IT_IC1: Input Capture 1 Interrupt
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* - TIM_IT_OC1: Output Compare 1 Interrupt
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* - TIM_IT_Update: Timer update Interrupt
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* - TIM_IT_GlobalUpdate: Timer global update Interrupt
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* - TIM_IT_IC2: Input Capture 2 Interrupt
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* - TIM_IT_OC2: Output Compare 2 Interrupt
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* - Newstate: new state of the specified TIMx interrupts.
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* This parameter can be: ENABLE or DISABLE.
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* Output : None
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* Return : None
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*******************************************************************************/
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void TIM_ITConfig(TIM_TypeDef *TIMx, u16 TIM_IT, FunctionalState Newstate)
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{
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u16 TIM_IT_Enable = 0;
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TIM_IT_Enable = TIM_IT & TIM_IT_Enable_Mask;
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if(Newstate == ENABLE)
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{
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/* Update interrupt global source: overflow/undeflow, counter reset operation
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or slave mode controller in reset mode */
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if((TIM_IT & TIM_IT_GlobalUpdate) == TIM_IT_GlobalUpdate)
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{
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TIMx->CR &= TIM_UFS_Reset;
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}
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/* Update interrupt source: counter overflow/underflow */
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else if((TIM_IT & TIM_IT_Update) == TIM_IT_Update)
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{
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TIMx->CR |= TIM_UFS_Set;
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}
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/* Select and enable the interrupts requests */
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TIMx->RSR |= TIM_IT_Enable;
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TIMx->RER |= TIM_IT_Enable;
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}
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/* Disable the interrupts requests */
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else
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{
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TIMx->RSR &= ~TIM_IT_Enable;
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TIMx->RER &= ~TIM_IT_Enable;
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}
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}
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|
343 |
|
|
/*******************************************************************************
|
344 |
|
|
* Function Name : TIM_PreloadConfig
|
345 |
|
|
* Description : Enables or disables TIM peripheral Preload register on OCRx.
|
346 |
|
|
* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral.
|
347 |
|
|
* - TIM_Channel: specifies the TIM channel to be used.
|
348 |
|
|
* This parameter can be one of the following values:
|
349 |
|
|
* - TIM_Channel_1: TIM Channel 1 is used
|
350 |
|
|
* - TIM_Channel_2: TIM Channel 2 is used
|
351 |
|
|
* - TIM_Channel_ALL: TIM Channel 1and 2 are used
|
352 |
|
|
* - Newstate: new state of the TIMx peripheral Preload register
|
353 |
|
|
* This parameter can be: ENABLE or DISABLE.
|
354 |
|
|
* Output : None
|
355 |
|
|
* Return : None
|
356 |
|
|
*******************************************************************************/
|
357 |
|
|
void TIM_PreloadConfig(TIM_TypeDef *TIMx, u16 TIM_Channel, FunctionalState Newstate)
|
358 |
|
|
{
|
359 |
|
|
if(Newstate == ENABLE)
|
360 |
|
|
{
|
361 |
|
|
switch (TIM_Channel)
|
362 |
|
|
{
|
363 |
|
|
case TIM_Channel_1:
|
364 |
|
|
TIMx->OMR1 |= TIM_PLD1_Set;
|
365 |
|
|
break;
|
366 |
|
|
|
367 |
|
|
case TIM_Channel_2:
|
368 |
|
|
TIMx->OMR1 |= TIM_PLD2_Set;
|
369 |
|
|
break;
|
370 |
|
|
|
371 |
|
|
case TIM_Channel_ALL:
|
372 |
|
|
TIMx->OMR1 |= TIM_PLD1_Set | TIM_PLD2_Set;
|
373 |
|
|
break;
|
374 |
|
|
|
375 |
|
|
default:
|
376 |
|
|
break;
|
377 |
|
|
}
|
378 |
|
|
}
|
379 |
|
|
else
|
380 |
|
|
{
|
381 |
|
|
switch (TIM_Channel)
|
382 |
|
|
{
|
383 |
|
|
case TIM_Channel_1:
|
384 |
|
|
TIMx->OMR1 &= TIM_PLD1_Reset;
|
385 |
|
|
break;
|
386 |
|
|
|
387 |
|
|
case TIM_Channel_2:
|
388 |
|
|
TIMx->OMR1 &= TIM_PLD2_Reset;
|
389 |
|
|
break;
|
390 |
|
|
|
391 |
|
|
case TIM_Channel_ALL:
|
392 |
|
|
TIMx->OMR1 &= TIM_PLD1_Reset & TIM_PLD2_Reset;
|
393 |
|
|
break;
|
394 |
|
|
|
395 |
|
|
default:
|
396 |
|
|
break;
|
397 |
|
|
}
|
398 |
|
|
}
|
399 |
|
|
}
|
400 |
|
|
|
401 |
|
|
/*******************************************************************************
|
402 |
|
|
* Function Name : TIM_DMAConfig
|
403 |
|
|
* Description : Configures the TIM0’s DMA interface.
|
404 |
|
|
* Input : - TIM_DMASources: specifies the DMA Request sources.
|
405 |
|
|
* This parameter can be any combination of the following values:
|
406 |
|
|
* - TIM_DMASource_OC1: Output Compare 1 DMA source
|
407 |
|
|
* - TIM_DMASource_OC2: Output Compare 2 DMA source
|
408 |
|
|
* - TIM_DMASource_IC1: Input Capture 1 DMA source
|
409 |
|
|
* - TIM_DMASource_IC2: Input Capture 2 DMA source
|
410 |
|
|
* - TIM_DMASource_Update: Timer Update DMA source
|
411 |
|
|
* - TIM_OCRMState: the state of output compare request mode.
|
412 |
|
|
* This parameter can be one of the following values:
|
413 |
|
|
* - TIM_OCRMState_Enable
|
414 |
|
|
* - TIM_OCRMState_Disable
|
415 |
|
|
* - TIM_DMABase:DMA Base address.
|
416 |
|
|
* This parameter can be one of the following values:
|
417 |
|
|
* TIM_DMABase_CR, TIM_DMABase_SCR, TIM_DMABase_IMCR,
|
418 |
|
|
* TIM_DMABase_OMR1, TIM_DMABase_RSR,
|
419 |
|
|
* TIM_DMABase_RER, TIM_DMABase_ISR, TIM_DMABase_CNT,
|
420 |
|
|
* TIM_DMABase_PSC, TIM_DMABase_ARR, TIM_DMABase_OCR1,
|
421 |
|
|
* TIM_DMABase_OCR2, TIM_DMABase_ICR1, TIM_DMABase_ICR2
|
422 |
|
|
* Output : None
|
423 |
|
|
* Return : None
|
424 |
|
|
*******************************************************************************/
|
425 |
|
|
void TIM_DMAConfig(u16 TIM_DMASources, u16 TIM_OCRMState, u16 TIM_DMABase)
|
426 |
|
|
{
|
427 |
|
|
/* Select the DMA requests */
|
428 |
|
|
TIM0->RSR &= TIM_DMASources;
|
429 |
|
|
|
430 |
|
|
/* Set the OCRM state */
|
431 |
|
|
if(TIM_OCRMState == TIM_OCRMState_Enable)
|
432 |
|
|
{
|
433 |
|
|
TIM0->RSR |= TIM_OCRM_Set;
|
434 |
|
|
}
|
435 |
|
|
else
|
436 |
|
|
{
|
437 |
|
|
TIM0->RSR &= TIM_OCRM_Reset;
|
438 |
|
|
}
|
439 |
|
|
|
440 |
|
|
/* Set the DMA Base address */
|
441 |
|
|
TIM0->CR &= TIM_DBASE_Mask;
|
442 |
|
|
TIM0->CR |= TIM_DMABase;
|
443 |
|
|
}
|
444 |
|
|
|
445 |
|
|
/*******************************************************************************
|
446 |
|
|
* Function Name : TIM_DMACmd
|
447 |
|
|
* Description : Enables or disables the TIM0’s DMA interface.
|
448 |
|
|
* Input : - TIM_DMASources: specifies the DMA Request sources.
|
449 |
|
|
* This parameter can be any combination of the following values:
|
450 |
|
|
* - TIM_DMASource_OC1: Output Compare 1 DMA source
|
451 |
|
|
* - TIM_DMASource_OC2: Output Compare 2 DMA source
|
452 |
|
|
* - TIM_DMASource_IC1: Input Capture 1 DMA source
|
453 |
|
|
* - TIM_DMASource_IC2: Input Capture 2 DMA source
|
454 |
|
|
* - TIM_DMASource_Update: Timer Update DMA source
|
455 |
|
|
* - Newstate: new state of the DMA Request sources.
|
456 |
|
|
* This parameter can be: ENABLE or DISABLE.
|
457 |
|
|
* Output : None
|
458 |
|
|
* Return : None
|
459 |
|
|
*******************************************************************************/
|
460 |
|
|
void TIM_DMACmd(u16 TIM_DMASources, FunctionalState Newstate)
|
461 |
|
|
{
|
462 |
|
|
if(Newstate == ENABLE)
|
463 |
|
|
{
|
464 |
|
|
TIM0->RER |= TIM_DMASources;
|
465 |
|
|
}
|
466 |
|
|
else
|
467 |
|
|
{
|
468 |
|
|
TIM0->RER &= ~TIM_DMASources;
|
469 |
|
|
}
|
470 |
|
|
}
|
471 |
|
|
|
472 |
|
|
/*******************************************************************************
|
473 |
|
|
* Function Name : TIM_ClockSourceConfig
|
474 |
|
|
* Description : Configures the TIM clock source.
|
475 |
|
|
* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral.
|
476 |
|
|
* - TIM_ClockSource: specifies the TIM clock source to be
|
477 |
|
|
* selected.
|
478 |
|
|
* This parameter can be one of the following values:
|
479 |
|
|
* - TIM_ClockSource_Internal: CK_TIM internal clock
|
480 |
|
|
* - TIM_ClockSource_TI11: External input pin TI1
|
481 |
|
|
* connected to IC1 channel.
|
482 |
|
|
* - TIM_ClockSource_TI12: External input pin TI1
|
483 |
|
|
* connected to IC2 channel.
|
484 |
|
|
* - TIM_ClockSource_TI22: External input pin TI2
|
485 |
|
|
* connected to IC2 channel.
|
486 |
|
|
* - TIM_ClockSource_TI21: External input pin TI2
|
487 |
|
|
* connected to IC1 channel.
|
488 |
|
|
* - TIM_ExtCLKEdge: specifies the External input signal edge.
|
489 |
|
|
* This parameter can be one of the following values:
|
490 |
|
|
* - TIM_ExtCLKEdge_Falling : Falling edge selected.
|
491 |
|
|
* - TIM_ExtCLKEdge_Rising : Rising edge selected.
|
492 |
|
|
* Output : None
|
493 |
|
|
* Return : None
|
494 |
|
|
*******************************************************************************/
|
495 |
|
|
void TIM_ClockSourceConfig(TIM_TypeDef *TIMx, u16 TIM_ClockSource,
|
496 |
|
|
u16 TIM_ExtCLKEdge)
|
497 |
|
|
{
|
498 |
|
|
if(TIM_ClockSource == TIM_ClockSource_Internal)
|
499 |
|
|
{
|
500 |
|
|
/* CK_TIM is used as clock source */
|
501 |
|
|
TIMx->SCR &= TIM_SME_Reset & TIM_SlaveModeSelection_Mask & TIM_TriggerSelection_Mask;
|
502 |
|
|
}
|
503 |
|
|
else
|
504 |
|
|
/* Input Captures are used as TIM external clock */
|
505 |
|
|
{
|
506 |
|
|
TIMx->SCR &= TIM_SME_Reset & TIM_SlaveModeSelection_Mask & TIM_TriggerSelection_Mask;
|
507 |
|
|
TIMx->SCR |= TIM_SMS_EXTCLK_Set | TIM_SME_Set;
|
508 |
|
|
|
509 |
|
|
if((TIM_ClockSource == TIM_ClockSource_TI11) ||
|
510 |
|
|
(TIM_ClockSource == TIM_ClockSource_TI21))
|
511 |
|
|
/* Input Capture 1 is selected */
|
512 |
|
|
{
|
513 |
|
|
/* Input capture Enable */
|
514 |
|
|
TIMx->IMCR |= TIM_IC1_Enable;
|
515 |
|
|
TIMx->SCR |= TIM_TS_IC1_Set;
|
516 |
|
|
|
517 |
|
|
if(TIM_ExtCLKEdge == TIM_ExtCLKEdge_Falling)
|
518 |
|
|
/* Set the corresponding polarity */
|
519 |
|
|
{
|
520 |
|
|
TIMx->IMCR |= TIM_IC1P_Set;
|
521 |
|
|
}
|
522 |
|
|
else
|
523 |
|
|
{
|
524 |
|
|
TIMx->IMCR &= TIM_IC1P_Reset;
|
525 |
|
|
}
|
526 |
|
|
if(TIM_ClockSource == TIM_ClockSource_TI11)
|
527 |
|
|
{
|
528 |
|
|
/* External signal TI1 connected to IC1 channel */
|
529 |
|
|
TIMx->IMCR &= TIM_IC1S_Reset;
|
530 |
|
|
}
|
531 |
|
|
else
|
532 |
|
|
{
|
533 |
|
|
/* External signal TI2 connected to IC1 channel */
|
534 |
|
|
TIMx->IMCR |= TIM_IC1S_Set;
|
535 |
|
|
}
|
536 |
|
|
}
|
537 |
|
|
else
|
538 |
|
|
/* Input Capture 2 is selected */
|
539 |
|
|
{
|
540 |
|
|
/* Input capture Enable */
|
541 |
|
|
TIMx->IMCR |= TIM_IC2_Enable;
|
542 |
|
|
TIMx->SCR |= TIM_TS_IC2_Set;
|
543 |
|
|
|
544 |
|
|
if(TIM_ExtCLKEdge == TIM_ExtCLKEdge_Falling)
|
545 |
|
|
/* Set the corresponding polarity */
|
546 |
|
|
{
|
547 |
|
|
TIMx->IMCR |= TIM_IC2P_Set;
|
548 |
|
|
}
|
549 |
|
|
else
|
550 |
|
|
{
|
551 |
|
|
TIMx->IMCR &= TIM_IC2P_Reset;
|
552 |
|
|
}
|
553 |
|
|
if(TIM_ClockSource == TIM_ClockSource_TI22)
|
554 |
|
|
{
|
555 |
|
|
/* External signal TI2 connected to IC2 channel */
|
556 |
|
|
TIMx->IMCR &= TIM_IC2S_Reset;
|
557 |
|
|
}
|
558 |
|
|
else
|
559 |
|
|
{
|
560 |
|
|
/* External signal TI1 connected to IC2 channel */
|
561 |
|
|
TIMx->IMCR |= TIM_IC2S_Set;
|
562 |
|
|
}
|
563 |
|
|
}
|
564 |
|
|
}
|
565 |
|
|
}
|
566 |
|
|
|
567 |
|
|
/*******************************************************************************
|
568 |
|
|
* Function Name : TIM_SetPrescaler
|
569 |
|
|
* Description : Sets the TIM prescaler value.
|
570 |
|
|
* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral
|
571 |
|
|
* - Prescaler: TIM prescaler new value.
|
572 |
|
|
* Output : None
|
573 |
|
|
* Return : None
|
574 |
|
|
*******************************************************************************/
|
575 |
|
|
void TIM_SetPrescaler(TIM_TypeDef* TIMx, u16 Prescaler)
|
576 |
|
|
{
|
577 |
|
|
TIMx->PSC = Prescaler;
|
578 |
|
|
}
|
579 |
|
|
|
580 |
|
|
/*******************************************************************************
|
581 |
|
|
* Function Name : TIM_SetPeriod
|
582 |
|
|
* Description : Sets the TIM period value.
|
583 |
|
|
* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral
|
584 |
|
|
* - Period: TIM period new value.
|
585 |
|
|
* Output : None
|
586 |
|
|
* Return : None
|
587 |
|
|
*******************************************************************************/
|
588 |
|
|
void TIM_SetPeriod(TIM_TypeDef* TIMx, u16 Period)
|
589 |
|
|
{
|
590 |
|
|
TIMx->ARR = Period;
|
591 |
|
|
}
|
592 |
|
|
|
593 |
|
|
/*******************************************************************************
|
594 |
|
|
* Function Name : TIM_SetPulse
|
595 |
|
|
* Description : Sets the TIM pulse value.
|
596 |
|
|
* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral
|
597 |
|
|
* - TIM_Channel: specifies the TIM channel to be used.
|
598 |
|
|
* This parameter can be one of the following values:
|
599 |
|
|
* - TIM_Channel_1: TIM Channel 1 is used
|
600 |
|
|
* - TIM_Channel_2: TIM Channel 2 is used
|
601 |
|
|
* - TIM_Channel_ALL: TIM Channel 1and 2 are used
|
602 |
|
|
* - Pulse: TIM pulse new value.
|
603 |
|
|
* Output : None
|
604 |
|
|
* Return : None
|
605 |
|
|
*******************************************************************************/
|
606 |
|
|
void TIM_SetPulse(TIM_TypeDef* TIMx, u16 TIM_Channel, u16 Pulse)
|
607 |
|
|
{
|
608 |
|
|
/* Set Channel 1 pulse value */
|
609 |
|
|
if(TIM_Channel == TIM_Channel_1)
|
610 |
|
|
{
|
611 |
|
|
TIMx->OCR1 = Pulse;
|
612 |
|
|
}
|
613 |
|
|
/* Set Channel 2 pulse value */
|
614 |
|
|
else if(TIM_Channel == TIM_Channel_2)
|
615 |
|
|
{
|
616 |
|
|
TIMx->OCR2 = Pulse;
|
617 |
|
|
}
|
618 |
|
|
/* Set Channel 1 and Channel 2 pulse values */
|
619 |
|
|
else if(TIM_Channel == TIM_Channel_ALL)
|
620 |
|
|
{
|
621 |
|
|
TIMx->OCR1 = Pulse;
|
622 |
|
|
TIMx->OCR2 = Pulse;
|
623 |
|
|
}
|
624 |
|
|
}
|
625 |
|
|
|
626 |
|
|
/*******************************************************************************
|
627 |
|
|
* Function Name : TIM_GetICAP1
|
628 |
|
|
* Description : Gets the Input Capture 1 value.
|
629 |
|
|
* Input : TIMx: where x can be 0, 1 or 2 to select the TIM peripheral
|
630 |
|
|
* Output : None
|
631 |
|
|
* Return : Input Capture 1 Register value.
|
632 |
|
|
*******************************************************************************/
|
633 |
|
|
u16 TIM_GetICAP1(TIM_TypeDef *TIMx)
|
634 |
|
|
{
|
635 |
|
|
return TIMx->ICR1;
|
636 |
|
|
}
|
637 |
|
|
|
638 |
|
|
/*******************************************************************************
|
639 |
|
|
* Function Name : TIM_GetICAP2
|
640 |
|
|
* Description : Gets the Input Capture 2 value.
|
641 |
|
|
* Input : TIMx: where x can be 0, 1 or 2 to select the TIM peripheral
|
642 |
|
|
* Output : None
|
643 |
|
|
* Return : Input Capture 2 Register value
|
644 |
|
|
*******************************************************************************/
|
645 |
|
|
u16 TIM_GetICAP2(TIM_TypeDef *TIMx)
|
646 |
|
|
{
|
647 |
|
|
return TIMx->ICR2;
|
648 |
|
|
}
|
649 |
|
|
|
650 |
|
|
/*******************************************************************************
|
651 |
|
|
* Function Name : TIM_GetPWMIPulse
|
652 |
|
|
* Description : Gets the PWM Input pulse value.
|
653 |
|
|
* Input : TIMx: where x can be 0, 1 or 2 to select the TIM peripheral
|
654 |
|
|
* Output : None
|
655 |
|
|
* Return : Input Capture 2 Register value
|
656 |
|
|
*******************************************************************************/
|
657 |
|
|
u16 TIM_GetPWMIPulse(TIM_TypeDef *TIMx)
|
658 |
|
|
{
|
659 |
|
|
return TIMx->ICR2;
|
660 |
|
|
}
|
661 |
|
|
|
662 |
|
|
/*******************************************************************************
|
663 |
|
|
* Function Name : TIM_GetPWMIPeriod
|
664 |
|
|
* Description : Gets the PWM Input period value.
|
665 |
|
|
* Input : TIMx: where x can be 0, 1 or 2 to select the TIM peripheral
|
666 |
|
|
* Output : None
|
667 |
|
|
* Return : Input Capture 1 Register value
|
668 |
|
|
*******************************************************************************/
|
669 |
|
|
u16 TIM_GetPWMIPeriod(TIM_TypeDef *TIMx)
|
670 |
|
|
{
|
671 |
|
|
return TIMx->ICR1;
|
672 |
|
|
}
|
673 |
|
|
|
674 |
|
|
/*******************************************************************************
|
675 |
|
|
* Function Name : TIM_DebugCmd
|
676 |
|
|
* Description : Enables or disables the specified TIM peripheral Debug control.
|
677 |
|
|
* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral
|
678 |
|
|
* - Newstate: new state of the TIMx Debug control.
|
679 |
|
|
This parameter can be: ENABLE or DISABLE.
|
680 |
|
|
* Output : None
|
681 |
|
|
* Return : None
|
682 |
|
|
*******************************************************************************/
|
683 |
|
|
void TIM_DebugCmd(TIM_TypeDef *TIMx, FunctionalState Newstate)
|
684 |
|
|
{
|
685 |
|
|
if(Newstate == ENABLE)
|
686 |
|
|
{
|
687 |
|
|
TIMx->CR |= TIM_DBGC_Set;
|
688 |
|
|
}
|
689 |
|
|
else
|
690 |
|
|
{
|
691 |
|
|
TIMx->CR &= TIM_DBGC_Reset;
|
692 |
|
|
}
|
693 |
|
|
}
|
694 |
|
|
|
695 |
|
|
/*******************************************************************************
|
696 |
|
|
* Function Name : TIM_CounterModeConfig
|
697 |
|
|
* Description : Specifies the Counter Mode to be used.
|
698 |
|
|
* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral.
|
699 |
|
|
* - TIM_CounterMode: specifies the Counter Mode to be used
|
700 |
|
|
* This parameter can be one of the following values:
|
701 |
|
|
* - TIM_CounterMode_Up: TIM Up Counting Mode
|
702 |
|
|
* - TIM_CounterMode_Down: TIM Down Counting Mode
|
703 |
|
|
* - TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1
|
704 |
|
|
* - TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2
|
705 |
|
|
* - TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3
|
706 |
|
|
* Output : None
|
707 |
|
|
* Return : None
|
708 |
|
|
*******************************************************************************/
|
709 |
|
|
void TIM_CounterModeConfig(TIM_TypeDef* TIMx, u16 TIM_CounterMode)
|
710 |
|
|
{
|
711 |
|
|
/* Counter mode configuration */
|
712 |
|
|
TIMx->CR &= TIM_CounterMode_Mask;
|
713 |
|
|
TIMx->CR |= TIM_CounterMode;
|
714 |
|
|
}
|
715 |
|
|
|
716 |
|
|
/*******************************************************************************
|
717 |
|
|
* Function Name : TIM_ForcedOCConfig
|
718 |
|
|
* Description : Forces the TIM output waveform to active or inactive level.
|
719 |
|
|
* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral.
|
720 |
|
|
* - TIM_Channel: specifies the TIM channel to be used.
|
721 |
|
|
* This parameter can be one of the following values:
|
722 |
|
|
* - TIM_Channel_1: Timer Channel 1 is used
|
723 |
|
|
* - TIM_Channel_2: Timer Channel 2 is used
|
724 |
|
|
* - TIM_Channel_ALL: Timer Channel 1 and 2 are used
|
725 |
|
|
* - TIM_ForcedAction: specifies the forced Action to be set to
|
726 |
|
|
* the output waveform.
|
727 |
|
|
* This parameter can be one of the following values:
|
728 |
|
|
* - TIM_ForcedAction_Active: Force active level on OCxREF
|
729 |
|
|
* - TIM_ForcedAction_InActive: Force inactive level on
|
730 |
|
|
* OCxREF.
|
731 |
|
|
* Output : None
|
732 |
|
|
* Return : None
|
733 |
|
|
*******************************************************************************/
|
734 |
|
|
void TIM_ForcedOCConfig(TIM_TypeDef* TIMx, u16 TIM_Channel,u16 TIM_ForcedAction)
|
735 |
|
|
{
|
736 |
|
|
/* Channel 1 Forced Output Compare mode configuration */
|
737 |
|
|
if(TIM_Channel == TIM_Channel_1)
|
738 |
|
|
{
|
739 |
|
|
TIMx->OMR1 &= TIM_OC1C_Mask;
|
740 |
|
|
TIMx->OMR1 |= TIM_ForcedAction;
|
741 |
|
|
}
|
742 |
|
|
/* Channel 2 Forced Output Compare mode configuration */
|
743 |
|
|
else
|
744 |
|
|
{
|
745 |
|
|
if(TIM_Channel == TIM_Channel_2)
|
746 |
|
|
{
|
747 |
|
|
TIMx->OMR1 &= TIM_OC2C_Mask;
|
748 |
|
|
TIMx->OMR1 |= (TIM_ForcedAction<<8);
|
749 |
|
|
}
|
750 |
|
|
/* Channel 1 and Channel 2 Forced Output Compare mode configuration */
|
751 |
|
|
else
|
752 |
|
|
{
|
753 |
|
|
TIMx->OMR1 &= TIM_OC1C_Mask & TIM_OC2C_Mask;
|
754 |
|
|
TIMx->OMR1 |= TIM_ForcedAction |(TIM_ForcedAction<<8);
|
755 |
|
|
}
|
756 |
|
|
}
|
757 |
|
|
}
|
758 |
|
|
|
759 |
|
|
/*******************************************************************************
|
760 |
|
|
* Function Name : TIM_ResetCounter
|
761 |
|
|
* Description : Re-intializes the TIM counter and generates an update of the
|
762 |
|
|
* registers.
|
763 |
|
|
* Input : TIMx: where x can be 0, 1 or 2 to select the TIM peripheral
|
764 |
|
|
* Output : None
|
765 |
|
|
* Return : None
|
766 |
|
|
*******************************************************************************/
|
767 |
|
|
void TIM_ResetCounter(TIM_TypeDef* TIMx)
|
768 |
|
|
{
|
769 |
|
|
/* Re-intialize the TIM counter */
|
770 |
|
|
TIMx->CR |= TIM_COUNTER_Reset;
|
771 |
|
|
}
|
772 |
|
|
|
773 |
|
|
/*******************************************************************************
|
774 |
|
|
* Function Name : TIM_SynchroConfig
|
775 |
|
|
* Description : Synchronizes two Timers in a specified mode.
|
776 |
|
|
* Input : - Master: specifies the peripheral master.
|
777 |
|
|
* This parameter can be one of the following values:
|
778 |
|
|
* PWM_Master, TIM0_Master, TIM1_Master or TIM2_Master.
|
779 |
|
|
* - Slave: specifies the peripheral slave.
|
780 |
|
|
* This parameter can be one of the following values:
|
781 |
|
|
* PWM_Slave, TIM0_Slave, TIM1_Slave or TIM2_Slave.
|
782 |
|
|
* - TIM_SynchroAction: specifies the synchronization Action to
|
783 |
|
|
* be used.
|
784 |
|
|
* This parameter can be one of the following values:
|
785 |
|
|
* - TIM_SynchroAction_Enable: The CNT_EN bit is used as TRGO
|
786 |
|
|
* - TIM_SynchroAction_Update: The Update event is used as TRGO
|
787 |
|
|
* - TIM_SynchroAction_Reset: The CNT_RST bit is used as TRGO
|
788 |
|
|
* - TIM_SynchroAction_OC: The OC1 signal is used as TRGO
|
789 |
|
|
* - TIM_SynchroMode: specifies the synchronization Mode to be used.
|
790 |
|
|
* This parameter can be one of the following values:
|
791 |
|
|
* - TIM_SynchroMode_Gated: Both start and stop of the
|
792 |
|
|
* counter is controlled.
|
793 |
|
|
* - TIM_SynchroMode_Trigger: Only the start of the
|
794 |
|
|
* counter is controlled.
|
795 |
|
|
* - TIM_SynchroMode_External: The rising edge of selected trigger
|
796 |
|
|
* clocks the counter.
|
797 |
|
|
* - TIM_SynchroMode_Reset: The rising edge of the selected trigger
|
798 |
|
|
* signal resets the counter and generates an update of the registers.
|
799 |
|
|
* Output : None
|
800 |
|
|
* Return : None
|
801 |
|
|
*******************************************************************************/
|
802 |
|
|
void TIM_SynchroConfig(Master_TypeDef Master, Slave_TypeDef Slave,
|
803 |
|
|
u16 TIM_SynchroAction, u16 TIM_SynchroMode)
|
804 |
|
|
{
|
805 |
|
|
switch (Slave)
|
806 |
|
|
{
|
807 |
|
|
case PWM_Slave:
|
808 |
|
|
{
|
809 |
|
|
PWM->SCR &= TIM_SME_Reset & TIM_TriggerSelection_Mask & TIM_SlaveModeSelection_Mask &
|
810 |
|
|
TIM_InternalTriggerSelection_Mask;
|
811 |
|
|
PWM->SCR |= TIM_SynchroMode | TIM_SME_Set;
|
812 |
|
|
|
813 |
|
|
if(Master == TIM1_Master)
|
814 |
|
|
{
|
815 |
|
|
/* Set the internal trigger */
|
816 |
|
|
PWM->SCR |= TIM_ITS_TIM1;
|
817 |
|
|
|
818 |
|
|
/* Set the synchronization action */
|
819 |
|
|
TIM1->CR &= TIM_MasterModeSelection_Mask;
|
820 |
|
|
TIM1->CR |= TIM_SynchroAction;
|
821 |
|
|
}
|
822 |
|
|
|
823 |
|
|
else if(Master == TIM0_Master)
|
824 |
|
|
{
|
825 |
|
|
/* Set the internal trigger */
|
826 |
|
|
PWM->SCR |= TIM_ITS_TIM0;
|
827 |
|
|
|
828 |
|
|
/* Set the synchronization action */
|
829 |
|
|
TIM0->CR &= TIM_MasterModeSelection_Mask;
|
830 |
|
|
TIM0->CR |= TIM_SynchroAction;
|
831 |
|
|
}
|
832 |
|
|
|
833 |
|
|
else if(Master == TIM2_Master)
|
834 |
|
|
{
|
835 |
|
|
/* Set the internal trigger */
|
836 |
|
|
PWM->SCR |= TIM_ITS_TIM2;
|
837 |
|
|
|
838 |
|
|
/* Set the synchronization action */
|
839 |
|
|
TIM2->CR &= TIM_MasterModeSelection_Mask;
|
840 |
|
|
TIM2->CR |= TIM_SynchroAction;
|
841 |
|
|
}
|
842 |
|
|
}
|
843 |
|
|
break;
|
844 |
|
|
|
845 |
|
|
case TIM0_Slave:
|
846 |
|
|
{
|
847 |
|
|
TIM0->SCR &= TIM_SME_Reset & TIM_TriggerSelection_Mask & TIM_SlaveModeSelection_Mask &
|
848 |
|
|
TIM_InternalTriggerSelection_Mask;
|
849 |
|
|
TIM0->SCR |= TIM_SynchroMode | TIM_SME_Set;
|
850 |
|
|
|
851 |
|
|
if(Master == PWM_Master)
|
852 |
|
|
{
|
853 |
|
|
/* Set the internal trigger */
|
854 |
|
|
TIM0->SCR |= TIM_ITS_PWM;
|
855 |
|
|
|
856 |
|
|
/* Set the synchronization action */
|
857 |
|
|
PWM->CR &= TIM_MasterModeSelection_Mask;
|
858 |
|
|
PWM->CR |= TIM_SynchroAction;
|
859 |
|
|
}
|
860 |
|
|
|
861 |
|
|
else if(Master == TIM1_Master)
|
862 |
|
|
{
|
863 |
|
|
/* Set the internal trigger */
|
864 |
|
|
TIM0->SCR |= TIM_ITS_TIM1;
|
865 |
|
|
|
866 |
|
|
/* Set the synchronization action */
|
867 |
|
|
TIM1->CR &= TIM_MasterModeSelection_Mask;
|
868 |
|
|
TIM1->CR |= TIM_SynchroAction;
|
869 |
|
|
}
|
870 |
|
|
|
871 |
|
|
else if(Master == TIM2_Master)
|
872 |
|
|
{
|
873 |
|
|
/* Set the internal trigger */
|
874 |
|
|
TIM0->SCR |= TIM_ITS_TIM2;
|
875 |
|
|
|
876 |
|
|
/* Set the synchronization action */
|
877 |
|
|
TIM2->CR &= TIM_MasterModeSelection_Mask;
|
878 |
|
|
TIM2->CR |= TIM_SynchroAction;
|
879 |
|
|
}
|
880 |
|
|
}
|
881 |
|
|
break;
|
882 |
|
|
|
883 |
|
|
case TIM1_Slave:
|
884 |
|
|
{
|
885 |
|
|
|
886 |
|
|
TIM1->SCR &= TIM_SME_Reset & TIM_TriggerSelection_Mask & TIM_SlaveModeSelection_Mask &
|
887 |
|
|
TIM_InternalTriggerSelection_Mask;
|
888 |
|
|
TIM1->SCR |= TIM_SynchroMode | TIM_SME_Set;
|
889 |
|
|
|
890 |
|
|
if(Master == PWM_Master)
|
891 |
|
|
{
|
892 |
|
|
/* Set the internal trigger */
|
893 |
|
|
TIM1->SCR |= TIM_ITS_PWM;
|
894 |
|
|
|
895 |
|
|
/* Set the synchronization action */
|
896 |
|
|
PWM->CR &= TIM_MasterModeSelection_Mask;
|
897 |
|
|
PWM->CR |= TIM_SynchroAction;
|
898 |
|
|
}
|
899 |
|
|
else if(Master == TIM0_Master)
|
900 |
|
|
{
|
901 |
|
|
/* Set the internal trigger */
|
902 |
|
|
TIM1->SCR |= TIM_ITS_TIM0;
|
903 |
|
|
|
904 |
|
|
/* Set the synchronization action */
|
905 |
|
|
TIM0->CR &= TIM_MasterModeSelection_Mask;
|
906 |
|
|
TIM0->CR |= TIM_SynchroAction;
|
907 |
|
|
}
|
908 |
|
|
|
909 |
|
|
else if(Master == TIM2_Master)
|
910 |
|
|
{
|
911 |
|
|
/* Set the internal trigger */
|
912 |
|
|
TIM1->SCR |= TIM_ITS_TIM2;
|
913 |
|
|
|
914 |
|
|
/* Set the synchronization action */
|
915 |
|
|
TIM2->CR &= TIM_MasterModeSelection_Mask;
|
916 |
|
|
TIM2->CR |= TIM_SynchroAction;
|
917 |
|
|
}
|
918 |
|
|
}
|
919 |
|
|
break;
|
920 |
|
|
|
921 |
|
|
case TIM2_Slave:
|
922 |
|
|
{
|
923 |
|
|
|
924 |
|
|
TIM2->SCR &= TIM_SME_Reset & TIM_TriggerSelection_Mask & TIM_SlaveModeSelection_Mask &
|
925 |
|
|
TIM_InternalTriggerSelection_Mask;
|
926 |
|
|
TIM2->SCR |= TIM_SynchroMode | TIM_SME_Set;
|
927 |
|
|
|
928 |
|
|
if(Master == PWM_Master)
|
929 |
|
|
{
|
930 |
|
|
/* Internal trigger selection */
|
931 |
|
|
TIM2->SCR |= TIM_ITS_PWM;
|
932 |
|
|
|
933 |
|
|
/* Set the synchronization action */
|
934 |
|
|
PWM->CR &= TIM_MasterModeSelection_Mask;
|
935 |
|
|
PWM->CR |= TIM_SynchroAction;
|
936 |
|
|
}
|
937 |
|
|
|
938 |
|
|
else if(Master == TIM1_Master)
|
939 |
|
|
{
|
940 |
|
|
/* Internal trigger selection */
|
941 |
|
|
TIM2->SCR |= TIM_ITS_TIM1;
|
942 |
|
|
|
943 |
|
|
/* Set the synchronization action */
|
944 |
|
|
TIM1->CR &= TIM_MasterModeSelection_Mask;
|
945 |
|
|
TIM1->CR |= TIM_SynchroAction;
|
946 |
|
|
}
|
947 |
|
|
|
948 |
|
|
else if(Master == TIM0_Master)
|
949 |
|
|
{
|
950 |
|
|
/* Internal trigger selection */
|
951 |
|
|
TIM2->SCR |= TIM_ITS_TIM0;
|
952 |
|
|
|
953 |
|
|
/* Set the synchronization action */
|
954 |
|
|
TIM0->CR &= TIM_MasterModeSelection_Mask;
|
955 |
|
|
TIM0->CR |= TIM_SynchroAction;
|
956 |
|
|
}
|
957 |
|
|
}
|
958 |
|
|
break;
|
959 |
|
|
|
960 |
|
|
default:
|
961 |
|
|
break;
|
962 |
|
|
}
|
963 |
|
|
}
|
964 |
|
|
|
965 |
|
|
/*******************************************************************************
|
966 |
|
|
* Function Name : TIM_GetFlagStatus
|
967 |
|
|
* Description : Checks whether the specified TIM flag is set or not.
|
968 |
|
|
* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral.
|
969 |
|
|
* - TIM_FLAG: specifies the flag to check.
|
970 |
|
|
* This parameter can be one of the following values:
|
971 |
|
|
* - TIM_FLAG_IC1: Input Capture 1 Flag
|
972 |
|
|
* - TIM_FLAG_OC1: Output Compare 1 Flag
|
973 |
|
|
* - TIM_FLAG_Update: Timer update Flag
|
974 |
|
|
* - TIM_FLAG_IC2: Input Capture 2 Flag
|
975 |
|
|
* - TIM_FLAG_OC2: Output Compare 2 Flag
|
976 |
|
|
* Output : None
|
977 |
|
|
* Return : The new state of TIM_FLAG (SET or RESET).
|
978 |
|
|
*******************************************************************************/
|
979 |
|
|
FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, u16 TIM_FLAG)
|
980 |
|
|
{
|
981 |
|
|
if((TIMx->ISR & TIM_FLAG) != RESET )
|
982 |
|
|
{
|
983 |
|
|
return SET;
|
984 |
|
|
}
|
985 |
|
|
else
|
986 |
|
|
{
|
987 |
|
|
return RESET;
|
988 |
|
|
}
|
989 |
|
|
}
|
990 |
|
|
|
991 |
|
|
/*******************************************************************************
|
992 |
|
|
* Function Name : TIM_ClearFlag
|
993 |
|
|
* Description : Clears the TIMx's pending flags.
|
994 |
|
|
* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral.
|
995 |
|
|
* - TIM_FLAG: specifies the flag bit to clear.
|
996 |
|
|
* This parameter can be any combination of the following values:
|
997 |
|
|
* - TIM_FLAG_IC1: Timer Input Capture 1 flag
|
998 |
|
|
* - TIM_FLAG_OC1: Timer Output Compare 1 flag
|
999 |
|
|
* - TIM_FLAG_Update: Timer update flag
|
1000 |
|
|
* - TIM_FLAG_IC2: Timer Input Capture 2 flag
|
1001 |
|
|
* - TIM_FLAG_OC2: Timer Output Compare 2 flag
|
1002 |
|
|
* Output : None
|
1003 |
|
|
* Return : None
|
1004 |
|
|
*******************************************************************************/
|
1005 |
|
|
void TIM_ClearFlag(TIM_TypeDef* TIMx, u16 TIM_FLAG)
|
1006 |
|
|
{
|
1007 |
|
|
/* Clear the flags */
|
1008 |
|
|
TIMx->ISR &= ~TIM_FLAG;
|
1009 |
|
|
}
|
1010 |
|
|
|
1011 |
|
|
/*******************************************************************************
|
1012 |
|
|
* Function Name : TIM_GetITStatus
|
1013 |
|
|
* Description : Checks whether the specified TIM interrupt has occurred or not.
|
1014 |
|
|
* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral.
|
1015 |
|
|
* - TIM_IT: specifies the TIM interrupt source to check.
|
1016 |
|
|
* This parameter can be one of the following values:
|
1017 |
|
|
* - TIM_IT_IC1: Input Capture 1 interrupt
|
1018 |
|
|
* - TIM_IT_OC1: Output Compare 1 interrupt
|
1019 |
|
|
* - TIM_IT_Update: Timer update interrupt
|
1020 |
|
|
* - TIM_IT_GlobalUpdate: Timer global update interrupt
|
1021 |
|
|
* - TIM_IT_IC2: Input Capture 2 interrupt
|
1022 |
|
|
* - TIM_IT_OC2: Output Compare 2 interrupt
|
1023 |
|
|
* Output : None
|
1024 |
|
|
* Return : The new state of TIM_IT(SET or RESET).
|
1025 |
|
|
*******************************************************************************/
|
1026 |
|
|
ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, u16 TIM_IT)
|
1027 |
|
|
{
|
1028 |
|
|
u16 TIM_IT_Check = 0;
|
1029 |
|
|
|
1030 |
|
|
/* Calculates the pending bits to be checked */
|
1031 |
|
|
TIM_IT_Check = TIM_IT & TIM_IT_Clear_Mask;
|
1032 |
|
|
|
1033 |
|
|
if((TIMx->ISR & TIM_IT_Check) != RESET )
|
1034 |
|
|
{
|
1035 |
|
|
return SET;
|
1036 |
|
|
}
|
1037 |
|
|
else
|
1038 |
|
|
{
|
1039 |
|
|
return RESET;
|
1040 |
|
|
}
|
1041 |
|
|
}
|
1042 |
|
|
|
1043 |
|
|
/*******************************************************************************
|
1044 |
|
|
* Function Name : TIM_ClearITPendingBit
|
1045 |
|
|
* Description : Clears the TIM's interrupt pending bits.
|
1046 |
|
|
* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral.
|
1047 |
|
|
* - TIM_IT: specifies the interrupt pending bit to clear.
|
1048 |
|
|
* This parameter can be one of the following values:
|
1049 |
|
|
* - TIM_IT_IC1: Input Capture 1 Interrupt
|
1050 |
|
|
* - TIM_IT_OC1: Output Compare 1 Interrupt
|
1051 |
|
|
* - TIM_IT_Update: Timer update Interrupt
|
1052 |
|
|
* - TIM_IT_GlobalUpdate: Timer global update Interrupt
|
1053 |
|
|
* - TIM_IT_IC2: Input Capture 2 Interrupt
|
1054 |
|
|
* - TIM_IT_OC2: Output Compare 2 Interrupt
|
1055 |
|
|
* Output : None
|
1056 |
|
|
* Return : None
|
1057 |
|
|
*******************************************************************************/
|
1058 |
|
|
void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, u16 TIM_IT)
|
1059 |
|
|
{
|
1060 |
|
|
u16 TIM_IT_Clear = 0;
|
1061 |
|
|
|
1062 |
|
|
/* Calculate the pending bits to be cleared */
|
1063 |
|
|
TIM_IT_Clear = TIM_IT & TIM_IT_Clear_Mask;
|
1064 |
|
|
|
1065 |
|
|
/* Clear the pending bits */
|
1066 |
|
|
TIMx->ISR &= ~TIM_IT_Clear;
|
1067 |
|
|
}
|
1068 |
|
|
|
1069 |
|
|
/*******************************************************************************
|
1070 |
|
|
* Function Name : OCM_ModuleConfig
|
1071 |
|
|
* Description : Output Compare Module configuration
|
1072 |
|
|
* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral
|
1073 |
|
|
* - TIM_InitStruct: pointer to a TIM_InitTypeDef structure that
|
1074 |
|
|
* contains the configuration information for the specified TIM
|
1075 |
|
|
* peripheral.
|
1076 |
|
|
* Output : None
|
1077 |
|
|
* Return : None
|
1078 |
|
|
*******************************************************************************/
|
1079 |
|
|
static void OCM_ModuleConfig(TIM_TypeDef* TIMx, TIM_InitTypeDef* TIM_InitStruct)
|
1080 |
|
|
{
|
1081 |
|
|
u16 TIM_OCControl = 0x0000;
|
1082 |
|
|
|
1083 |
|
|
if(TIM_InitStruct->TIM_Mode == TIM_Mode_OCTiming)
|
1084 |
|
|
{
|
1085 |
|
|
TIM_OCControl = TIM_OCControl_OCTiming;
|
1086 |
|
|
}
|
1087 |
|
|
else
|
1088 |
|
|
{
|
1089 |
|
|
if((TIM_InitStruct->TIM_Mode == TIM_Mode_OCActive) ||
|
1090 |
|
|
(TIM_InitStruct->TIM_Mode == TIM_Mode_OPM_Active))
|
1091 |
|
|
{
|
1092 |
|
|
TIM_OCControl = TIM_OCControl_OCActive;
|
1093 |
|
|
}
|
1094 |
|
|
else
|
1095 |
|
|
{
|
1096 |
|
|
if(TIM_InitStruct->TIM_Mode == TIM_Mode_OCInactive)
|
1097 |
|
|
{
|
1098 |
|
|
TIM_OCControl = TIM_OCControl_OCInactive;
|
1099 |
|
|
}
|
1100 |
|
|
else
|
1101 |
|
|
{
|
1102 |
|
|
if((TIM_InitStruct->TIM_Mode == TIM_Mode_OCToggle) ||
|
1103 |
|
|
(TIM_InitStruct->TIM_Mode == TIM_Mode_OPM_Toggle))
|
1104 |
|
|
{
|
1105 |
|
|
TIM_OCControl = TIM_OCControl_OCToggle;
|
1106 |
|
|
}
|
1107 |
|
|
else
|
1108 |
|
|
{
|
1109 |
|
|
TIM_OCControl = TIM_OCControl_PWM;
|
1110 |
|
|
|
1111 |
|
|
}
|
1112 |
|
|
}
|
1113 |
|
|
}
|
1114 |
|
|
}
|
1115 |
|
|
|
1116 |
|
|
if(TIM_InitStruct->TIM_Channel == TIM_Channel_1)
|
1117 |
|
|
{
|
1118 |
|
|
/* Configure Channel 1 on Output Compare mode */
|
1119 |
|
|
TIMx->OMR1 &= TIM_OC1C_Mask;
|
1120 |
|
|
TIMx->OMR1 |= TIM_OCControl|TIM_OC1_Enable;
|
1121 |
|
|
TIMx->OMR1 |= TIM_PLD1_Set;
|
1122 |
|
|
TIMx->OCR1 = TIM_InitStruct->TIM_Pulse1;
|
1123 |
|
|
|
1124 |
|
|
/* Set the OC1 wave polarity */
|
1125 |
|
|
if(TIM_InitStruct->TIM_Polarity1 == TIM_Polarity1_Low)
|
1126 |
|
|
{
|
1127 |
|
|
TIMx->OMR1 |= TIM_OC1P_Set;
|
1128 |
|
|
}
|
1129 |
|
|
else
|
1130 |
|
|
{
|
1131 |
|
|
TIMx->OMR1 &= TIM_OC1P_Reset;
|
1132 |
|
|
}
|
1133 |
|
|
}
|
1134 |
|
|
else
|
1135 |
|
|
{
|
1136 |
|
|
if(TIM_InitStruct->TIM_Channel == TIM_Channel_2)
|
1137 |
|
|
{
|
1138 |
|
|
/* Configure Channel 2 on Output Compare mode */
|
1139 |
|
|
TIMx->OMR1 &= TIM_OC2C_Mask;
|
1140 |
|
|
TIMx->OMR1 |= TIM_OCControl<<8|TIM_OC2_Enable;
|
1141 |
|
|
TIMx->OMR1 |= TIM_PLD2_Set;
|
1142 |
|
|
TIMx->OCR2 = TIM_InitStruct->TIM_Pulse2;
|
1143 |
|
|
|
1144 |
|
|
/* Set the OCB wave polarity */
|
1145 |
|
|
if(TIM_InitStruct->TIM_Polarity2 == TIM_Polarity2_Low)
|
1146 |
|
|
{
|
1147 |
|
|
TIMx->OMR1 |= TIM_OC2P_Set;
|
1148 |
|
|
}
|
1149 |
|
|
else
|
1150 |
|
|
{
|
1151 |
|
|
TIMx->OMR1 &= TIM_OC2P_Reset;
|
1152 |
|
|
}
|
1153 |
|
|
}
|
1154 |
|
|
/* Configure Channel 1 and Channel 2 on Output Compare mode */
|
1155 |
|
|
else
|
1156 |
|
|
{
|
1157 |
|
|
TIMx->OMR1 &= TIM_OC1C_Mask & TIM_OC2C_Mask;
|
1158 |
|
|
TIMx->OMR1 |= TIM_OCControl|(TIM_OCControl<<8)|TIM_OC1_Enable|TIM_OC2_Enable|
|
1159 |
|
|
TIM_PLD1_Set|TIM_PLD2_Set;
|
1160 |
|
|
|
1161 |
|
|
TIMx->OCR1 = TIM_InitStruct->TIM_Pulse1;
|
1162 |
|
|
TIMx->OCR2 = TIM_InitStruct->TIM_Pulse2;
|
1163 |
|
|
|
1164 |
|
|
/* Set the OC1 wave polarity */
|
1165 |
|
|
if(TIM_InitStruct->TIM_Polarity1 == TIM_Polarity1_Low)
|
1166 |
|
|
{
|
1167 |
|
|
TIMx->OMR1 |= TIM_OC1P_Set;
|
1168 |
|
|
}
|
1169 |
|
|
else
|
1170 |
|
|
{
|
1171 |
|
|
TIMx->OMR1 &= TIM_OC1P_Reset;
|
1172 |
|
|
}
|
1173 |
|
|
|
1174 |
|
|
/* Set the OC2 wave polarity */
|
1175 |
|
|
if(TIM_InitStruct->TIM_Polarity2 == TIM_Polarity2_Low)
|
1176 |
|
|
{
|
1177 |
|
|
TIMx->OMR1 |= TIM_OC2P_Set;
|
1178 |
|
|
}
|
1179 |
|
|
else
|
1180 |
|
|
{
|
1181 |
|
|
TIMx->OMR1 &= TIM_OC2P_Reset;
|
1182 |
|
|
}
|
1183 |
|
|
}
|
1184 |
|
|
}
|
1185 |
|
|
}
|
1186 |
|
|
|
1187 |
|
|
/*******************************************************************************
|
1188 |
|
|
* Function Name : ICAP_ModuleConfig
|
1189 |
|
|
* Description : Input Capture Module configuration
|
1190 |
|
|
* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral
|
1191 |
|
|
* - TIM_InitStruct: pointer to a TIM_InitTypeDef structure that
|
1192 |
|
|
* contains the configuration information for the specified TIM
|
1193 |
|
|
* peripheral.
|
1194 |
|
|
* Output : None
|
1195 |
|
|
* Return : None
|
1196 |
|
|
*******************************************************************************/
|
1197 |
|
|
static void ICAP_ModuleConfig(TIM_TypeDef* TIMx, TIM_InitTypeDef* TIM_InitStruct)
|
1198 |
|
|
{
|
1199 |
|
|
if(TIM_InitStruct->TIM_Mode == TIM_Mode_PWMI)
|
1200 |
|
|
{ /* PWM input mode configuration */
|
1201 |
|
|
TIMx->SCR |= TIM_TS_IC1_Set|TIM_SMS_RESETCLK_Set|TIM_SME_Set;
|
1202 |
|
|
|
1203 |
|
|
/* Channel 1 and channel 2 input selection */
|
1204 |
|
|
if(TIM_InitStruct->TIM_PWMI_ICSelection == TIM_PWMI_ICSelection_TI1)
|
1205 |
|
|
{
|
1206 |
|
|
TIMx->IMCR &= TIM_IC1S_Reset;
|
1207 |
|
|
TIMx->IMCR |= TIM_IC2S_Set;
|
1208 |
|
|
}
|
1209 |
|
|
else
|
1210 |
|
|
{
|
1211 |
|
|
TIMx->IMCR |= TIM_IC1S_Set;
|
1212 |
|
|
TIMx->IMCR &= TIM_IC2S_Reset;
|
1213 |
|
|
}
|
1214 |
|
|
|
1215 |
|
|
/* Channel polarity */
|
1216 |
|
|
if(TIM_InitStruct->TIM_PWMI_ICPolarity == TIM_PWMI_ICPolarity_Rising)
|
1217 |
|
|
{
|
1218 |
|
|
TIMx->IMCR &= TIM_IC1P_Reset;
|
1219 |
|
|
TIMx->IMCR |= TIM_IC2P_Set;
|
1220 |
|
|
}
|
1221 |
|
|
else
|
1222 |
|
|
{
|
1223 |
|
|
TIMx->IMCR |= TIM_IC1P_Set;
|
1224 |
|
|
TIMx->IMCR &= TIM_IC2P_Reset;
|
1225 |
|
|
}
|
1226 |
|
|
|
1227 |
|
|
/* Input capture Enable */
|
1228 |
|
|
TIMx->IMCR |= TIM_IC1_Enable |TIM_IC2_Enable;
|
1229 |
|
|
}
|
1230 |
|
|
else
|
1231 |
|
|
{
|
1232 |
|
|
if(TIM_InitStruct->TIM_Channel == TIM_Channel_1)
|
1233 |
|
|
{
|
1234 |
|
|
/* Input Capture 1 mode configuration */
|
1235 |
|
|
TIMx->SCR &= TIM_TriggerSelection_Mask & TIM_SlaveModeSelection_Mask;
|
1236 |
|
|
TIMx->SCR |= TIM_TS_IC1_Set|TIM_SMS_RESETCLK_Set|TIM_SME_Set;
|
1237 |
|
|
|
1238 |
|
|
/* Channel 1 input selection */
|
1239 |
|
|
if(TIM_InitStruct->TIM_IC1Selection == TIM_IC1Selection_TI1)
|
1240 |
|
|
{
|
1241 |
|
|
TIMx->IMCR &= TIM_IC1S_Reset;
|
1242 |
|
|
}
|
1243 |
|
|
else
|
1244 |
|
|
{
|
1245 |
|
|
TIMx->IMCR |= TIM_IC1S_Set;
|
1246 |
|
|
}
|
1247 |
|
|
/* Channel 1 polarity */
|
1248 |
|
|
if(TIM_InitStruct->TIM_IC1Polarity == TIM_IC1Polarity_Rising)
|
1249 |
|
|
{
|
1250 |
|
|
TIMx->IMCR &= TIM_IC1P_Reset;
|
1251 |
|
|
}
|
1252 |
|
|
else
|
1253 |
|
|
{
|
1254 |
|
|
TIMx->IMCR |= TIM_IC1P_Set;
|
1255 |
|
|
}
|
1256 |
|
|
|
1257 |
|
|
/* Input capture Enable */
|
1258 |
|
|
TIMx->IMCR |= TIM_IC1_Enable;
|
1259 |
|
|
}
|
1260 |
|
|
else
|
1261 |
|
|
{
|
1262 |
|
|
/* Input Capture 2 mode configuration */
|
1263 |
|
|
TIMx->SCR &= (TIM_TriggerSelection_Mask & TIM_SlaveModeSelection_Mask);
|
1264 |
|
|
TIMx->SCR |= TIM_TS_IC2_Set|TIM_SMS_RESETCLK_Set|TIM_SME_Set;
|
1265 |
|
|
|
1266 |
|
|
/* Channel 2 input selection */
|
1267 |
|
|
if(TIM_InitStruct->TIM_IC2Selection == TIM_IC2Selection_TI2)
|
1268 |
|
|
{
|
1269 |
|
|
TIMx->IMCR &= TIM_IC2S_Reset;
|
1270 |
|
|
}
|
1271 |
|
|
else
|
1272 |
|
|
{
|
1273 |
|
|
TIMx->IMCR |= TIM_IC2S_Set;
|
1274 |
|
|
}
|
1275 |
|
|
|
1276 |
|
|
/* Channel 2 polarity */
|
1277 |
|
|
if(TIM_InitStruct->TIM_IC2Polarity == TIM_IC2Polarity_Rising)
|
1278 |
|
|
{
|
1279 |
|
|
TIMx->IMCR &= TIM_IC2P_Reset;
|
1280 |
|
|
}
|
1281 |
|
|
else
|
1282 |
|
|
{
|
1283 |
|
|
TIMx->IMCR |= TIM_IC2P_Set;
|
1284 |
|
|
}
|
1285 |
|
|
|
1286 |
|
|
/* Input capture Enable */
|
1287 |
|
|
TIMx->IMCR |= TIM_IC2_Enable;
|
1288 |
|
|
}
|
1289 |
|
|
}
|
1290 |
|
|
}
|
1291 |
|
|
|
1292 |
|
|
/*******************************************************************************
|
1293 |
|
|
* Function Name : Encoder_ModeConfig
|
1294 |
|
|
* Description : Encoder Mode configuration
|
1295 |
|
|
* Input : - TIMx: where x can be 0, 1 or 2 to select the TIM peripheral
|
1296 |
|
|
* - TIM_InitStruct: pointer to a TIM_InitTypeDef structure that
|
1297 |
|
|
* contains the configuration information for the specified TIM
|
1298 |
|
|
* peripheral.
|
1299 |
|
|
* Output : None
|
1300 |
|
|
* Return : None
|
1301 |
|
|
*******************************************************************************/
|
1302 |
|
|
static void Encoder_ModeConfig(TIM_TypeDef* TIMx, TIM_InitTypeDef* TIM_InitStruct)
|
1303 |
|
|
{
|
1304 |
|
|
/* Set Encoder mode */
|
1305 |
|
|
TIMx->SCR &= TIM_Encoder_Mask;
|
1306 |
|
|
|
1307 |
|
|
if(TIM_InitStruct->TIM_Mode == TIM_Mode_Encoder1)
|
1308 |
|
|
{
|
1309 |
|
|
TIMx->SCR |= TIM_Encoder1_Set;
|
1310 |
|
|
}
|
1311 |
|
|
else if (TIM_InitStruct->TIM_Mode == TIM_Mode_Encoder2)
|
1312 |
|
|
{
|
1313 |
|
|
TIMx->SCR |= TIM_Encoder2_Set;
|
1314 |
|
|
}
|
1315 |
|
|
else
|
1316 |
|
|
{
|
1317 |
|
|
TIMx->SCR |= TIM_Encoder3_Set;
|
1318 |
|
|
}
|
1319 |
|
|
|
1320 |
|
|
/* Channel 1 input selection */
|
1321 |
|
|
if(TIM_InitStruct->TIM_IC1Selection == TIM_IC1Selection_TI2)
|
1322 |
|
|
{
|
1323 |
|
|
TIMx->IMCR |= TIM_IC1S_Set;
|
1324 |
|
|
}
|
1325 |
|
|
else
|
1326 |
|
|
{
|
1327 |
|
|
TIMx->IMCR &= TIM_IC1S_Reset;
|
1328 |
|
|
}
|
1329 |
|
|
|
1330 |
|
|
/* Channel 2 input selection */
|
1331 |
|
|
if(TIM_InitStruct->TIM_IC2Selection == TIM_IC2Selection_TI1)
|
1332 |
|
|
{
|
1333 |
|
|
TIMx->IMCR |= TIM_IC2S_Set;
|
1334 |
|
|
}
|
1335 |
|
|
else
|
1336 |
|
|
{
|
1337 |
|
|
TIMx->IMCR &= TIM_IC2S_Reset;
|
1338 |
|
|
}
|
1339 |
|
|
|
1340 |
|
|
/* Channel 1 polarity */
|
1341 |
|
|
if(TIM_InitStruct->TIM_IC1Polarity == TIM_IC1Polarity_Falling)
|
1342 |
|
|
{
|
1343 |
|
|
TIMx->IMCR |= TIM_IC1P_Set;
|
1344 |
|
|
}
|
1345 |
|
|
else
|
1346 |
|
|
{
|
1347 |
|
|
TIMx->IMCR &= TIM_IC1P_Reset;
|
1348 |
|
|
}
|
1349 |
|
|
|
1350 |
|
|
/* Channel 2 polarity */
|
1351 |
|
|
if(TIM_InitStruct->TIM_IC2Polarity == TIM_IC2Polarity_Falling)
|
1352 |
|
|
{
|
1353 |
|
|
TIMx->IMCR |= TIM_IC2P_Set;
|
1354 |
|
|
}
|
1355 |
|
|
else
|
1356 |
|
|
{
|
1357 |
|
|
TIMx->IMCR &= TIM_IC2P_Reset;
|
1358 |
|
|
}
|
1359 |
|
|
}
|
1360 |
|
|
/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/
|