OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [ARM7_STR75x_GCC/] [SystemFiles/] [STR75x_COMMON_FreeRTOS.ld] - Blame information for rev 860

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 577 jeremybenn
/*
2
Common part of the linker scripts for STR75x devices
3
Copyright RAISONANCE 2006
4
You can use, modify and distribute this file freely, but without any waranty.
5
*/
6
 
7
 
8
/* Registers mapping */
9
FLASHR_BASE     = 0x20100000 ;
10
FLASHPR_BASE    = 0x2010DFB0 ;
11
CFG_BASE        = 0x60000000 ;
12
MRCC_BASE       = 0x60000020 ;
13
EXTMEM_BASE     = 0x80000000 ;
14
SMI_BASE        = 0x90000000 ;
15
DMA_BASE        = 0xFFFFEC00 ;
16
EIC_BASE        = 0xFFFFF800 ;
17
APB_BASE        = 0xFFFF8000 ;
18
 
19
PROVIDE( _MRCC  =  MRCC_BASE );
20
PROVIDE( _CFG   =  CFG_BASE  );
21
PROVIDE( _SMI   =  SMI_BASE  );
22
PROVIDE( _DMA   =  DMA_BASE  );
23
PROVIDE( _EIC   =  EIC_BASE  );
24
 
25
PROVIDE( _ADC   = (APB_BASE + 0x0400) );
26
PROVIDE( _TB    = (APB_BASE + 0x0800) );
27
PROVIDE( _TIM0  = (APB_BASE + 0x0C00) );
28
PROVIDE( _TIM1  = (APB_BASE + 0x1000) );
29
PROVIDE( _TIM2  = (APB_BASE + 0x1400) );
30
PROVIDE( _PWM   = (APB_BASE + 0x1800) );
31
PROVIDE( _USB   = (APB_BASE + 0x2800) ); /* USB registers */
32
PROVIDE( _WDG   = (APB_BASE + 0x3000) );
33
PROVIDE( _SSP0  = (APB_BASE + 0x3800) );
34
PROVIDE( _SSP1  = (APB_BASE + 0x3C00) );
35
PROVIDE( _CAN   = (APB_BASE + 0x4400) );
36
PROVIDE( _I2C   = (APB_BASE + 0x4C00) );
37
PROVIDE( _UART0 = (APB_BASE + 0x5400) );
38
PROVIDE( _UART1 = (APB_BASE + 0x5800) );
39
PROVIDE( _UART2 = (APB_BASE + 0x5C00) );
40
PROVIDE( _GPIO0 = (APB_BASE + 0x6400) );
41
PROVIDE( _GPIO1 = (APB_BASE + 0x6440) );
42
PROVIDE( _GPIO2 = (APB_BASE + 0x6480) );
43
PROVIDE( _RTC   = (APB_BASE + 0x7000) );
44
PROVIDE( _EXTIT = (APB_BASE + 0x7400) );
45
 
46
/* default stack sizes.
47
 
48
These are used by the startup in order to allocate stacks for the different modes.
49
*/
50
 
51
__SVC_Stack_Size = 400 ;
52
__IRQ_Stack_Size = 400 ;
53
__USR_Stack_Size = 4 ;
54
__FIQ_Stack_Size = 4 ;
55
__ABT_Stack_Size = 0 ;
56
__UND_Stack_Size = 0 ;
57
 
58
__SVC_Stack_Init = _estack ;
59
__IRQ_Stack_Init = __SVC_Stack_Init - __SVC_Stack_Size ;
60
__USR_Stack_Init = __IRQ_Stack_Init - __IRQ_Stack_Size ;
61
__FIQ_Stack_Init = __USR_Stack_Init - __USR_Stack_Size ;
62
__ABT_Stack_Init = __FIQ_Stack_Init - __FIQ_Stack_Size ;
63
__UND_Stack_Init = __ABT_Stack_Init - __ABT_Stack_Size ;
64
 
65
/*"PROVIDE" allows to easily override these values from an object file or the commmand line.*/
66
PROVIDE ( _SVC_Stack_Init = __SVC_Stack_Init ) ;
67
PROVIDE ( _IRQ_Stack_Init = __IRQ_Stack_Init ) ;
68
PROVIDE ( _USR_Stack_Init = __USR_Stack_Init ) ;
69
PROVIDE ( _FIQ_Stack_Init = __FIQ_Stack_Init ) ;
70
PROVIDE ( _ABT_Stack_Init = __ABT_Stack_Init ) ;
71
PROVIDE ( _UND_Stack_Init = __UND_Stack_Init ) ;
72
 
73
/*
74
the user mode stack is an exception because we want it at the end of the RAM.
75
therefore, we just check against a minimum.
76
The value below is the minimum memory required for ALL THE STACKS.
77
There will be a link error if there is not this amount of RAM free at the end.
78
*/
79
_Minimum_Stack_Size = 0xC00 ;
80
 
81
 
82
 
83
/* default ISR addresses.
84
 
85
The startup needs these addresses defined from another object file.
86
In case they are not, these PROVIDEs redirect them to the Reset.
87
 
88
_start must be defined, usually in the startup.
89
*/
90
 
91
PROVIDE( SWI_Handler = _start );
92
PROVIDE( Undefined_Handler = _start );
93
PROVIDE( Prefetch_Handler = _start );
94
PROVIDE( Abort_Handler = _start );
95
PROVIDE( IRQ_Handler = _start ); /* <-- needed ? */
96
PROVIDE( FIQ_Handler = _start );
97
PROVIDE( WAKUP_IRQHandler = _start );
98
PROVIDE( TIM2_OC2_IRQHandler = _start );
99
PROVIDE( TIM2_OC1_IRQHandler = _start );
100
PROVIDE( TIM2_IC12_IRQHandler = _start );
101
PROVIDE( TIM2_UP_IRQHandler = _start );
102
PROVIDE( TIM1_OC2_IRQHandler = _start );
103
PROVIDE( TIM1_OC1_IRQHandler = _start );
104
PROVIDE( TIM1_IC12_IRQHandler = _start );
105
PROVIDE( TIM1_UP_IRQHandler = _start );
106
PROVIDE( TIM0_OC2_IRQHandler = _start );
107
PROVIDE( TIM0_OC1_IRQHandler = _start );
108
PROVIDE( TIM0_IC12_IRQHandler = _start );
109
PROVIDE( TIM0_UP_IRQHandler = _start );
110
PROVIDE( PWM_OC123_IRQHandler = _start );
111
PROVIDE( PWM_EM_IRQHandler = _start );
112
PROVIDE( PWM_UP_IRQHandler = _start );
113
PROVIDE( I2C_IRQHandler = _start );
114
PROVIDE( SSP1_IRQHandler = _start );
115
PROVIDE( SSP0_IRQHandler = _start );
116
PROVIDE( UART2_IRQHandler = _start );
117
PROVIDE( UART1_IRQHandler = _start );
118
PROVIDE( UART0_IRQHandler = _start );
119
PROVIDE( CAN_IRQHandler = _start );
120
PROVIDE( USB_LPI_RQHandler = _start );
121
PROVIDE( USB_HP_IRQHandler = _start );
122
PROVIDE( ADC_IRQHandler = _start );
123
PROVIDE( DMA_IRQHandler = _start );
124
PROVIDE( EXTIT_IRQHandler = _start );
125
PROVIDE( MRCC_IRQHandler = _start );
126
PROVIDE( FLASHSMI_IRQHandler = _start );
127
PROVIDE( RTC_IRQHandler = _start );
128
PROVIDE( TB_IRQHandler = _start );
129
PROVIDE( USB_LP_IRQHandler = _start );
130
PROVIDE( USB_HP_IRQHandler = _start );

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.