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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [ARM7_STR75x_IAR/] [STLibrary/] [src/] [75x_dma.c] - Blame information for rev 615

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1 577 jeremybenn
/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
2
* File Name          : 75x_dma.c
3
* Author             : MCD Application Team
4
* Date First Issued  : 03/10/2006
5
* Description        : This file provides all the DMA software functions.
6
********************************************************************************
7
* History:
8
* 07/17/2006 : V1.0
9
* 03/10/2006 : V0.1
10
********************************************************************************
11
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
12
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
13
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
14
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
15
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
16
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
17
*******************************************************************************/
18
 
19
/* Includes ------------------------------------------------------------------*/
20
#include "75x_dma.h"
21
#include "75x_mrcc.h"
22
 
23
/* Private typedef -----------------------------------------------------------*/
24
/* Private define ------------------------------------------------------------*/
25
/* Private macro -------------------------------------------------------------*/
26
/* Private variables ---------------------------------------------------------*/
27
 
28
/* DMA enable */
29
#define DMA_Enable     0x0001
30
#define DMA_Disable    0xFFFE
31
 
32
/* DMA Last Buffer Sweep */
33
#define DMA_Last0_Enable_Mask    0x0001
34
#define DMA_Last0_Disable_Mask   0xFFFE
35
#define DMA_Last1_Enable_Mask    0x0002
36
#define DMA_Last1_Disable_Mask   0xFFFD
37
#define DMA_Last2_Enable_Mask    0x0004
38
#define DMA_Last2_Disable_Mask   0xFFFB
39
#define DMA_Last3_Enable_Mask    0x0008
40
#define DMA_Last3_Disable_Mask   0xFFF7
41
 
42
/* DMA Masks */
43
#define DMA_Stream0_MASK_Mask  0xFFEE
44
#define DMA_Stream0_CLR_Mask   0x0011
45
#define DMA_Stream0_LAST_Mask  0xFFFE
46
 
47
#define DMA_Stream1_MASK_Mask  0xFFDD
48
#define DMA_Stream1_CLR_Mask   0x0022
49
#define DMA_Stream1_LAST_Mask  0xFFFD
50
 
51
#define DMA_Stream2_MASK_Mask  0xFFBB
52
#define DMA_Stream2_CLR_Mask   0x0044
53
#define DMA_Stream2_LAST_Mask  0xFFFB
54
 
55
#define DMA_Stream3_MASK_Mask  0xFF77
56
#define DMA_Stream3_CLR_Mask   0x0088
57
#define DMA_Stream3_LAST_Mask  0xFFF7
58
 
59
#define DMA_SRCSize_Mask   0xFFE7
60
#define DMA_SRCBurst_Mask  0xFF9F
61
#define DMA_DSTSize_Mask   0xFE7F     
62
 
63
/* Private function prototypes -----------------------------------------------*/
64
/* Private functions ---------------------------------------------------------*/
65
/*******************************************************************************
66
* Function Name  : DMA_DeInit
67
* Description    : Deinitializes the DMA streamx registers to their default reset
68
*                  values.
69
* Input          : - DMA_Streamx: where x can be 0, 1, 2 or 3 to select the DMA
70
*                    Stream.
71
* Output         : None
72
* Return         : None
73
*******************************************************************************/
74
void DMA_DeInit(DMA_Stream_TypeDef* DMA_Streamx)
75
{
76
  /* Reset streamx source base address register */
77
  DMA_Streamx->SOURCEL = 0;
78
  DMA_Streamx->SOURCEH = 0;
79
 
80
  /* Reset streamx destination base address register */
81
  DMA_Streamx->DESTL = 0;
82
  DMA_Streamx->DESTH = 0;
83
 
84
  /* Reset streamx maximum count register */
85
  DMA_Streamx->MAX  = 0;
86
  /* Reset streamx control register */
87
  DMA_Streamx->CTRL = 0;
88
  /* Reset streamx last used buffer location register */
89
  DMA_Streamx->LUBUFF = 0;
90
 
91
  switch(*(u32*)&DMA_Streamx)
92
  {
93
    case DMA_Stream0_BASE:
94
      /* Reset interrupt mask, clear and flag bits for stream0 */
95
      DMA->MASK &= DMA_Stream0_MASK_Mask;
96
      DMA->CLR |= DMA_Stream0_CLR_Mask;
97
      DMA->LAST &= DMA_Stream0_LAST_Mask;
98
      break;
99
 
100
    case DMA_Stream1_BASE:
101
      /* Reset interrupt mask, clear and flag bits for stream1 */
102
      DMA->MASK &= DMA_Stream1_MASK_Mask;
103
      DMA->CLR |= DMA_Stream1_CLR_Mask;
104
      DMA->LAST &= DMA_Stream1_LAST_Mask;
105
      break;
106
 
107
    case DMA_Stream2_BASE:
108
    /* Reset interrupt mask, clear and flag bits for stream2 */
109
      DMA->MASK &= DMA_Stream2_MASK_Mask;
110
      DMA->CLR |= DMA_Stream2_CLR_Mask;
111
      DMA->LAST &= DMA_Stream2_LAST_Mask;
112
      break;
113
 
114
    case DMA_Stream3_BASE:
115
      /* Reset interrupt mask, clear and flag bits for stream3 */
116
      DMA->MASK &= DMA_Stream3_MASK_Mask;
117
      DMA->CLR |= DMA_Stream3_CLR_Mask;
118
      DMA->LAST &= DMA_Stream3_LAST_Mask;
119
      break;
120
 
121
    default:
122
      break;
123
  }
124
}
125
 
126
/*******************************************************************************
127
* Function Name  : DMA_Init
128
* Description    : Initializes the DMAx stream according to the specified
129
*                  parameters in the DMA_InitStruct.
130
* Input          : - DMA_Streamx: where x can be 0, 1, 2 or 3 to select the DMA
131
*                    Stream.
132
*                  - DMA_InitStruct: pointer to a DMA_InitTypeDef structure that
133
*                    contains the configuration information for the specified
134
*                    DMA stream.
135
* Output         : None
136
* Return         : None
137
******************************************************************************/
138
void DMA_Init(DMA_Stream_TypeDef*  DMA_Streamx, DMA_InitTypeDef* DMA_InitStruct)
139
{
140
  /* set the buffer Size */
141
   DMA_Streamx->MAX = DMA_InitStruct->DMA_BufferSize ;
142
 
143
  /* Configure the incrementation of the current source Register */
144
  if(DMA_InitStruct->DMA_SRC == DMA_SRC_INCR)
145
  {
146
    /* Increment current source register */
147
    DMA_Streamx->CTRL |= DMA_SRC_INCR;
148
  }
149
  else
150
  {
151
    /* Current source register unchanged */
152
    DMA_Streamx->CTRL &= DMA_SRC_NOT_INCR;
153
  }
154
 
155
  /* Configure the incrementation of the current destination Register */
156
  if(DMA_InitStruct->DMA_DST == DMA_DST_INCR)
157
  {
158
    /* Increment current source register */
159
    DMA_Streamx->CTRL |= DMA_DST_INCR;
160
  }
161
  else
162
  {
163
    /* Current source register unchanged */
164
    DMA_Streamx->CTRL &= DMA_DST_NOT_INCR;
165
  }
166
 
167
  /* Clear source to DMA data width SOSIZE[1:0] bits */
168
  DMA_Streamx->CTRL &= DMA_SRCSize_Mask;
169
  /* Set the source to DMA data width */
170
  DMA_Streamx->CTRL |= DMA_InitStruct->DMA_SRCSize;
171
 
172
  /* Clear the DMA peripheral burst size SOBURST[1:0] bits */
173
  DMA_Streamx->CTRL &= DMA_SRCBurst_Mask;
174
  /* Set the DMA peripheral burst size */
175
  DMA_Streamx->CTRL |= DMA_InitStruct->DMA_SRCBurst;
176
 
177
  /* Clear destination to DMA dat width DESIZE[1:0] bits */
178
  DMA_Streamx->CTRL &= DMA_DSTSize_Mask;
179
  /* Set the destination to DMA data width */
180
  DMA_Streamx->CTRL |= DMA_InitStruct->DMA_DSTSize;
181
 
182
  /* Configure the circular mode */
183
  if(DMA_InitStruct->DMA_Mode == DMA_Mode_Circular)
184
  {
185
    /* Set circular mode */
186
    DMA_Streamx->CTRL |= DMA_Mode_Circular;
187
  }
188
  else
189
  {
190
    /* Set normal mode */
191
    DMA_Streamx->CTRL &= DMA_Mode_Normal;
192
  }
193
 
194
  /* Configure the direction transfer */
195
  if(DMA_InitStruct->DMA_DIR == DMA_DIR_PeriphDST)
196
  {
197
    /* Set peripheral as destination */
198
    DMA_Streamx->CTRL |= DMA_DIR_PeriphDST;
199
  }
200
  else
201
  {
202
    /* Set peripheral as source */
203
    DMA_Streamx->CTRL &= DMA_DIR_PeriphSRC;
204
  }
205
 
206
  /* Configure the memory to memory transfer only for stream3 */
207
  if(DMA_Streamx == DMA_Stream3)
208
  {
209
    if(DMA_InitStruct->DMA_M2M == DMA_M2M_Enable)
210
    {
211
      /* Enable memory to memory transfer for stream3 */
212
      DMA_Streamx->CTRL |= DMA_M2M_Enable;
213
    }
214
    else
215
    {
216
      /* Disable memory to memory transfer for stream3 */
217
      DMA_Streamx->CTRL &= DMA_M2M_Disable;
218
    }
219
  }
220
 
221
  /* Configure the source base address */
222
  DMA_Streamx->SOURCEL = DMA_InitStruct->DMA_SRCBaseAddr;
223
  DMA_Streamx->SOURCEH = DMA_InitStruct->DMA_SRCBaseAddr >> 16;
224
 
225
  /* Configure the destination base address */
226
  DMA_Streamx->DESTL = DMA_InitStruct->DMA_DSTBaseAddr;
227
  DMA_Streamx->DESTH = DMA_InitStruct->DMA_DSTBaseAddr >> 16;
228
}
229
 
230
/*******************************************************************************
231
* Function Name  : DMA_StructInit
232
* Description    : Fills each DMA_InitStruct member with its default value.
233
* Input          : DMA_InitStruct : pointer to a DMA_InitTypeDef structure
234
*                  which will be initialized.
235
* Output         : None
236
* Return         : None
237
*******************************************************************************/
238
void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)
239
{
240
  /* Initialize the DMA_BufferSize member */
241
  DMA_InitStruct->DMA_BufferSize = 0;
242
 
243
  /* initialize the DMA_SRCBaseAddr member */
244
  DMA_InitStruct->DMA_SRCBaseAddr = 0;
245
 
246
  /* Initialize the DMA_DSTBaseAddr member */
247
  DMA_InitStruct ->DMA_DSTBaseAddr = 0;
248
 
249
  /* Initialize the DMA_SRC member */
250
  DMA_InitStruct->DMA_SRC = DMA_SRC_NOT_INCR;
251
 
252
  /* Initialize the DMA_DST member */
253
  DMA_InitStruct->DMA_DST = DMA_DST_NOT_INCR;
254
 
255
  /* Initialize the DMA_SRCSize member */
256
  DMA_InitStruct->DMA_SRCSize = DMA_SRCSize_Byte;
257
 
258
  /* Initialize the DMA_SRCBurst member */
259
  DMA_InitStruct->DMA_SRCBurst = DMA_SRCBurst_1Data;
260
 
261
  /* Initialize the DMA_DSTSize member */
262
  DMA_InitStruct->DMA_DSTSize = DMA_DSTSize_Byte;
263
 
264
  /* Initialize the DMA_Mode member */
265
  DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
266
 
267
  /* Initialize the DMA_M2M member */
268
  DMA_InitStruct->DMA_M2M =  DMA_M2M_Disable;
269
 
270
  /* Initialize the DMA_DIR member */
271
  DMA_InitStruct->DMA_DIR = DMA_DIR_PeriphSRC;
272
}
273
 
274
/*******************************************************************************
275
* Function Name  : DMA_Cmd
276
* Description    : Enables or disables the specified DMA stream.
277
* Input          : - DMA_Streamx: where x can be 0, 1, 2 or 3 to select the DMA
278
*                    Stream.
279
*                  - NewState: new state of the DMAx stream. This parameter can
280
*                  be: ENABLE or DISABLE.
281
* Output         : None
282
* Return         : None
283
*******************************************************************************/
284
void DMA_Cmd(DMA_Stream_TypeDef*  DMA_Streamx, FunctionalState NewState)
285
{
286
  if(NewState == ENABLE)
287
  {
288
    /* Enable the selected DMA streamx */
289
    DMA_Streamx->CTRL |= DMA_Enable;
290
  }
291
  else
292
  {
293
    /* Disable the selected DMA streamx */
294
    DMA_Streamx->CTRL &= DMA_Disable;
295
  }
296
}
297
 
298
/*******************************************************************************
299
* Function Name  : DMA_ITConfig
300
* Description    : Enables or disables the specified DMA interrupts.
301
* Input          : - DMA_IT: specifies the DMA interrupts sources to be enabled
302
*                    or disabled. This parameter can be any combination of the
303
*                    following values:
304
*                         - DMA_IT_SI0: Stream0 transfer end interrupt mask
305
*                         - DMA_IT_SI1: Stream1 transfer end interrupt mask
306
*                         - DMA_IT_SI2: Stream2 transfer end interrupt mask
307
*                         - DMA_IT_SI3: Stream3 transfer end interrupt mask
308
*                         - DMA_IT_SE0: Stream0 transfer error interrupt mask
309
*                         - DMA_IT_SE1: Stream1 transfer error interrupt mask
310
*                         - DMA_IT_SE2: Stream2 transfer error interrupt mask
311
*                         - DMA_IT_SE3: Stream3 transfer error interrupt mask
312
*                         - DMA_IT_ALL: ALL DMA interrupts mask
313
*                  - NewState: new state of the specified DMA interrupts.
314
*                    This parameter can be: ENABLE or DISABLE.
315
* Output         : None
316
* Return         : None
317
*******************************************************************************/
318
void DMA_ITConfig(u16 DMA_IT, FunctionalState NewState)
319
{
320
  if(NewState == ENABLE)
321
  {
322
    /* Enable the selected DMA interrupts */
323
    DMA->MASK |= DMA_IT;
324
  }
325
  else
326
  {
327
    /* Disable the selected DMA interrupts */
328
    DMA->MASK &= ~DMA_IT;
329
  }
330
}
331
 
332
/*******************************************************************************
333
* Function Name  : DMA_GetCurrDSTAddr
334
* Description    : Returns the current value of the destination address pointer
335
*                  related to the specified DMA stream.
336
* Input          : - DMA_Streamx: where x can be 0, 1, 2 or 3 to select the DMA
337
*                    Stream.
338
* Output         : None
339
* Return         : The current value of the destination address pointer related
340
*                  to the specified DMA stream.
341
*******************************************************************************/
342
u32 DMA_GetCurrDSTAddr(DMA_Stream_TypeDef*  DMA_Streamx)
343
{
344
  u32 Tmp = 0;
345
 
346
  /* Get high current destination address */
347
  Tmp = (DMA_Streamx->DECURRH)<<16;
348
  /* Get low current destination address */
349
  Tmp |= DMA_Streamx->DECURRL;
350
 
351
  /* Return the current destination address value for streamx */
352
  return Tmp;
353
}
354
 
355
/*******************************************************************************
356
* Function Name  : DMA_GetCurrSRCAddr
357
* Description    : Returns the current value of the source address pointer
358
*                  related to the specified DMA stream.
359
* Input          : - DMA_Streamx: where x can be 0, 1, 2 or 3 to select the DMA
360
*                    Stream.
361
* Output         : None
362
* Return         : The current value of the source address pointer related to
363
*                  the specified DMA stream.
364
*******************************************************************************/
365
u32 DMA_GetCurrSRCAddr(DMA_Stream_TypeDef*  DMA_Streamx)
366
{
367
  u32 Tmp = 0;
368
 
369
  /* Get high current source address */
370
  Tmp = (DMA_Streamx->SOCURRH)<<16;
371
  /* Get slow current source address */
372
  Tmp |= DMA_Streamx->SOCURRL;
373
 
374
  /* Return the current source address value for streamx */
375
  return Tmp;
376
}
377
 
378
/*******************************************************************************
379
* Function Name  : DMA_GetTerminalCounter
380
* Description    : Returns the number of data units remaining in the current
381
*                  DMA stream transfer.
382
* Input          : - DMA_Streamx: where x can be 0, 1, 2 or 3 to select the DMA
383
*                    Stream.
384
* Output         : None
385
* Return         : The number of data units remaining in the current DMA stream
386
*                  transfer.
387
*******************************************************************************/
388
u16 DMA_GetTerminalCounter(DMA_Stream_TypeDef*  DMA_Streamx)
389
{
390
  /* Return the terminal counter value for streamx */
391
  return(DMA_Streamx->TCNT);
392
}
393
 
394
/*******************************************************************************
395
* Function Name  : DMA_LastBufferSweepConfig
396
* Description    : Activates or disactivates the last buffer sweep mode for the
397
*                  DMA streamx configured in circular buffer mode.
398
* Input          : - DMA_Streamx: where x can be 0, 1, 2 or 3 to select the DMA
399
*                    Stream.
400
*                  - NewState: new state of the Last buffer sweep DMA_Streamx.
401
*                    This parameter can be: ENABLE or DISABLE.
402
* Output         : None
403
* Return         : None
404
*******************************************************************************/
405
void DMA_LastBufferSweepConfig(DMA_Stream_TypeDef* DMA_Streamx, FunctionalState NewState)
406
{
407
  switch(*(u32*)&DMA_Streamx)
408
  {
409
    case DMA_Stream0_BASE:
410
      if(NewState == ENABLE)
411
      {
412
        /* Activates the last circular buffer sweep mode for stream0 */
413
        DMA->LAST |= DMA_Last0_Enable_Mask;
414
      }
415
      else
416
      {
417
        /* Disactivates the last circular buffer sweep mode for stream0 */
418
        DMA->LAST &= DMA_Last0_Disable_Mask;
419
      }
420
      break;
421
 
422
    case DMA_Stream1_BASE:
423
      if(NewState == ENABLE)
424
      {
425
        /* Activates the last circular buffer sweep mode for stream1 */
426
        DMA->LAST |= DMA_Last1_Enable_Mask;
427
      }
428
      else
429
      {
430
        /* Disactivates the last circular buffer sweep mode for stream1 */
431
        DMA->LAST &= DMA_Last1_Disable_Mask;
432
      }
433
      break;
434
 
435
    case DMA_Stream2_BASE:
436
      if(NewState == ENABLE)
437
      {
438
        /* Activates the last circular buffer sweep mode for stream2 */
439
        DMA->LAST |= DMA_Last2_Enable_Mask;
440
      }
441
      else
442
      {
443
        /* Disactivates the last circular buffer sweep mode for stream2 */
444
        DMA->LAST &= DMA_Last2_Disable_Mask;
445
      }
446
      break;
447
 
448
    case DMA_Stream3_BASE:
449
      if(NewState == ENABLE)
450
      {
451
        /* Activates the last circular buffer sweep mode for stream3 */
452
        DMA->LAST |= DMA_Last3_Enable_Mask;
453
      }
454
      else
455
      {
456
        /* Disactivates the last circular buffer sweep mode for stream3 */
457
        DMA->LAST &= DMA_Last3_Disable_Mask;
458
      }
459
      break;
460
 
461
    default:
462
      break;
463
  }
464
}
465
 
466
/*******************************************************************************
467
* Function Name  : DMA_LastBufferAddrConfig
468
* Description    : Configures the circular buffer position where the last data
469
*                  to be used by the specified DMA stream is located.
470
* Input          : - DMA_Streamx: where x can be 0, 1, 2 or 3 to select the DMA
471
*                    Stream.
472
*                  - DMA_LastBufferAddr: specifies the circular buffer position
473
*                    where the last data to be used by the specified DMA stream
474
*                    is located.
475
*                    This member must be a number between 0 and the stream BufferSize-1.
476
* Output         : None
477
* Return         : None
478
*******************************************************************************/
479
void DMA_LastBufferAddrConfig(DMA_Stream_TypeDef*  DMA_Streamx, u16 DMA_LastBufferAddr)
480
{
481
  /* Set the streamx last data circular buffer location */
482
  DMA_Streamx->LUBUFF = DMA_LastBufferAddr;
483
}
484
 
485
/*******************************************************************************
486
* Function Name  : DMA_GetFlagStatus
487
* Description    : Checks whether the specified DMA flag is set or not.
488
* Input          : - DMA_FLAG: specifies the flag to check. This parameter can
489
*                    be one of the following values:
490
*                         - DMA_FLAG_SI0:  Stream0 transfer end flag.
491
*                         - DMA_FLAG_SI1:  Stream1 transfer end flag.
492
*                         - DMA_FLAG_SI2:  Stream2 transfer end flag.
493
*                         - DMA_FLAG_SI3:  Stream3 transfer end flag.
494
*                         - DMA_FLAG_SE0:  Stream0 transfer error flag.
495
*                         - DMA_FLAG_SE1:  Stream1 transfer error flag.
496
*                         - DMA_FLAG_SE2:  Stream2 transfer error flag.
497
*                         - DMA_FLAG_SE3:  Stream3 transfer error flag.
498
*                         - DMA_FLAG_ACT0: Stream0 status.
499
*                         - DMA_FLAG_ACT1: Stream1 status.
500
*                         - DMA_FLAG_ACT2: Stream2 status.
501
*                         - DMA_FLAG_ACT3: Stream3 status.
502
* Output         : None
503
* Return         : The new state of DMA_FLAG (SET or RESET).
504
*******************************************************************************/
505
FlagStatus DMA_GetFlagStatus(u16 DMA_FLAG)
506
{
507
  /* Check the status of the specified DMA flag */
508
  if((DMA->STATUS & DMA_FLAG) != RESET)
509
  {
510
    /* Return SET if DMA_FLAG is set */
511
    return SET;
512
  }
513
  else
514
  {
515
    /* Return RESET if DMA_FLAG is reset */
516
    return RESET;
517
  }
518
}
519
 
520
/*******************************************************************************
521
* Function Name  : DMA_ClearFlag
522
* Description    : Clears the DMA’s pending flags.
523
* Input          : - DMA_FLAG: specifies the flag to clear. This parameter can
524
*                    be any combination of the following values:
525
*                         - DMA_FLAG_SI0:  Stream0 transfer end flag.
526
*                         - DMA_FLAG_SI1:  Stream1 transfer end flag.
527
*                         - DMA_FLAG_SI2:  Stream2 transfer end flag.
528
*                         - DMA_FLAG_SI3:  Stream3 transfer end flag.
529
*                         - DMA_FLAG_SE0:  Stream0 transfer error flag.
530
*                         - DMA_FLAG_SE1:  Stream1 transfer error flag.
531
*                         - DMA_FLAG_SE2:  Stream2 transfer error flag.
532
*                         - DMA_FLAG_SE3:  Stream3 transfer error flag.
533
* Output         : None
534
* Return         : None
535
*******************************************************************************/
536
void DMA_ClearFlag(u16 DMA_FLAG)
537
{
538
  /* Clear the selected DMA flags */
539
  DMA->CLR = DMA_FLAG ;
540
}
541
 
542
/*******************************************************************************
543
* Function Name  : DMA_GetITStatus
544
* Description    : Checks whether the specified DMA interrupt has occured or not.
545
* Input          : - DMA_IT: specifies the DMA interrupt source to check.
546
*                    This parameter can be one of the following values:
547
*                         - DMA_IT_SI0: Stream0 transfer end interrupt
548
*                         - DMA_IT_SI1: Stream1 transfer end interrupt
549
*                         - DMA_IT_SI2: Stream2 transfer end interrupt
550
*                         - DMA_IT_SI3: Stream3 transfer end interrupt
551
*                         - DMA_IT_SE0: Stream0 transfer error interrupt
552
*                         - DMA_IT_SE1: Stream1 transfer error interrupt
553
*                         - DMA_IT_SE2: Stream2 transfer error interrupt
554
*                         - DMA_IT_SE3: Stream3 transfer error interrupt
555
* Output         : None
556
* Return         : The new state of DMA_IT (SET or RESET).
557
*******************************************************************************/
558
ITStatus DMA_GetITStatus(u16 DMA_IT)
559
{
560
  /* Check the status of the specified DMA interrupt */
561
  if((DMA->STATUS & DMA_IT) != RESET)
562
  {
563
    /* Return SET if the DMA interrupt flag is set */
564
    return SET;
565
  }
566
  else
567
  {
568
    /* Return RESET if the DMA interrupt flag is reset */
569
    return RESET;
570
  }
571
}
572
 
573
/*******************************************************************************
574
* Function Name  : DMA_ClearITPendingBit
575
* Description    : Clears the DMA’s interrupt pending bits.
576
* Input          : - DMA_IT: specifies the interrupt pending bit to clear.
577
*                    This parameter can be any combination of the following values:
578
*                         - DMA_IT_SI0:  Stream0 transfer end interrupt.
579
*                         - DMA_IT_SI1:  Stream1 transfer end interrupt.
580
*                         - DMA_IT_SI2:  Stream2 transfer end interrupt.
581
*                         - DMA_IT_SI3:  Stream3 transfer end interrupt.
582
*                         - DMA_IT_SE0:  Stream0 transfer error interrupt.
583
*                         - DMA_IT_SE1:  Stream1 transfer error interrupt.
584
*                         - DMA_IT_SE2:  Stream2 transfer error interrupt.
585
*                         - DMA_IT_SE3:  Stream3 transfer error interrupt.
586
*                         - DMA_IT_ALL:  All DMA interrupts.
587
* Output         : None
588
* Return         : None
589
*******************************************************************************/
590
void DMA_ClearITPendingBit(u16 DMA_IT)
591
{
592
  /* Clear the selected DMA interrupts pending bits */
593
  DMA->CLR = DMA_IT ;
594
}
595
 
596
/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/

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