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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [ARM9_AT91SAM9XE_IAR/] [ewp/] [at91sam9xe-ek-sdram.mac] - Blame information for rev 615

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Line No. Rev Author Line
1 577 jeremybenn
// ---------------------------------------------------------
2
//   ATMEL Microcontroller Software Support  -  ROUSSET  -
3
// ---------------------------------------------------------
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// The software is delivered "AS IS" without warranty or
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// condition of any  kind, either express, implied or
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// statutory. This includes without limitation any warranty
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// or condition with respect to merchantability or fitness
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// for any particular purpose, or against the infringements of
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// intellectual property rights of others.
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// ---------------------------------------------------------
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//  File: SAM9XE_SDRAM.mac
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//  User setup file for CSPY debugger.
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//  1.1 08/Aug/06 jpp    : Creation
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//
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//  $Revision: 2 $
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//
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// ---------------------------------------------------------
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__var __mac_i;
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__var __mac_pt;
20
 
21
/*********************************************************************
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*
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*       execUserReset() : JTAG set initially to Full Speed
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*/
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execUserReset()
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{
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    __message "------------------------------ execUserReset ---------------------------------";
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    _MapRAMAt0();                          //* Set the RAM memory at 0x00200000 & 0x00000000
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    __PllSetting();                        //* Init PLL
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    __PllSetting100MHz();
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    __message "-------------------------------Set PC Reset ----------------------------------";
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}
33
 
34
/*********************************************************************
35
*
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*       execUserPreload() : JTAG set initially to 32kHz
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*/
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execUserPreload()
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{
40
    __message "------------------------------ execUserPreload ---------------------------------";
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    __hwReset(0);                          //* Hardware Reset: CPU is automatically halted after the reset (JTAG is already configured to 32kHz)
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    __writeMemory32(0xD3,0x98,"Register"); //*  Set CPSR
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    __PllSetting();                        //* Init PLL
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    __PllSetting100MHz();
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    __initSDRAM();                         //* Init SDRAM before load
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    _MapRAMAt0();                          //* Set the RAM memory at 0x0020 0000 & 0x0000 0000
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    _InitRSTC();                           //* Enable User Reset to allow execUserReset() execution
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}
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50
 
51
 
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/*********************************************************************
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*
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*       _InitRSTC()
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*
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* Function description
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*   Initializes the RSTC (Reset controller).
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*   This makes sense since the default is to not allow user resets, which makes it impossible to
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*   apply a second RESET via J-Link
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*/
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_InitRSTC() {
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    __writeMemory32(0xA5000001, 0xFFFFFD08,"Memory");    // Allow user reset
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}
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65
 
66
/*********************************************************************
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*
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*       __initSDRAM()
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* Function description
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* Set SDRAM for works at 100 MHz
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*/
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__initSDRAM()
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{
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//* Configure EBI Chip select
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//    pCCFG->CCFG_EBICSA |= AT91C_EBI_CS1A_SDRAMC;
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// AT91C_CCFG_EBICSA ((AT91_REG *)      0xFFFFEF1C) // (CCFG)  EBI Chip Select Assignement Register
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    __writeMemory32(0x0001003A,0xFFFFEF1C,"Memory");
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79
 
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//*  Configure PIOs
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//*     AT91F_PIO_CfgPeriph( AT91C_BASE_PIOC, AT91C_PC16_D16 to AT91C_PC16_D31
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// pPio->PIO_ASR = periphAEnable; AT91C_PIOC_ASR ((AT91_REG *) 0xFFFFF870) // (PIOC) Select A Register
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// pPio->PIO_BSR = periphBEnable;AT91C_PIOC_BSR  ((AT91_REG *) 0xFFFFF874) // (PIOC) Select B Register
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// pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode
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    __writeMemory32(0xFFFF0000,0xFFFFF870,"Memory");
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    __writeMemory32(0x00000000,0xFFFFF874,"Memory");
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    __writeMemory32(0xFFFF0000,0xFFFFF804,"Memory");
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//* psdrc->SDRAMC_CR =  AT91C_SDRAMC_NC_9  | AT91C_SDRAMC_NR_13 | AT91C_SDRAMC_CAS_3 |
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//  AT91C_SDRAMC_NB_4_BANKS | AT91C_SDRAMC_DBW_32_BITS | AT91C_SDRAMC_TWR_2 | AT91C_SDRAMC_TRC_7 |
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//  AT91C_SDRAMC_TRP_2 | AT91C_SDRAMC_TRCD_2 | AT91C_SDRAMC_TRAS_5 | AT91C_SDRAMC_TXSR_8 ;
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    __writeMemory32(0x85227279,0xFFFFEA08,"Memory");
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 __sleep(100);
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//*     psdrc->SDRAMC_MR        = 0x00000002;           // Set PRCHG AL
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    __writeMemory32(0x00000002,0xFFFFEA00,"Memory");
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//*     *AT91C_SDRAM    = 0x00000000;                   // Perform PRCHG
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    __writeMemory32(0x00000000,0x20000000,"Memory");
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 __sleep(100);
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100
 
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//*     psdrc->SDRAMC_MR        = AT91C_SDRAMC_MODE_RFSH_CMD;           // Set 1st CBR
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      __writeMemory32(0x00000004,0xFFFFEA00,"Memory");
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//*     *(AT91C_SDRAM+4)        = 0x00000001;   // Perform CBR
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    __writeMemory32(0x00000001,0x20000010,"Memory");
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//*     psdrc->SDRAMC_MR        = 0x00000004;           // Set 2 CBR
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     __writeMemory32(0x00000004,0xFFFFEA00,"Memory");
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//*     *(AT91C_SDRAM+8)        = 0x00000002;   // Perform CBR
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     __writeMemory32(0x00000002,0x20000020,"Memory");
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//*     psdrc->SDRAMC_MR        = AT91C_SDRAMC_MODE_RFSH_CMD;           // Set 3 CBR
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      __writeMemory32(0x00000004,0xFFFFEA00,"Memory");
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//*     *(AT91C_SDRAM+0xc)      = 0x00000003;   // Perform CBR
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     __writeMemory32(0x00000003,0x20000030,"Memory");
116
 
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//*     psdrc->SDRAMC_MR        = AT91C_SDRAMC_MODE_RFSH_CMD;           // Set 4 CBR
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      __writeMemory32(0x00000004,0xFFFFEA00,"Memory");
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//*     *(AT91C_SDRAM+0x10)     = 0x00000004;   // Perform CBR
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     __writeMemory32(0x00000004,0x20000040,"Memory");
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//*     psdrc->SDRAMC_MR        = AT91C_SDRAMC_MODE_RFSH_CMD;           // Set 5 CBR
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      __writeMemory32(0x00000004,0xFFFFEA00,"Memory");
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//*     *(AT91C_SDRAM+0x14)     = 0x00000005;   // Perform CBR
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     __writeMemory32(0x00000005,0x20000050,"Memory");
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//*     psdrc->SDRAMC_MR        = AT91C_SDRAMC_MODE_RFSH_CMD;           // Set 6 CBR
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      __writeMemory32(0x00000004,0xFFFFEA00,"Memory");
129
//*     *(AT91C_SDRAM+0x18)     = 0x00000006;   // Perform CBR
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     __writeMemory32(0x00000006,0x20000060,"Memory");
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132
//*     psdrc->SDRAMC_MR        = AT91C_SDRAMC_MODE_RFSH_CMD;           // Set 7 CBR
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      __writeMemory32(0x00000004,0xFFFFEA00,"Memory");
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//*     *(AT91C_SDRAM+0x1c)     = 0x00000007;   // Perform CBR
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     __writeMemory32(0x00000007,0x20000070,"Memory");
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//*     psdrc->SDRAMC_MR        = AT91C_SDRAMC_MODE_RFSH_CMD;           // Set 8 CBR
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      __writeMemory32(0x00000004,0xFFFFEA00,"Memory");
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//*     *(AT91C_SDRAM+0x20)     = 0x00000008;   // Perform CBR
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     __writeMemory32(0x00000008,0x20000080,"Memory");
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//*     psdrc->SDRAMC_MR        = AT91C_SDRAMC_MODE_LMR_CMD;            // Set LMR operation
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      __writeMemory32(0x00000003,0xFFFFEA00,"Memory");
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//*     *(AT91C_SDRAM+0x24)     = 0xcafedede;           // Perform LMR burst=1, lat=2
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     __writeMemory32(0xCAFEDEDE,0x20000090,"Memory");
146
 
147
//*     psdrc->SDRAMC_TR        = (AT91C_MASTER_CLOCK * 7)/1000000;                             // Set Refresh Timer 390 for 25MHz (TR= 15.6 * F )
148
//                                                                                     // (F : system clock freq. MHz
149
 
150
      __writeMemory32(0x000002B9,0xFFFFEA04,"Memory");
151
 
152
//*     psdrc->SDRAMC_MR        = AT91C_SDRAMC_MODE_NORMAL_CMD;         // Set Normal mode
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      __writeMemory32(0x00000000,0xFFFFEA00,"Memory");
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//*     *AT91C_SDRAM    = 0x00000000;   // Perform Normal mode
156
      __writeMemory32(0x00000000,0x20000000,"Memory");
157
   __message "------------------------------- SDRAM Done at 100 MHz -------------------------------";
158
 
159
}
160
 
161
/*********************************************************************
162
*
163
*       _MapRAMAt0()
164
* Function description
165
* Remap RAM at 0
166
*/
167
_MapRAMAt0()
168
{
169
// AT91C_MATRIX_MRCR ((AT91_REG *)      0xFFFFEF00) // (MATRIX)  Master Remp Control Register
170
    __mac_i=__readMemory32(0xFFFFEF00,"Memory");
171
    __message "----- AT91C_MATRIX_MRCR  : 0x",__mac_i:%X;
172
 
173
    if ( ((__mac_i & 0x01) == 0) || ((__mac_i & 0x02) == 0)){
174
        __message "------------------------------- The Remap is NOT & REMAP ----------------------------";
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        __writeMemory32(0x00000003,0xFFFFEF00,"Memory");
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        __mac_i=__readMemory32(0xFFFFEF00,"Memory");
177
        __message "----- AT91C_MATRIX_MRCR  : 0x",__mac_i:%X;
178
    } else {
179
        __message "------------------------------- The Remap is done -----------------------------------";
180
    }
181
}
182
 
183
 
184
/*********************************************************************
185
*
186
*       __PllSetting()
187
* Function description
188
*   Initializes the PMC.
189
*   1. Enable the Main Oscillator
190
*   2. Configure PLL
191
*   3. Switch Master
192
*/
193
__PllSetting()
194
{
195
     if ((__readMemory32(0xFFFFFC30,"Memory")&0x3) != 0 ) {
196
//* Disable all PMC interrupt ( $$ JPP)
197
//* AT91C_PMC_IDR   ((AT91_REG *) 0xFFFFFC64) //(PMC) Interrupt Disable Register
198
//*    pPmc->PMC_IDR = 0xFFFFFFFF;
199
    __writeMemory32(0xFFFFFFFF,0xFFFFFC64,"Memory");
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//* AT91C_PMC_PCDR  ((AT91_REG *) 0xFFFFFC14) //(PMC) Peripheral Clock Disable Register
201
    __writeMemory32(0xFFFFFFFF,0xFFFFFC14,"Memory");
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// Disable all clock only Processor clock is enabled.
203
    __writeMemory32(0xFFFFFFFE,0xFFFFFC04,"Memory");
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205
// AT91C_PMC_MCKR  ((AT91_REG *)        0xFFFFFC30) // (PMC) Master Clock Register
206
    __writeMemory32(0x00000001,0xFFFFFC30,"Memory");
207
    __sleep(10000);
208
 
209
// write reset value to PLLA and PLLB
210
// AT91C_PMC_PLLAR ((AT91_REG *)        0xFFFFFC28) // (PMC) PLL A Register
211
    __writeMemory32(0x00003F00,0xFFFFFC28,"Memory");
212
 
213
// AT91C_PMC_PLLBR ((AT91_REG *)        0xFFFFFC2C) // (PMC) PLL B Register
214
    __writeMemory32(0x00003F00,0xFFFFFC2C,"Memory");
215
    __sleep(10000);
216
 
217
   __message "------------------------------- PLL  Enable -----------------------------------------";
218
   } else {
219
   __message " ********* Core in SLOW CLOCK mode ********* "; }
220
}
221
 
222
 
223
/*********************************************************************
224
*
225
*       __PllSetting100MHz()
226
* Function description
227
*   Set core at 200 MHz and MCK at 100 MHz
228
*/
229
__PllSetting100MHz()
230
{
231
 
232
   __message "------------------------------- PLL Set at 100 MHz ----------------------------------";
233
 
234
//* pPmc->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x40 <<8) | AT91C_CKGR_MOSCEN ));
235
    __writeMemory32(0x00004001,0xFFFFFC20,"Memory");
236
    __sleep(10000);
237
// AT91C_PMC_MCKR  ((AT91_REG *)        0xFFFFFC30) // (PMC) Master Clock Register
238
    __writeMemory32(0x00000001,0xFFFFFC30,"Memory");
239
    __sleep(10000);
240
//*   AT91C_BASE_CKGR->CKGR_PLLAR = (AT91C_CKGR_SRCA | ((96 << 16) & AT91C_CKGR_MULA) |
241
//    (AT91C_CKGR_PLLACOUNT | (AT91C_CKGR_OUTA_0 | (9);
242
    __writeMemory32(0x2060BF09,0xFFFFFC28,"Memory");
243
    __sleep(10000);
244
//*   AT91C_BASE_PMC->PMC_MCKR =  AT91C_PMC_CSS_PLLA_CLK | AT91C_PMC_PRES_CLK | AT91C_PMC_MDIV_2;;
245
    __writeMemory32(0x00000102,0xFFFFFC30,"Memory");
246
     __sleep(10000);
247
 
248
}
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