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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [ARM9_AT91SAM9XE_IAR/] [ewp/] [at91sam9xe-ek-sram.mac] - Blame information for rev 583

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Line No. Rev Author Line
1 577 jeremybenn
// ---------------------------------------------------------
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//   ATMEL Microcontroller Software Support  -  ROUSSET  -
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// ---------------------------------------------------------
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// The software is delivered "AS IS" without warranty or
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// condition of any  kind, either express, implied or
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// statutory. This includes without limitation any warranty
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// or condition with respect to merchantability or fitness
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// for any particular purpose, or against the infringements of
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// intellectual property rights of others.
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// ---------------------------------------------------------
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//  File: SAM9XE_SRAM.mac
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//  User setup file for CSPY debugger.
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//  1.1 08/Aug/06 jpp    : Creation
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//
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//  $Revision: 2 $
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//
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// ---------------------------------------------------------
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__var __mac_i;
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__var __mac_pt;
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/*********************************************************************
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*
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*       execUserReset() : JTAG set initially to Full Speed
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*/
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execUserReset()
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{
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    __message "------------------------------ execUserReset ---------------------------------";
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    _MapRAMAt0();                          //* Set the RAM memory at 0x00200000 & 0x00000000
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    __PllSetting();                        //* Init PLL
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    __PllSetting100MHz();
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    __message "-------------------------------Set PC Reset ----------------------------------";
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}
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/*********************************************************************
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*
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*       execUserPreload() : JTAG set initially to 32kHz
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*/
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execUserPreload()
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{
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    __message "------------------------------ execUserPreload ---------------------------------";
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    __hwReset(0);                          //* Hardware Reset: CPU is automatically halted after the reset (JTAG is already configured to 32kHz)
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    __writeMemory32(0xD3,0x98,"Register"); //*  Set CPSR
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    __PllSetting();                        //* Init PLL
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    __PllSetting100MHz();
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    _MapRAMAt0();                          //* Set the RAM memory at 0x0020 0000 & 0x0000 0000
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    _InitRSTC();                           //* Enable User Reset to allow execUserReset() execution
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}
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/*********************************************************************
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*
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*       _InitRSTC()
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*
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* Function description
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*   Initializes the RSTC (Reset controller).
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*   This makes sense since the default is to not allow user resets, which makes it impossible to
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*   apply a second RESET via J-Link
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*/
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_InitRSTC() {
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    __writeMemory32(0xA5000001, 0xFFFFFD08,"Memory");    // Allow user reset
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}
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/*********************************************************************
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*
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*       _MapRAMAt0()
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* Function description
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* Remap RAM at 0
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*/
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_MapRAMAt0()
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{
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// AT91C_MATRIX_MRCR ((AT91_REG *)      0xFFFFEF00) // (MATRIX)  Master Remp Control Register
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    __mac_i=__readMemory32(0xFFFFEF00,"Memory");
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    __message "----- AT91C_MATRIX_MRCR  : 0x",__mac_i:%X;
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    if ( ((__mac_i & 0x01) == 0) || ((__mac_i & 0x02) == 0)){
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        __message "------------------------------- The Remap is NOT & REMAP ----------------------------";
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        __writeMemory32(0x00000003,0xFFFFEF00,"Memory");
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        __mac_i=__readMemory32(0xFFFFEF00,"Memory");
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        __message "----- AT91C_MATRIX_MRCR  : 0x",__mac_i:%X;
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    } else {
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        __message "------------------------------- The Remap is done -----------------------------------";
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    }
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}
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/*********************************************************************
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*
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*       __PllSetting()
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* Function description
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*   Initializes the PMC.
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*   1. Enable the Main Oscillator
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*   2. Configure PLL
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*   3. Switch Master
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*/
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__PllSetting()
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{
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     if ((__readMemory32(0xFFFFFC30,"Memory")&0x3) != 0 ) {
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//* Disable all PMC interrupt ( $$ JPP)
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//* AT91C_PMC_IDR   ((AT91_REG *) 0xFFFFFC64) //(PMC) Interrupt Disable Register
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//*    pPmc->PMC_IDR = 0xFFFFFFFF;
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    __writeMemory32(0xFFFFFFFF,0xFFFFFC64,"Memory");
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//* AT91C_PMC_PCDR  ((AT91_REG *) 0xFFFFFC14) //(PMC) Peripheral Clock Disable Register
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    __writeMemory32(0xFFFFFFFF,0xFFFFFC14,"Memory");
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// Disable all clock only Processor clock is enabled.
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    __writeMemory32(0xFFFFFFFE,0xFFFFFC04,"Memory");
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// AT91C_PMC_MCKR  ((AT91_REG *)        0xFFFFFC30) // (PMC) Master Clock Register
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    __writeMemory32(0x00000001,0xFFFFFC30,"Memory");
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    __sleep(10000);
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// write reset value to PLLA and PLLB
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// AT91C_PMC_PLLAR ((AT91_REG *)        0xFFFFFC28) // (PMC) PLL A Register
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    __writeMemory32(0x00003F00,0xFFFFFC28,"Memory");
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// AT91C_PMC_PLLBR ((AT91_REG *)        0xFFFFFC2C) // (PMC) PLL B Register
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    __writeMemory32(0x00003F00,0xFFFFFC2C,"Memory");
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    __sleep(10000);
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   __message "------------------------------- PLL  Enable -----------------------------------------";
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   } else {
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   __message " ********* Core in SLOW CLOCK mode ********* "; }
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}
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/*********************************************************************
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*
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*       __PllSetting100MHz()
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* Function description
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*   Set core at 200 MHz and MCK at 100 MHz
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*/
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__PllSetting100MHz()
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{
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   __message "------------------------------- PLL Set at 100 MHz ----------------------------------";
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//* pPmc->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x40 <<8) | AT91C_CKGR_MOSCEN ));
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    __writeMemory32(0x00004001,0xFFFFFC20,"Memory");
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    __sleep(10000);
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// AT91C_PMC_MCKR  ((AT91_REG *)        0xFFFFFC30) // (PMC) Master Clock Register
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    __writeMemory32(0x00000001,0xFFFFFC30,"Memory");
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    __sleep(10000);
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//*   AT91C_BASE_CKGR->CKGR_PLLAR = (AT91C_CKGR_SRCA | ((96 << 16) & AT91C_CKGR_MULA) |
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//    (AT91C_CKGR_PLLACOUNT | (AT91C_CKGR_OUTA_0 | (9);
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    __writeMemory32(0x2060BF09,0xFFFFFC28,"Memory");
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    __sleep(10000);
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//*   AT91C_BASE_PMC->PMC_MCKR =  AT91C_PMC_CSS_PLLA_CLK | AT91C_PMC_PRES_CLK | AT91C_PMC_MDIV_2;;
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    __writeMemory32(0x00000102,0xFFFFFC30,"Memory");
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     __sleep(10000);
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}
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