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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [ARM9_STR91X_IAR/] [91x_init_IAR.s] - Blame information for rev 591

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1 577 jeremybenn
;******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
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;* File Name          : 91x_init.s
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;* Author             : MCD Application Team
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;* Date First Issued  : 05/18/2006 : Version 1.0
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;* Description        : This module performs:
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;*                      - FLASH/RAM initialization,
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;*                      - Stack pointer initialization for each mode ,
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;*                      - Branches to ?main in the C library (which eventually 
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;*                        calls main()).
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;*
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;*                    On reset, the ARM core starts up in Supervisor (SVC) mode,
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;*                    in ARM state,with IRQ and FIQ disabled.
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;*******************************************************************************
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; History:
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; 05/24/2006 : Version 1.1
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; 05/18/2006 : Version 1.0
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;*******************************************************************************
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;* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
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;* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS
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;* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
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;* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
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;* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
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;* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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;******************************************************************************/
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; Depending in Your Application, Disable or Enable the following Define
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;         #define  BUFFERED_Mode       ; Work on Buffered mode, when enabling this define
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                               ; just enable the Buffered define on 91x_conf.h
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; --- Standard definitions of mode bits and interrupt (I & F) flags in PSRs
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Mode_USR           EQU     0x10
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Mode_FIQ           EQU     0x11
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Mode_IRQ           EQU     0x12
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Mode_SVC           EQU     0x13
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Mode_ABT           EQU     0x17
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Mode_UND           EQU     0x1B
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Mode_SYS           EQU     0x1F ; available on ARM Arch 4 and later
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I_Bit              EQU     0x80 ; when I bit is set, IRQ is disabled
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F_Bit              EQU     0x40 ; when F bit is set, FIQ is disabled
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;--- BASE ADDRESSES
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; System memory locations
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SRAM_Base               EQU     0x04000000
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SRAM_Limit              EQU     0x04018000                      ; at the top of 96 KB SRAM
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SVC_Stack           DEFINE     SRAM_Limit       ; 512 byte SVC stack at
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                                                         ; top of memory - used by kernel.
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IRQ_Stack           DEFINE     SVC_Stack-512    ; followed by IRQ stack
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USR_Stack           DEFINE     IRQ_Stack-512    ; followed by USR stack.  Tasks run in
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                                                ; system mode but task stacks are allocated
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                                                ; when the task is created.
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FIQ_Stack           DEFINE     USR_Stack-8      ; followed by FIQ stack
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ABT_Stack           DEFINE     FIQ_Stack-8      ; followed by ABT stack
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UND_Stack               DEFINE     ABT_Stack-8      ; followed by UNDEF stack
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                                        EXTERN main
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; STR9X register specific definition
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FMI_BBSR_AHB_UB                 EQU                     0x54000000
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FMI_BBADR_AHB_UB                EQU                     0x5400000C
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FMI_NBBSR_AHB_UB                EQU                     0x54000004
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FMI_NBBADR_AHB_UB               EQU                     0x54000010
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SCU_SCRO_APB1_UB                EQU                     0x4C002034
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SCRO_AHB_UNB    EQU     0x5C002034
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;---------------------------------------------------------------
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; ?program_start
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;---------------------------------------------------------------
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                MODULE  ?program_start
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                RSEG    ICODE:CODE(2)
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                IMPORT    LINK
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                PUBLIC  __program_start
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                EXTERN  ?main
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                CODE32
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__program_start:
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        LDR     pc, =NextInst
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NextInst
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        NOP   ; execute some instructions to access CPU registers after wake
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        NOP  ; up from Reset, while waiting for OSC stabilization
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        NOP
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        NOP
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        NOP
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        NOP
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        NOP
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        NOP
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        NOP
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                ldr r0,=LINK    ; to include the vector table inside the final executable.
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; --- Remap Flash Bank 0 at address 0x0 and Bank 1 at address 0x80000, 
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;     when the bank 0 is the boot bank, then enable the Bank 1.
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        LDR R6, =0x54000000
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        LDR R7, =0x4
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        STR R7, [R6]
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        LDR R6, =0x54000004
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        LDR R7, =0x3
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        STR R7, [R6]
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        LDR R6, =0x5400000C
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        LDR R7, =0x0
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        STR R7, [R6]
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        LDR R6, =0x54000010
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        LDR R7, =0x20000
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        STR R7, [R6]
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        LDR R6, =0x54000018
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        LDR R7, =0x18
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        STR R7, [R6]
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; --- Enable 96K RAM
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        LDR     R0, = SCRO_AHB_UNB
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        LDR     R1, = 0x0196
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        STR     R1, [R0]
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        /* Setup a stack for each mode - note that this only sets up a usable stack
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        for system/user, SWI and IRQ modes.   Also each mode is setup with
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        interrupts initially disabled. */
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        MSR     CPSR_c, #Mode_FIQ|I_Bit|F_Bit   ; No interrupts
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        LDR     SP, =FIQ_Stack
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        MSR     CPSR_c, #Mode_IRQ|I_Bit|F_Bit   ; No interrupts
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        LDR     SP, =IRQ_Stack
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        MSR     CPSR_c, #Mode_ABT|I_Bit|F_Bit   ; No interrupts
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        LDR     SP, =ABT_Stack
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        MSR     CPSR_c, #Mode_UND|I_Bit|F_Bit   ; No interrupts
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        LDR     SP, =UND_Stack
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        MSR     CPSR_c, #Mode_SVC|I_Bit|F_Bit   ; No interrupts
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        LDR     SP, =SVC_Stack
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        MSR     CPSR_c, #Mode_SYS|I_Bit|F_Bit   ; No interrupts
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        LDR     SP, =USR_Stack
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        /* We want to start in supervisor mode.  Operation will switch to system
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        mode when the first task starts. */
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        MSR   CPSR_c, #Mode_SVC|I_Bit|F_Bit
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; --- Set bits 17-18 of the Core Configuration Control Register
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        MOV     r0, #0x60000
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        MCR     p15,0x1,r0,c15,c1,0
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; --- Now enter the C code
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        B       ?main   ; Note : use B not BL, because an application will
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                         ; never return this way
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        LTORG
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        END
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;******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****
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