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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [ARM9_STR91X_IAR/] [Library/] [include/] [91x_dma.h] - Blame information for rev 612

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1 577 jeremybenn
/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
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* File Name          : template.h
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* Author             : MCD Application Team
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* Date First Issued  : 05/18/2006 : Version 1.0
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* Description        : provide a short description of the source file indicating
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*                      its purpose.
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********************************************************************************
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* History:
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* 05/24/2006 : Version 1.1
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* 05/18/2006 : Version 1.0
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********************************************************************************
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* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
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* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
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* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
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* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
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* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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*******************************************************************************/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __91x_DMA_H
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#define __91x_DMA_H
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/* Includes ------------------------------------------------------------------*/
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#include"91x_map.h"
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/* Exported types ------------------------------------------------------------*/
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typedef struct
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{
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 u32 DMA_Channel_SrcAdd;    /* The current source address (byte-aligned) of the data to be transferred.*/
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 u32 DMA_Channel_DesAdd;    /* The current destination address (byte-aligned) of the data to be transferred.*/
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 u32 DMA_Channel_LLstItm;   /* The word- aligned address for the next Linked List Item. */
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 u32 DMA_Channel_DesWidth;   /* Destination transfer width. */
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 u32 DMA_Channel_SrcWidth;   /* Source transfer width. */
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 u32 DMA_Channel_DesBstSize; /* The destination burst size which indicates the number of transfers that make up a destination burst transfer request.*/
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 u32 DMA_Channel_SrcBstSize; /* The source burst size.Indicates the number of transfers that make up a source burst */
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 u32 DMA_Channel_TrsfSize;   /* Transfer size which indicates the size of the transfer when the DMA controller is the flow controller*/
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 u32 DMA_Channel_FlowCntrl;  /* Flow control and transfer type. */
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 u32 DMA_Channel_Src;        /* Source peripheral: selects the DMA source request peripheral. */
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 u32 DMA_Channel_Des;        /* Destination peripheral:selects the DMA destination request peripheral. */
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} DMA_InitTypeDef;
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/* Exported constants --------------------------------------------------------*/
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    /* Interrupts masks */
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#define    DMA_ITMask_IE                0x4000  /* Interrupt error mask. */
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#define    DMA_ITMask_ITC               0x8000  /* Terminal count interrupt mask.*/
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#define    DMA_ITMask_ALL               0xC000  /* All DMA_Channelx interrupts enable/disable mask*/
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  /* Sources Request (used as masks) */
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#define   DMA_USB_RX_Mask                   0x0001
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#define   DMA_USB_TX_Mask                   0x0002
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#define   DMA_TIM0_Mask                 0x0004
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#define   DMA_TIM1_Mask                 0x0008
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#define   DMA_UART0_RX_Mask             0x0010
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#define   DMA_UART0_TX_Mask             0x0020
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#define   DMA_UART1_RX_Mask             0x0040
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#define   DMA_UART1_TX_Mask             0x0080
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#define   DMA_External_Req0_Mask        0x0100
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#define   DMA_External_Req1_Mask            0x0200
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#define   DMA_I2C0_Mask                 0x0400
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#define   DMA_I2C1_Mask                 0x0800
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#define   DMA_SSP0_RX_Mask                  0x1000
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#define   DMA_SSP0_TX_Mask                  0x2000
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#define   DMA_SSP1_RX_Mask                  0x4000
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#define   DMA_SSP1_TX_Mask                  0x8000
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/* Previleged Mode and user mode */
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#define   DMA_PrevilegedMode            0x10000000
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#define   DMA_UserMode                  0xEFFFFFFF
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/* Error and Terminal Count interrupts Status, after and before"raw" masking */
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#define   DMA_IS                        0x01
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#define   DMA_TCS                       0x02
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#define   DMA_ES                        0x03
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#define   DMA_TCRS                      0x04
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#define   DMA_ERS                       0x05
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/* interrupt clear: Terminal Count flag Clear and Error flag clear*/
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#define   DMA_TCC                       0x01
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#define   DMA_EC                        0x02
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/* channel index "0...7"*/
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#define   Channel0                      0
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#define   Channel1                      1
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#define   Channel2                      2
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#define   Channel3                      3
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#define   Channel4                      4
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#define   Channel5                      5
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#define   Channel6                      6
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#define   Channel7                      7
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/* Destination request selection: selects the DMA Destination request peripheral */
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#define   DMA_DES_USB_RX                0x00
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#define   DMA_DES_USB_TX                0x40
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#define   DMA_DES_TIM1              0x80
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#define   DMA_DES_TIM2              0xC0
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#define   DMA_DES_UART0_RX                  0x100
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#define   DMA_DES_UART0_TX                  0x140
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#define   DMA_DES_UART1_RX              0x180
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#define   DMA_DES_UART1_TX              0x1C0
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#define   DMA_DES_External_Req0     0x200
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#define   DMA_DES_External_Req1     0x240
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#define   DMA_DES_I2C0              0x280
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#define   DMA_DES_I2C1              0x2C0
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#define   DMA_DES_SSP0_RX               0x300
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#define   DMA_DES_SSP0_TX               0x340
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#define   DMA_DES_SSP1_RX               0x380
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#define   DMA_DES_SSP1_TX               0x3C0
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/* Source request selection: selects the DMA Source request peripheral */
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#define   DMA_SRC_USB_RX                0x00
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#define   DMA_SRC_USB_TX                0x02
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#define   DMA_SRC_TIM1              0x04
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#define   DMA_SRC_TIM2              0x06
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#define   DMA_SRC_UART0_RX                  0x08
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#define   DMA_SRC_UART0_TX                  0x0A
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#define   DMA_SRC_UART1_RX              0x0C
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#define   DMA_SRC_UART1_TX              0x0E
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#define   DMA_SRC_External_Req0     0x10
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#define   DMA_SRC_External_Req1     0x12
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#define   DMA_SRC_I2C0              0x14
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#define   DMA_SRC_I2C1              0x16
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#define   DMA_SRC_SSP0_RX               0x18
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#define   DMA_SRC_SSP0_TX               0x1A
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#define   DMA_SRC_SSP1_RX               0x1C
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#define   DMA_SRC_SSP1_TX               0x1E
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#define   DMA_FlowCntrlt0_DMA          0x00000000          /* transfer type :Memory-to-memory, flow controller:DMA */
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#define   DMA_FlowCntrl1_DMA           0x00000800          /* transfer type :Memory-to-peripheral, flow controller:DMA */
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#define   DMA_FlowCntrl2_DMA           0x00001000          /* transfer type :Peripheral-to-memory, flow controller:DMA */
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#define   DMA_FlowCntrl3_DMA           0x00001800          /* transfer type :Source peripheral-to-destination peripheral, flow controller:DMA */        
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#define   DMA_FlowCntrl_DestPerip          0x00002000      /* transfer type :Source peripheral-to-destination peripheral, flow controller:Destination peripheral */     
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#define   DMA_FlowCntrl_Perip1         0x00002800      /* transfer type :Memory-to-peripheral, flow controller:peripheral */            
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#define   DMA_FlowCntrl_Perip2         0x00003000      /* transfer  type : Peripheral-to-memory, flow controller:peripheral */  
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#define   DMA_FlowCntrl_SrcPerip           0x00003800      /* transfer  type :Source peripheral-to-destination peripheral, flow controller:Source peripheral */ 
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#define   DMA_SrcBst_1Data                0x00000000    /* Source Burst transfer request IS 1 Data ( DATA = Source transfer width ) */
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#define   DMA_SrcBst_4Data                0x00001000    /* Source Burst transfer request IS 4 Data  */
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#define   DMA_SrcBst_8Data                0x00002000    /* Source Burst transfer request IS 8 Data   */
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#define   DMA_SrcBst_16Data               0x00003000    /* Source Burst transfer request IS 16 Data  */
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#define   DMA_SrcBst_32Data               0x00004000    /* Source Burst transfer request IS 32 Data  */
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#define   DMA_SrcBst_64Data               0x00005000    /* Source Burst transfer request IS 64Data   */
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#define   DMA_SrcBst_128Data          0x00006000        /* Source Burst transfer request IS 128 Data */
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#define   DMA_SrcBst_256Data          0x00007000        /* Source Burst transfer request IS 256 Data */
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#define   DMA_DesBst_1Data                0x00000000    /*Destination Burst transfer request IS 1Data ( DATA = destination transfer width ) */
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#define   DMA_DesBst_4Data                0x00008000    /*Destination Burst transfer request IS 1 Data   */
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#define   DMA_DesBst_8Data                0x00010000    /*Destination Burst transfer request IS 4 Data   */
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#define   DMA_DesBst_16Data               0x00018000    /*Destination Burst transfer request IS 8 Data   */
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#define   DMA_DesBst_32Data               0x00020000    /*Destination Burst transfer request IS 16 Data  */
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#define   DMA_DesBst_64Data               0x00028000    /*Destination Burst transfer request IS 32 Data  */
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#define   DMA_DesBst_128Data          0x00030000        /*Destination Burst transfer request IS 128 Data */
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#define   DMA_DesBst_256Data          0x00038000        /*Destination Burst transfer request IS 256 Data */
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#define   DMA_SrcWidth_Byte               0x00000000  /* source Width is one Byte */
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#define   DMA_SrcWidth_HalfWord       0x00040000  /* source Width is one HalfWord */
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#define   DMA_SrcWidth_Word               0x00080000  /*  source Width is one Word  */
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#define   DMA_DesWidth_Byte               0x00000000  /* Destination Width is one Byte */
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#define   DMA_DesWidth_HalfWord       0x00200000  /* Destination Width is one HalfWord */
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#define   DMA_DesWidth_Word               0x00400000    /* Destination Width is one Word */
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/* Exported macro ------------------------------------------------------------*/
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/* Exported functions ------------------------------------------------------- */
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void DMA_DeInit(void);
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void DMA_Init(DMA_Channel_TypeDef * DMA_Channelx, DMA_InitTypeDef * DMA_InitStruct);
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void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct);
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void DMA_Cmd(FunctionalState NewState);
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void DMA_ITMaskConfig(DMA_Channel_TypeDef * DMA_Channelx, u16 DMA_ITMask, FunctionalState NewState);
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void DMA_ITConfig(DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState);
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FlagStatus DMA_GetChannelStatus(u8 ChannelIndx );
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ITStatus DMA_GetITStatus(u8 ChannelIndx,u8 DMA_ITReq);
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void DMA_ClearIT(u8 ChannelIndx,u8 DMA_ITClr);
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void DMA_SyncConfig(u16 DMA_SrcReq, FunctionalState NewState);
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FlagStatus DMA_GetSReq(u16 DMA_SrcReq);
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FlagStatus DMA_GetLSReq(u16 DMA_SrcReq);
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FlagStatus DMA_GetBReq(u16 DMA_SrcReq);
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FlagStatus DMA_GetLBReq(u16 DMA_SrcReq);
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FlagStatus DMA_GetChannelActiveStatus( DMA_Channel_TypeDef * DMA_Channelx);
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void DMA_SetSReq(u16 DMA_SrcReq);
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void DMA_SetLSReq(u16 DMA_SrcReq);
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void DMA_SetBReq(u16 DMA_SrcReq);
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void DMA_SetLBReq(u16 DMA_SrcReq);
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void DMA_ChannelCmd (DMA_Channel_TypeDef * DMA_Channelx,FunctionalState NewState);
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void DMA_ChannelHalt (DMA_Channel_TypeDef * DMA_Channelx,FunctionalState NewState);
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void DMA_ChannelBuffering (DMA_Channel_TypeDef * DMA_Channelx,FunctionalState NewState);
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void DMA_ChannelLockTrsf(DMA_Channel_TypeDef * DMA_Channelx,FunctionalState NewState);
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void DMA_ChannelCache(DMA_Channel_TypeDef * DMA_Channelx,FunctionalState NewState);
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void DMA_ChannelProt0Mode(DMA_Channel_TypeDef * DMA_Channelx,u32 Prot0Mode);
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void DMA_ChannelSRCIncConfig (DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState);
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void DMA_ChannelDESIncConfig (DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState);
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#endif /* __91x_DMA_H */
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/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/

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