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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [ARM9_STR91X_IAR/] [Library/] [include/] [91x_map.h] - Blame information for rev 613

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1 577 jeremybenn 
/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
2 
* File Name          : 91x_map.h
3 
* Author             : MCD Application Team
4 
* Date First Issued  : 05/18/2006 : Version 1.0
5 
* Description        : Peripherals registers definition and memory mapping.
6 
********************************************************************************
7 
* History:
8 
* 05/24/2006 : Version 1.1
9 
* 05/18/2006 : Version 1.0
10 
********************************************************************************
11 
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
12 
* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS
13 
* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
14 
* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
15 
* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
16 
* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
17 
*******************************************************************************/
18 
 
19 
/* Define to prevent recursive inclusion ------------------------------------ */
20 
#ifndef __91x_MAP_H
21 
#define __91x_MAP_H
22 
 
23 
#ifndef EXT
24 
  #define EXT extern
25 
#endif /* EXT */
26 
 
27 
/* Includes ------------------------------------------------------------------*/
28 
#include "91x_conf.h"
29 
#include "91x_type.h"
30 
 
31 
/******************************************************************************/
32 
/*                          IP registers structures                           */
33 
/******************************************************************************/
34 
 
35 
/*------------------------------------ FMI -----------------------------------*/
36 
 
37 
typedef struct
38 
{
39 
  vu32 BBSR;        /* Boot Bank Size Register                */
40 
  vu32 NBBSR;       /* Non-Boot Bank Size Register            */
41 
  vu32 EMPTY1;
42 
  vu32 BBADR;       /* Boot Bank Base Address Register        */
43 
  vu32 NBBADR;      /* Non-Boot Bank Base Address Register    */
44 
  vu32 EMPTY2;
45 
  vu32 CR;          /* Control Register                       */
46 
  vu32 SR;          /* Status Register                        */
47 
  vu32 BCE5ADDR;    /* BC Fifth Entry Target Address Register */
48 
} FMI_TypeDef;
49 
 
50 
/*----------------------  Analog to Digital Convertor ------------------------*/
51 
 
52 
typedef struct
53 
{
54 
  vu16 CR;         /* Control Register               */
55 
  vu16 EMPTY1;
56 
  vu16 CCR;        /* Channel Configuration Register */
57 
  vu16 EMPTY2;
58 
  vu16 HTR;        /* Higher Threshold Register      */
59 
  vu16 EMPTY3;
60 
  vu16 LTR;        /* Lower Threshold Register       */
61 
  vu16 EMPTY4;
62 
  vu16 CRR;        /* Compare Result Register        */
63 
  vu16 EMPTY5;
64 
  vu16 DR0;        /* Data Register for Channel 0    */
65 
  vu16 EMPTY6;
66 
  vu16 DR1;        /* Data Register for Channel 1    */
67 
  vu16 EMPTY7;
68 
  vu16 DR2;        /* Data Register for Channel 2    */
69 
  vu16 EMPTY8;
70 
  vu16 DR3;        /* Data Register for Channel 3    */
71 
  vu16 EMPTY9;
72 
  vu16 DR4;        /* Data Register for Channel 4    */
73 
  vu16 EMPTY10;
74 
  vu16 DR5;        /* Data Register for Channel 5    */
75 
  vu16 EMPTY11;
76 
  vu16 DR6;        /* Data Register for Channel 6    */
77 
  vu16 EMPTY12;
78 
  vu16 DR7;        /* Data Register for Channel 7    */
79 
  vu16 EMPTY13;
80 
  vu16 PRS;        /* Prescaler Value Register       */
81 
  vu16 EMPTY14;
82 
} ADC_TypeDef;
83 
 
84 
/*--------------------- AHB APB BRIDGE registers strcture --------------------*/
85 
 
86 
typedef struct
87 
{
88 
  vu32 BSR;        /* Bridge Status Register            */
89 
  vu32 BCR;        /* Bridge Configuration Register     */
90 
  vu32 PAER;       /* Peripheral Address Error register */
91 
} AHBAPB_TypeDef;
92 
 
93 
/*--------------- Controller Area Network Interface Register -----------------*/
94 
 
95 
typedef struct
96 
{
97 
  vu16 CRR;                     /* IFn Command request Register       */
98 
  vu16 EMPTY1;
99 
  vu16 CMR;                     /* IFn Command Mask Register          */
100 
  vu16 EMPTY2;
101 
  vu16 M1R;                     /* IFn Message Mask 1 Register        */
102 
  vu16 EMPTY3;
103 
  vu16 M2R;                     /* IFn Message Mask 2 Register        */
104 
  vu16 EMPTY4;
105 
  vu16 A1R;                     /* IFn Message Arbitration 1 Register */
106 
  vu16 EMPTY5;
107 
  vu16 A2R;                     /* IFn Message Arbitration 2 Register */
108 
  vu16 EMPTY6;
109 
  vu16 MCR;                     /* IFn Message Control Register       */
110 
  vu16 EMPTY7;
111 
  vu16 DA1R;                    /* IFn DATA A 1 Register              */
112 
  vu16 EMPTY8;
113 
  vu16 DA2R;                    /* IFn DATA A 2 Register              */
114 
  vu16 EMPTY9;
115 
  vu16 DB1R;                    /* IFn DATA B 1 Register              */
116 
  vu16 EMPTY10;
117 
  vu16 DB2R;                    /* IFn DATA B 2 Register              */
118 
  vu16 EMPTY11[27];
119 
} CAN_MsgObj_TypeDef;
120 
 
121 
typedef struct
122 
{
123 
  vu16 CR;              /* Control Register                */
124 
  vu16 EMPTY1;
125 
  vu16 SR;              /* Status Register                 */
126 
  vu16 EMPTY2;
127 
  vu16 ERR;             /* Error counter Register          */
128 
  vu16 EMPTY3;
129 
  vu16 BTR;             /* Bit Timing Register             */
130 
  vu16 EMPTY4;
131 
  vu16 IDR;             /* Interrupt Identifier Register   */
132 
  vu16 EMPTY5;
133 
  vu16 TESTR;           /* Test Register                   */
134 
  vu16 EMPTY6;
135 
  vu16 BRPR;            /* BRP Extension Register          */
136 
  vu16 EMPTY7[3];
137 
  CAN_MsgObj_TypeDef sMsgObj[2];
138 
  vu16 EMPTY8[16];
139 
  vu16 TXR1R;           /* Transmission request 1 Register */
140 
  vu16 EMPTY9;
141 
  vu16 TXR2R;           /* Transmission Request 2 Register */
142 
  vu16 EMPTY10[13];
143 
  vu16 ND1R;            /* New Data 1 Register             */
144 
  vu16 EMPTY11;
145 
  vu16 ND2R;            /* New Data 2 Register             */
146 
  vu16 EMPTY12[13];
147 
  vu16 IP1R;            /* Interrupt Pending 1 Register    */
148 
  vu16 EMPTY13;
149 
  vu16 IP2R;            /* Interrupt Pending 2 Register    */
150 
  vu16 EMPTY14[13];
151 
  vu16 MV1R;            /* Message Valid 1 Register        */
152 
  vu16 EMPTY15;
153 
  vu16 MV2R;            /* Message VAlid 2 Register        */
154 
  vu16 EMPTY16;
155 
} CAN_TypeDef;
156 
 
157 
/*----------------------- System Control Unit---------------------------------*/
158 
 
159 
typedef struct
160 
{
161 
  vu32 CLKCNTR;    /* Clock Control Register                       */
162 
  vu32 PLLCONF;    /* PLL Configuration Register                   */
163 
  vu32 SYSSTATUS;  /* System Status Register                       */
164 
  vu32 PWRMNG;     /* Power Management Register                    */
165 
  vu32 ITCMSK;     /* Interrupt Mask Register                      */
166 
  vu32 PCGRO;      /* Peripheral Clock Gating Register 0           */
167 
  vu32 PCGR1;      /* Peripheral Clock Gating Register 1           */
168 
  vu32 PRR0;       /* Peripheral Reset Register 0                  */
169 
  vu32 PRR1;       /* Peripheral Reset Register 1                  */
170 
  vu32 MGR0;       /* Idle Mode Mask Gating Register 0             */
171 
  vu32 MGR1;       /* Idle Mode Mask Gating Register 1             */
172 
  vu32 PECGR0;     /* Peripheral Emulation Clock Gating Register 0 */
173 
  vu32 PECGR1;     /* Peripheral Emulation Clock Gating Register 1 */
174 
  vu32 SCR0;       /* System Configuration Register 0              */
175 
  vu32 SCR1;       /* System Configuration Register 1              */
176 
  vu32 SCR2;       /* System Configuration Register 2              */
177 
  u32 EMPTY1;
178 
  vu32 GPIOOUT[8];   /* GPIO Output Registers                      */
179 
  vu32 GPIOIN[8];    /* GPIO Input Registers                       */
180 
  vu32 GPIOTYPE[10]; /* GPIO Type Registers                        */
181 
  vu32 GPIOEMI;      /* GPIO EMI Selector Register                 */
182 
  vu32 WKUPSEL;      /* Wake-Up Selection Register                 */
183 
  u32 EMPTY2[2];
184 
  vu32 GPIOANA;      /* GPIO Analag mode Register                  */
185 
} SCU_TypeDef;
186 
 
187 
/*------------------------- DMA Channelx Registers ---------------------------*/
188 
 
189 
typedef struct
190 
{
191 
  vu32 SRC;      /* Channelx Source Address Register      */
192 
  vu32 DES;      /* Channelx Destination Address Register */
193 
  vu32 LLI;      /* Channelx Lincked List Item Register   */
194 
  vu32 CC;       /* Channelx Contol Register              */
195 
  vu32 CCNF;     /* Channelx Configuration Register       */
196 
} DMA_Channel_TypeDef;
197 
 
198 
/* x can be ,0,1,2,3,4,5,6 or 7. There are eight Channels AHB BUS Master */
199 
 
200 
/*----------------------------- DMA Controller -------------------------------*/
201 
 
202 
typedef struct
203 
{
204 
  vu32 ISR;         /* Interrupt Status Register                    */
205 
  vu32 TCISR;       /* Terminal Count Interrupt Status Register     */
206 
  vu32 TCICR;       /* Terminal CountInterrupt Clear Register       */
207 
  vu32 EISR;        /* Error Interrupt Status Register              */
208 
  vu32 EICR;        /* Error Interrupt Clear Register               */
209 
  vu32 TCRISR;      /* Terminal Count Raw Interrupt Status Register */
210 
  vu32 ERISR;       /* Raw Error Interrupt Status Register          */
211 
  vu32 ENCSR;       /* Enabled Channel Status Register              */
212 
  vu32 SBRR;        /* Software Burst Request Register              */
213 
  vu32 SSRR;        /* Software Single Request Register             */
214 
  vu32 SLBRR;       /* Software Last Burst Request Register         */
215 
  vu32 SLSRR;       /* Software Last Single Request Register        */
216 
  vu32 CNFR;        /* Configuration Register                       */
217 
  vu32 SYNR;        /* Syncronization Register                      */
218 
} DMA_TypeDef;
219 
 
220 
/*--------------------------------- TIM Timer --------------------------------*/
221 
 
222 
typedef struct
223 
{
224 
  vu16 IC1R;        /* Input Capture 1 Register  */
225 
  vu16 EMPTY1;
226 
  vu16 IC2R;        /* Input Capture 2 Register  */
227 
  vu16 EMPTY2;
228 
  vu16 OC1R;        /* Output Compare 1 Register */
229 
  vu16 EMPTY3;
230 
  vu16 OC2R;        /* Output Compare 2 Register */
231 
  vu16 EMPTY4;
232 
  vu16 CNTR;        /* Counter Register          */
233 
  vu16 EMPTY5;
234 
  vu16 CR1;         /* Control Register 1        */
235 
  vu16 EMPTY6;
236 
  vu16 CR2;         /* Control Register 2        */
237 
  vu16 EMPTY7;
238 
  vu16 SR;          /* Status Register           */
239 
  vu16 EMPTY8;
240 
} TIM_TypeDef;
241 
 
242 
/*---------------------------- EMI Bankx Registers ---------------------------*/
243 
 
244 
typedef struct
245 
{
246 
  vu32 ICR;      /* Bankx   Idle Cycle Control Register                    */
247 
  vu32 RCR;      /* Bankx   Read Wait State Control Register               */
248 
  vu32 WCR;      /* Bankx   Write Wait State Control Register              */
249 
  vu32 OECR;     /* Bankx   Output Enable Assertion Delay Control Register */
250 
  vu32 WECR;     /* Bankx   Write Enable Assertion Delay Control Register  */
251 
  vu32 BCR;      /* Bankx   Control Register                               */
252 
 } EMI_Bank_TypeDef;
253 
 
254 
/*---------------------------- Ethernet Controller ---------------------------*/
255 
 
256 
/* MAC Registers */
257 
typedef struct
258 
{
259 
  vu32 MCR;      /* ENET Control Register             */
260 
  vu32 MAH;      /* ENET Address High Register        */
261 
  vu32 MAL;      /* ENET Address Low Register         */
262 
  vu32 MCHA;     /* Multicast Address High Register   */
263 
  vu32 MCLA;     /* Multicast Address Low Register    */
264 
  vu32 MIIA;     /* MII Address Register              */
265 
  vu32 MIID;     /* MII Data Register                 */
266 
  vu32 MCF;      /* ENET Control Frame Register       */
267 
  vu32 VL1;      /* VLAN1 Register                    */
268 
  vu32 VL2;      /* VLAN2 register                    */
269 
  vu32 MTS;      /* ENET Transmission Status Register */
270 
  vu32 MRS;      /* ENET Reception Status Register    */
271 
} ENET_MAC_TypeDef;
272 
 
273 
/* DMA Registers */
274 
typedef struct
275 
{
276 
  vu32 SCR;           /* DMA Status and Control Register         */
277 
  vu32 IER;           /* DMA Interrupt Sources Enable Register   */
278 
  vu32 ISR;           /* DMA Interrupt Status Register           */
279 
  vu32 CCR;           /* Clock Control Relation : HCLK, PCLK and
280 
                         ENET_CLK phase relations                */
281 
  vu32 RXSTR;         /* Rx DMA start Register                   */
282 
  vu32 RXCR;          /* Rx DMA Control Register                 */
283 
  vu32 RXSAR;         /* Rx DMA Base Address Register            */
284 
  vu32 RXNDAR;        /* Rx DMA Next Descriptor Address Register */
285 
  vu32 RXCAR;         /* Rx DMA Current Address Register         */
286 
  vu32 RXCTCR;        /* Rx DMA Current Transfer Count Register  */
287 
  vu32 RXTOR;         /* Rx DMA FIFO Time Out Register           */
288 
  vu32 RXSR;          /* Rx DMA FIFO Status Register             */
289 
  vu32 TXSTR;         /* Tx DMA start Register                   */
290 
  vu32 TXCR;          /* Tx DMA Control Register                 */
291 
  vu32 TXSAR;         /* Tx DMA Base Address Register            */
292 
  vu32 TXNDAR;        /* Tx DMA Next Descriptor Address Register */
293 
  vu32 TXCAR;         /* Tx DMA Current Address Register         */
294 
  vu32 TXTCR;         /* Tx DMA Current Transfer Count Register  */
295 
  vu32 TXTOR;         /* Tx DMA FIFO Time Out Register           */
296 
  vu32 TXSR;          /* Tx DMA FIFO Status Register             */
297 
} ENET_DMA_TypeDef;
298 
 
299 
/*------------------------------------- GPIO ---------------------------------*/
300 
 
301 
typedef struct
302 
{
303 
  vu8 DR[1021];     /* Data Register                    */
304 
  vu32 DDR;         /* Data Direction Register          */
305 
} GPIO_TypeDef;
306 
 
307 
/*-------------------------------- I2C interface -----------------------------*/
308 
 
309 
typedef struct
310 
{
311 
  vu8  CR;                 /* Control Register                */
312 
  vu8  EMPTY1[3];
313 
  vu8  SR1;                /* Status Register 1               */
314 
  vu8  EMPTY2[3];
315 
  vu8  SR2;                /* Status Register 2               */
316 
  vu8  EMPTY3[3];
317 
  vu8  CCR;                /* Clock Control Register          */
318 
  vu8  EMPTY4[3];
319 
  vu8  OAR1;               /* Own Address Register 1          */
320 
  vu8  EMPTY5[3];
321 
  vu8  OAR2;               /* Own Address Register 2          */
322 
  vu8  EMPTY6[3];
323 
  vu8  DR;                 /* Data Register                   */
324 
  vu8  EMPTY7[3];
325 
  vu8  ECCR;               /* Extended Clock Control Register */
326 
  vu8  EMPTY8[3];
327 
} I2C_TypeDef;
328 
 
329 
/*------------------------------------- VIC ----------------------------------*/
330 
 
331 
typedef struct
332 
{
333 
  vu32 ISR;                /* IRQ Status Register               */
334 
  vu32 FSR;                /* FIQ Status Register               */
335 
  vu32 RINTSR;             /* Raw Interrupt Status Register     */
336 
  vu32 INTSR;              /* Interrupt Select Register         */
337 
  vu32 INTER;              /* Interrupt Enable Register         */
338 
  vu32 INTECR;             /* Interrupt Enable Clear Register   */
339 
  vu32 SWINTR;             /* Software Interrupt Register       */
340 
  vu32 SWINTCR;            /* Software Interrupt clear Register */
341 
  vu32 PER;                /* Protection Enable Register        */
342 
  vu32 EMPTY1[3];
343 
  vu32 VAR;                /* Vector Address Register           */
344 
  vu32 DVAR;               /* Default Vector Address Register   */
345 
  vu32 EMPTY2[50];
346 
  vu32 VAiR[16];           /* Vector Address 0-15 Register      */
347 
  vu32 EMPTY3[48];
348 
  vu32 VCiR[16];           /* Vector Control 0-15 Register      */
349 
} VIC_TypeDef;
350 
 
351 
/*-------------------------------- Motor Control -----------------------------*/
352 
 
353 
typedef struct
354 
{
355 
  vu16 TCPT;          /* Tacho Capture Register           */
356 
  vu16 EMPTY1;
357 
  vu16 TCMP;          /* Tacho Compare Register           */
358 
  vu16 EMPTY2;
359 
  vu16 IPR;           /* Input Pending Register           */
360 
  vu16 EMPTY3;
361 
  vu16 TPRS;          /* Tacho Prescaler Register         */
362 
  vu16 EMPTY4;
363 
  vu16 CPRS;          /* PWM Counter Prescaler Register   */
364 
  vu16 EMPTY5;
365 
  vu16 REP;           /* Repetition Counter Register      */
366 
  vu16 EMPTY6;
367 
  vu16 CMPW;          /* Compare Phase W Preload Register */
368 
  vu16 EMPTY7;
369 
  vu16 CMPV;          /* Compare Phase V Preload Register */
370 
  vu16 EMPTY8;
371 
  vu16 CMPU;          /* Compare Phase U Preload Register */
372 
  vu16 EMPTY9;
373 
  vu16 CMP0;          /* Compare 0 Preload Register       */
374 
  vu16 EMPTY10;
375 
  vu16 PCR0;          /* Peripheral Control Register 0    */
376 
  vu16 EMPTY11;
377 
  vu16 PCR1;          /* Peripheral Control Register 1    */
378 
  vu16 EMPTY12;
379 
  vu16 PCR2;          /* Peripheral Control Register 2    */
380 
  vu16 EMPTY13;
381 
  vu16 PSR;           /* Polarity Selection Register      */
382 
  vu16 EMPTY14;
383 
  vu16 OPR;           /* Output Peripheral Register       */
384 
  vu16 EMPTY15;
385 
  vu16 IMR;           /* Interrupt Mask Register          */
386 
  vu16 EMPTY16;
387 
  vu16 DTG;           /* Dead Time Generator Register     */
388 
  vu16 EMPTY17;
389 
  vu16 ESC;           /* Emergency Stop Clear Register    */
390 
  vu16 EMPTY18;
391 
}MC_TypeDef;
392 
 
393 
/*------------------------------------- RTC ----------------------------------*/
394 
 
395 
typedef struct
396 
{
397 
  vu32 TR;         /* Time Register       */
398 
  vu32 DTR;        /* Date Register       */
399 
  vu32 ATR;        /* Alarm time Register */
400 
  vu32 CR;         /* Control Register    */
401 
  vu32 SR;         /* Status Register     */
402 
  vu32 MILR;       /* Millisec Register   */
403 
}RTC_TypeDef;
404 
 
405 
/*------------------------------------- SSP ----------------------------------*/
406 
 
407 
typedef struct
408 
{
409 
  vu16 CR0;        /* Control Register 1                   */
410 
  vu16 EMPTY1;
411 
  vu16 CR1;        /* Control Register 2                   */
412 
  vu16 EMPTY2;
413 
  vu16 DR;         /* Data Register                        */
414 
  vu16 EMPTY3;
415 
  vu16 SR;         /* Status Register                      */
416 
  vu16 EMPTY4;
417 
  vu16 PR;         /* Clock Prescale Register              */
418 
  vu16 EMPTY5;
419 
  vu16 IMSCR;      /* Interrupt Mask Set or Clear Register */
420 
  vu16 EMPTY6;
421 
  vu16 RISR;       /* Raw Interrupt Status Register        */
422 
  vu16 EMPTY7;
423 
  vu16 MISR;       /* Masked Interrupt Status Register     */
424 
  vu16 EMPTY8;
425 
  vu16 ICR;        /* Interrupt Clear Register             */
426 
  vu16 EMPTY9;
427 
  vu16 DMACR;      /* DMA Control Register                 */
428 
  vu16 EMPTY10;
429 
}SSP_TypeDef;
430 
 
431 
/*------------------------------------ UART ----------------------------------*/
432 
 
433 
typedef struct
434 
{
435 
  vu16 DR;        /* Data Register                                               */
436 
  vu16 EMPTY1;
437 
  vu16 RSECR;     /* Receive Status Register (read)/Error Clear Register (write) */
438 
  vu16 EMPTY2[9];
439 
  vu16 FR;        /* Flag Register                                               */
440 
  vu16 EMPTY3[3];
441 
  vu16 ILPR;      /* IrDA Low-Power counter Register                             */
442 
  vu16 EMPTY4;
443 
  vu16 IBRD;      /* Integer Baud Rate Divisor Register                          */
444 
  vu16 EMPTY5;
445 
  vu16 FBRD;      /* Fractional Baud Rate Divisor Register                       */
446 
  vu16 EMPTY6;
447 
  vu16 LCR;       /* Line Control Register, High byte                            */
448 
  vu16 EMPTY7;
449 
  vu16 CR;        /* Control Register                                            */
450 
  vu16 EMPTY8;
451 
  vu16 IFLS;      /* Interrupt FIFO Level Select Register                        */
452 
  vu16 EMPTY9;
453 
  vu16 IMSC;      /* Interrupt Mask Set/Clear Register                           */
454 
  vu16 EMPTY10;
455 
  vu16 RIS;       /* Raw Interrupt Status Register                               */
456 
  vu16 EMPTY11;
457 
  vu16 MIS;       /* Masked Interrupt Status Register                            */
458 
  vu16 EMPTY12;
459 
  vu16 ICR;       /* Interrupt Clear Register                                    */
460 
  vu16 EMPTY13;
461 
  vu16 DMACR;     /* DMA Control Register                                        */
462 
  vu16 EMPTY14;
463 
}UART_TypeDef;
464 
 
465 
/*------------------------------- Wake-up System -----------------------------*/
466 
 
467 
typedef struct
468 
{
469 
  vu32  CTRL;   /* Control Register            */
470 
  vu32  MR;     /* Mask Register               */
471 
  vu32  TR;     /* Trigger Register            */
472 
  vu32  PR;     /* Pending Register            */
473 
  vu32  INTR;   /* Software Interrupt Register */
474 
} WIU_TypeDef;
475 
 
476 
/*------------------------------- WatchDog Timer -----------------------------*/
477 
 
478 
typedef struct
479 
{
480 
  vu16 CR;        /* Control Register        */
481 
  vu16 EMPTY1;
482 
  vu16 PR;        /* Presclar Register       */
483 
  vu16 EMPTY2;
484 
  vu16 VR;        /* Pre-load Value Register */
485 
  vu16 EMPTY3;
486 
  vu16 CNT;       /* Counter Register        */
487 
  vu16 EMPTY4;
488 
  vu16 SR;        /* Status Register         */
489 
  vu16 EMPTY5;
490 
  vu16 MR;        /* Mask Register           */
491 
  vu16 EMPTY6;
492 
  vu16 KR;        /* Key Register            */
493 
  vu16 EMPTY7;
494 
} WDG_TypeDef;
495 
 
496 
/*******************************************************************************
497 
*                         Memory Mapping of STR91x                             *
498 
*******************************************************************************/
499 
 
500 
#define AHB_APB_BRDG0_U    (0x58000000) /* AHB/APB Bridge 0 UnBuffered Space */
501 
#define AHB_APB_BRDG0_B    (0x48000000) /* AHB/APB Bridge 0 Buffered Space   */
502 
 
503 
#define AHB_APB_BRDG1_U    (0x5C000000) /* AHB/APB Bridge 1 UnBuffered Space */
504 
#define AHB_APB_BRDG1_B    (0x4C000000) /* AHB/APB Bridge 1 Buffered Space   */
505 
 
506 
#define AHB_EMI_U          (0x74000000) /* EMI UnBuffered Space */
507 
#define AHB_EMI_B          (0x64000000) /* EMI Buffered Space   */
508 
 
509 
#define AHB_DMA_U          (0x78000000) /* DMA UnBuffered Space */
510 
#define AHB_DMA_B          (0x68000000) /* DMA Buffered Space   */
511 
 
512 
#define AHB_ENET_MAC_U     (0x7C000400) /* ENET_MAC  UnBuffered Space */
513 
#define AHB_ENET_MAC_B     (0x6C000400) /* ENET_MAC  Buffered Space   */
514 
 
515 
#define AHB_ENET_DMA_U     (0x7C000000) /* ENET_DMA  Unbuffered Space */
516 
#define AHB_ENET_DMA_B     (0x6C000000) /* ENET_DMA  Buffered Space    */
517 
 
518 
#define AHB_VIC1_U         (0xFC000000) /* Secondary VIC1 UnBuffered Space */
519 
#define AHB_VIC0_U         (0xFFFFF000) /* Primary VIC0 UnBuffered Space   */
520 
 
521 
#define AHB_FMI_U          (0x54000000) /* FMI Unbuffered Space */
522 
#define AHB_FMI_B          (0x44000000) /* FMI buffered Space   */
523 
 
524 
/*******************************************************************************
525 
*                Addresses related to the VICs' peripherals                    *
526 
*******************************************************************************/
527 
 
528 
#define VIC0_BASE          (AHB_VIC0_U)
529 
#define VIC1_BASE          (AHB_VIC1_U)
530 
 
531 
/*******************************************************************************
532 
*                    Addresses related to the EMI banks                        *
533 
*******************************************************************************/
534 
 
535 
#define AHB_EMIB3_OFST      (0x00000040)   /* Offset of EMI bank3 */
536 
#define AHB_EMIB2_OFST      (0x00000020)   /* Offset of EMI bank2 */
537 
#define AHB_EMIB1_OFST      (0x00000000)   /* Offset of EMI bank1 */
538 
#define AHB_EMIB0_OFST      (0x000000E0)   /* Offset of EMI bank0 */
539 
 
540 
/*******************************************************************************
541 
*                 Addresses related to the DMA peripheral                      *
542 
*******************************************************************************/
543 
 
544 
#define AHB_DMA_Channel0_OFST    (0x00000100)   /* Offset of Channel 0 */
545 
#define AHB_DMA_Channel1_OFST    (0x00000120)   /* Offset of Channel 1 */
546 
#define AHB_DMA_Channel2_OFST    (0x00000140)   /* Offset of Channel 2 */
547 
#define AHB_DMA_Channel3_OFST    (0x00000160)   /* Offset of Channel 3 */
548 
#define AHB_DMA_Channel4_OFST    (0x00000180)   /* Offset of Channel 4 */
549 
#define AHB_DMA_Channel5_OFST    (0x000001A0)   /* Offset of Channel 5 */
550 
#define AHB_DMA_Channel6_OFST    (0x000001C0)   /* Offset of Channel 6 */
551 
#define AHB_DMA_Channel7_OFST    (0x000001E0)   /* Offset of Channel 7 */
552 
 
553 
/*******************************************************************************
554 
*                 Addresses related to the APB0 sub-system                     *
555 
*******************************************************************************/
556 
 
557 
#define APB_WIU_OFST       (0x00001000)   /* Offset of WIU   */
558 
#define APB_TIM0_OFST      (0x00002000)   /* Offset of TIM0  */
559 
#define APB_TIM1_OFST      (0x00003000)   /* Offset of TIM1  */
560 
#define APB_TIM2_OFST      (0x00004000)   /* Offset of TIM2  */
561 
#define APB_TIM3_OFST      (0x00005000)   /* Offset of TIM3  */
562 
#define APB_GPIO0_OFST     (0x00006000)   /* Offset of GPIO0 */
563 
#define APB_GPIO1_OFST     (0x00007000)   /* Offset of GPIO1 */
564 
#define APB_GPIO2_OFST     (0x00008000)   /* Offset of GPIO2 */
565 
#define APB_GPIO3_OFST     (0x00009000)   /* Offset of GPIO3 */
566 
#define APB_GPIO4_OFST     (0x0000A000)   /* Offset of GPIO4 */
567 
#define APB_GPIO5_OFST     (0x0000B000)   /* Offset of GPIO5 */
568 
#define APB_GPIO6_OFST     (0x0000C000)   /* Offset of GPIO6 */
569 
#define APB_GPIO7_OFST     (0x0000D000)   /* Offset of GPIO7 */
570 
#define APB_GPIO8_OFST     (0x0000E000)   /* Offset of GPIO8 */
571 
#define APB_GPIO9_OFST     (0x0000F000)   /* Offset of GPIO9 */
572 
 
573 
/*******************************************************************************
574 
*                   Addresses related to the APB1 sub-system                   *
575 
*******************************************************************************/
576 
 
577 
#define APB_RTC_OFST       (0x00001000) /* Offset of RTC               */
578 
#define APB_SCU_OFST       (0x00002000) /* Offset of System Controller */
579 
#define APB_MC_OFST        (0x00003000) /* Offset of Motor Control     */
580 
#define APB_UART0_OFST     (0x00004000) /* Offset of UART0             */
581 
#define APB_UART1_OFST     (0x00005000) /* Offset of UART1             */
582 
#define APB_UART2_OFST     (0x00006000) /* Offset of UART2             */
583 
#define APB_SSP0_OFST      (0x00007000) /* Offset of SSP0              */
584 
#define APB_SSP1_OFST      (0x00008000) /* Offset of SSPI              */
585 
#define APB_CAN_OFST       (0x00009000) /* Offset of CAN               */
586 
#define APB_ADC_OFST       (0x0000A000) /* Offset of ADC               */
587 
#define APB_WDG_OFST       (0x0000B000) /* Offset of WDG               */
588 
#define APB_I2C0_OFST      (0x0000C000) /* Offset of I2C0              */
589 
#define APB_I2C1_OFST      (0x0000D000) /* Offset of I2C1              */
590 
 
591 
/*----------------------------------------------------------------------------*/
592 
/*----------------------------- Unbuffered Mode ------------------------------*/
593 
/*----------------------------------------------------------------------------*/
594 
 
595 
#ifndef Buffered
596 
 
597 
/*******************************************************************************
598 
*                  AHBAPB peripheral Unbuffered Base Address                   *
599 
*******************************************************************************/
600 
 
601 
#define AHBAPB0_BASE           (AHB_APB_BRDG0_U)
602 
#define AHBAPB1_BASE           (AHB_APB_BRDG1_U)
603 
 
604 
/*******************************************************************************
605 
*                  ENET peripheral Unbuffered Base Address                     *
606 
*******************************************************************************/
607 
 
608 
#define ENET_MAC_BASE          (AHB_ENET_MAC_U)
609 
#define ENET_DMA_BASE          (AHB_ENET_DMA_U)
610 
 
611 
/*******************************************************************************
612 
*                  DMA peripheral Unbuffered Base Address                      *
613 
*******************************************************************************/
614 
 
615 
#define DMA_BASE           (AHB_DMA_U)
616 
 
617 
/*******************************************************************************
618 
*                  EMI peripheral Unbuffered Base Address                      *
619 
*******************************************************************************/
620 
 
621 
#define EMI_BASE           (AHB_EMI_U)
622 
 
623 
/*******************************************************************************
624 
*                  FMI peripheral Unbuffered Base Address                      *
625 
*******************************************************************************/
626 
 
627 
#define FMI_BASE           (AHB_FMI_U)
628 
 
629 
 
630 
#else /* Buffered */
631 
 
632 
/*----------------------------------------------------------------------------*/
633 
/*------------------------------ Buffered Mode -------------------------------*/
634 
/*----------------------------------------------------------------------------*/
635 
 
636 
/*******************************************************************************
637 
*                   AHBAPB peripheral Buffered Base Address                    *
638 
*******************************************************************************/
639 
 
640 
#define AHBAPB0_BASE           (AHB_APB_BRDG0_B)
641 
#define AHBAPB1_BASE           (AHB_APB_BRDG1_B)
642 
 
643 
/*******************************************************************************
644 
*                  ENET peripheral Unbuffered Base Address                     *
645 
*******************************************************************************/
646 
 
647 
#define ENET_MAC_BASE          (AHB_ENET_MAC_B)
648 
#define ENET_DMA_BASE          (AHB_ENET_DMA_B)
649 
 
650 
/*******************************************************************************
651 
*                    DMA peripheral Buffered Base Address                      *
652 
*******************************************************************************/
653 
 
654 
#define DMA_BASE           (AHB_DMA_B)
655 
 
656 
/*******************************************************************************
657 
*                      EMI peripheral Buffered Base Address                    *
658 
*******************************************************************************/
659 
 
660 
#define EMI_BASE           (AHB_EMI_B)
661 
 
662 
/*******************************************************************************
663 
*                      FMI peripheral Buffered Base Address                    *
664 
*******************************************************************************/
665 
 
666 
#define FMI_BASE           (AHB_FMI_B)
667 
 
668 
#endif /* Buffered */
669 
 
670 
/*******************************************************************************
671 
*                          DMA channels Base Address                           *
672 
*******************************************************************************/
673 
#define DMA_Channel0_BASE  (DMA_BASE + AHB_DMA_Channel0_OFST)
674 
#define DMA_Channel1_BASE  (DMA_BASE + AHB_DMA_Channel1_OFST)
675 
#define DMA_Channel2_BASE  (DMA_BASE + AHB_DMA_Channel2_OFST)
676 
#define DMA_Channel3_BASE  (DMA_BASE + AHB_DMA_Channel3_OFST)
677 
#define DMA_Channel4_BASE  (DMA_BASE + AHB_DMA_Channel4_OFST)
678 
#define DMA_Channel5_BASE  (DMA_BASE + AHB_DMA_Channel5_OFST)
679 
#define DMA_Channel6_BASE  (DMA_BASE + AHB_DMA_Channel6_OFST)
680 
#define DMA_Channel7_BASE  (DMA_BASE + AHB_DMA_Channel7_OFST)
681 
 
682 
/*******************************************************************************
683 
*                     EMI Banks peripheral Base Address                        *
684 
*******************************************************************************/
685 
 
686 
#define EMI_Bank0_BASE  (EMI_BASE + AHB_EMIB0_OFST)
687 
#define EMI_Bank1_BASE  (EMI_BASE + AHB_EMIB1_OFST)
688 
#define EMI_Bank2_BASE  (EMI_BASE + AHB_EMIB2_OFST)
689 
#define EMI_Bank3_BASE  (EMI_BASE + AHB_EMIB3_OFST)
690 
 
691 
/*******************************************************************************
692 
*                     APB0 Peripherals' Base addresses                         *
693 
*******************************************************************************/
694 
 
695 
#define WIU_BASE           (AHBAPB0_BASE + APB_WIU_OFST)
696 
#define TIM0_BASE          (AHBAPB0_BASE + APB_TIM0_OFST)
697 
#define TIM1_BASE          (AHBAPB0_BASE + APB_TIM1_OFST)
698 
#define TIM2_BASE          (AHBAPB0_BASE + APB_TIM2_OFST)
699 
#define TIM3_BASE          (AHBAPB0_BASE + APB_TIM3_OFST)
700 
#define GPIO0_BASE         (AHBAPB0_BASE + APB_GPIO0_OFST)
701 
#define GPIO1_BASE         (AHBAPB0_BASE + APB_GPIO1_OFST)
702 
#define GPIO2_BASE         (AHBAPB0_BASE + APB_GPIO2_OFST)
703 
#define GPIO3_BASE         (AHBAPB0_BASE + APB_GPIO3_OFST)
704 
#define GPIO4_BASE         (AHBAPB0_BASE + APB_GPIO4_OFST)
705 
#define GPIO5_BASE         (AHBAPB0_BASE + APB_GPIO5_OFST)
706 
#define GPIO6_BASE         (AHBAPB0_BASE + APB_GPIO6_OFST)
707 
#define GPIO7_BASE         (AHBAPB0_BASE + APB_GPIO7_OFST)
708 
#define GPIO8_BASE         (AHBAPB0_BASE + APB_GPIO8_OFST)
709 
#define GPIO9_BASE         (AHBAPB0_BASE + APB_GPIO9_OFST)
710 
 
711 
/*******************************************************************************
712 
*                      APB1 Peripherals' Base addresses                        *
713 
*******************************************************************************/
714 
 
715 
#define RTC_BASE           (AHBAPB1_BASE + APB_RTC_OFST)
716 
#define SCU_BASE           (AHBAPB1_BASE + APB_SCU_OFST)
717 
#define MC_BASE            (AHBAPB1_BASE + APB_MC_OFST)
718 
#define UART0_BASE         (AHBAPB1_BASE + APB_UART0_OFST)
719 
#define UART1_BASE         (AHBAPB1_BASE + APB_UART1_OFST)
720 
#define UART2_BASE         (AHBAPB1_BASE + APB_UART2_OFST)
721 
#define SSP0_BASE          (AHBAPB1_BASE + APB_SSP0_OFST)
722 
#define SSP1_BASE          (AHBAPB1_BASE + APB_SSP1_OFST)
723 
#define CAN_BASE           (AHBAPB1_BASE + APB_CAN_OFST)
724 
#define ADC_BASE           (AHBAPB1_BASE + APB_ADC_OFST)
725 
#define WDG_BASE           (AHBAPB1_BASE + APB_WDG_OFST)
726 
#define I2C0_BASE          (AHBAPB1_BASE + APB_I2C0_OFST)
727 
#define I2C1_BASE          (AHBAPB1_BASE + APB_I2C1_OFST)
728 
 
729 
/*******************************************************************************
730 
*                                IPs' declaration                              *
731 
*******************************************************************************/
732 
 
733 
/*------------------------------ Non Debug Mode ------------------------------*/
734 
 
735 
#ifndef DEBUG
736 
 
737 
/*********************************** AHBAPB ***********************************/
738 
 
739 
#define AHBAPB0               ((AHBAPB_TypeDef *)AHBAPB0_BASE)
740 
#define AHBAPB1               ((AHBAPB_TypeDef *)AHBAPB1_BASE)
741 
 
742 
/************************************* EMI ************************************/
743 
 
744 
#define EMI                ((EMI_TypeDef *)EMI_BASE)
745 
 
746 
/************************************* DMA ************************************/
747 
 
748 
#define DMA                ((DMA_TypeDef *)DMA_BASE)
749 
#define DMA_Channel0       ((DMA_Channel_TypeDef *)DMA_Channel0_BASE)
750 
#define DMA_Channel1       ((DMA_Channel_TypeDef *)DMA_Channel1_BASE)
751 
#define DMA_Channel2       ((DMA_Channel_TypeDef *)DMA_Channel2_BASE)
752 
#define DMA_Channel3       ((DMA_Channel_TypeDef *)DMA_Channel3_BASE)
753 
#define DMA_Channel4       ((DMA_Channel_TypeDef *)DMA_Channel4_BASE)
754 
#define DMA_Channel5       ((DMA_Channel_TypeDef *)DMA_Channel5_BASE)
755 
#define DMA_Channel6       ((DMA_Channel_TypeDef *)DMA_Channel6_BASE)
756 
#define DMA_Channel7       ((DMA_Channel_TypeDef *)DMA_Channel7_BASE)
757 
 
758 
/************************************* EMI ************************************/
759 
 
760 
#define EMI_Bank0         ((EMI_Bank_TypeDef *)EMI_Bank0_BASE)
761 
#define EMI_Bank1         ((EMI_Bank_TypeDef *)EMI_Bank1_BASE)
762 
#define EMI_Bank2         ((EMI_Bank_TypeDef *)EMI_Bank2_BASE)
763 
#define EMI_Bank3         ((EMI_Bank_TypeDef *)EMI_Bank3_BASE)
764 
 
765 
/************************************* ENET_MAC ************************************/
766 
 
767 
#define ENET_MAC              ((ENET_MAC_TypeDef *)ENET_MAC_BASE)
768 
 
769 
/************************************* ENET_DMA ************************************/
770 
 
771 
#define ENET_DMA              ((ENET_DMA_TypeDef *)ENET_DMA_BASE)
772 
 
773 
/************************************* FMI ************************************/
774 
 
775 
#define FMI                ((FMI_TypeDef *)FMI_BASE)
776 
 
777 
/************************************* VIC ************************************/
778 
 
779 
#define VIC0               ((VIC_TypeDef *)VIC0_BASE)
780 
#define VIC1               ((VIC_TypeDef *)VIC1_BASE)
781 
 
782 
/*******************************************************************************
783 
*                              APB0 Peripherals'                               *
784 
*******************************************************************************/
785 
#define WIU                ((WIU_TypeDef *)WIU_BASE)
786 
#define TIM0               ((TIM_TypeDef *)TIM0_BASE)
787 
#define TIM1               ((TIM_TypeDef *)TIM1_BASE)
788 
#define TIM2               ((TIM_TypeDef *)TIM2_BASE)
789 
#define TIM3               ((TIM_TypeDef *)TIM3_BASE)
790 
#define GPIO0              ((GPIO_TypeDef *)GPIO0_BASE)
791 
#define GPIO1              ((GPIO_TypeDef *)GPIO1_BASE)
792 
#define GPIO2              ((GPIO_TypeDef *)GPIO2_BASE)
793 
#define GPIO3              ((GPIO_TypeDef *)GPIO3_BASE)
794 
#define GPIO4              ((GPIO_TypeDef *)GPIO4_BASE)
795 
#define GPIO5              ((GPIO_TypeDef *)GPIO5_BASE)
796 
#define GPIO6              ((GPIO_TypeDef *)GPIO6_BASE)
797 
#define GPIO7              ((GPIO_TypeDef *)GPIO7_BASE)
798 
#define GPIO8              ((GPIO_TypeDef *)GPIO8_BASE)
799 
#define GPIO9              ((GPIO_TypeDef *)GPIO9_BASE)
800 
/*******************************************************************************
801 
*                              APB1 Peripherals'                               *
802 
*******************************************************************************/
803 
#define RTC                ((RTC_TypeDef *)RTC_BASE)
804 
#define SCU                ((SCU_TypeDef *)SCU_BASE)
805 
#define MC                 ((MC_TypeDef *)MC_BASE)
806 
#define UART0              ((UART_TypeDef *)UART0_BASE)
807 
#define UART1              ((UART_TypeDef *)UART1_BASE)
808 
#define UART2              ((UART_TypeDef *)UART2_BASE)
809 
#define SSP0               ((SSP_TypeDef *)SSP0_BASE)
810 
#define SSP1               ((SSP_TypeDef *)SSP1_BASE)
811 
#define CAN                ((CAN_TypeDef *)CAN_BASE)
812 
#define ADC                ((ADC_TypeDef *)ADC_BASE)
813 
#define WDG                ((WDG_TypeDef *)WDG_BASE)
814 
#define I2C0               ((I2C_TypeDef *)I2C0_BASE)
815 
#define I2C1               ((I2C_TypeDef *)I2C1_BASE)
816 
#define ENET_MAC           ((ENET_MAC_TypeDef *)ENET_MAC_BASE)
817 
#define ENET_DMA           ((ENET_DMA_TypeDef *)ENET_DMA_BASE)
818 
 
819 
#else   /* DEBUG */
820 
 
821 
/*-------------------------------- Debug Mode --------------------------------*/
822 
 
823 
EXT AHBAPB_TypeDef         *AHBAPB0;
824 
EXT AHBAPB_TypeDef         *AHBAPB1;
825 
EXT DMA_TypeDef            *DMA;
826 
EXT DMA_Channel_TypeDef    *DMA_Channel0;
827 
EXT DMA_Channel_TypeDef    *DMA_Channel1;
828 
EXT DMA_Channel_TypeDef    *DMA_Channel2;
829 
EXT DMA_Channel_TypeDef    *DMA_Channel3;
830 
EXT DMA_Channel_TypeDef    *DMA_Channel4;
831 
EXT DMA_Channel_TypeDef    *DMA_Channel5;
832 
EXT DMA_Channel_TypeDef    *DMA_Channel6;
833 
EXT DMA_Channel_TypeDef    *DMA_Channel7;
834 
EXT EMI_Bank_TypeDef       *EMI_Bank0;
835 
EXT EMI_Bank_TypeDef       *EMI_Bank1;
836 
EXT EMI_Bank_TypeDef       *EMI_Bank2;
837 
EXT EMI_Bank_TypeDef       *EMI_Bank3;
838 
EXT FMI_TypeDef            *FMI;
839 
EXT VIC_TypeDef            *VIC0;
840 
EXT VIC_TypeDef            *VIC1;
841 
EXT WIU_TypeDef            *WIU;
842 
EXT TIM_TypeDef            *TIM0;
843 
EXT TIM_TypeDef            *TIM1;
844 
EXT TIM_TypeDef            *TIM2;
845 
EXT TIM_TypeDef            *TIM3;
846 
EXT GPIO_TypeDef           *GPIO0;
847 
EXT GPIO_TypeDef           *GPIO1;
848 
EXT GPIO_TypeDef           *GPIO2;
849 
EXT GPIO_TypeDef           *GPIO3;
850 
EXT GPIO_TypeDef           *GPIO4;
851 
EXT GPIO_TypeDef           *GPIO5;
852 
EXT GPIO_TypeDef           *GPIO6;
853 
EXT GPIO_TypeDef           *GPIO7;
854 
EXT GPIO_TypeDef           *GPIO8;
855 
EXT GPIO_TypeDef           *GPIO9;
856 
EXT RTC_TypeDef            *RTC;
857 
EXT SCU_TypeDef            *SCU;
858 
EXT MC_TypeDef             *MC;
859 
EXT UART_TypeDef           *UART0;
860 
EXT UART_TypeDef           *UART1;
861 
EXT UART_TypeDef           *UART2;
862 
EXT SSP_TypeDef            *SSP0;
863 
EXT SSP_TypeDef            *SSP1;
864 
EXT CAN_TypeDef            *CAN;
865 
EXT ADC_TypeDef            *ADC;
866 
EXT WDG_TypeDef            *WDG;
867 
EXT I2C_TypeDef            *I2C0;
868 
EXT I2C_TypeDef            *I2C1;
869 
EXT ENET_MAC_TypeDef       *ENET_MAC;
870 
EXT ENET_DMA_TypeDef       *ENET_DMA;
871 
 
872 
 
873 
#endif  /* DEBUG */
874 
 
875 
#endif  /* __91x_MAP_H*/
876 
 
877 
/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/
878 
 

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