OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [ARM9_STR91X_IAR/] [Library/] [include/] [91x_scu.h] - Blame information for rev 584

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 577 jeremybenn
/******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
2
* File Name          : 91x_scu.h
3
* Author             : MCD Application Team
4
* Date First Issued  : 05/18/2006 : Version 1.0
5
* Description        : This file provides the SCU library software functions
6
*                      prototypes & definitions
7
********************************************************************************
8
* History:
9
* 05/24/2006 : Version 1.1
10
* 05/18/2006 : Version 1.0
11
********************************************************************************
12
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
13
* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS
14
* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
15
* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
16
* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
17
* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
18
*******************************************************************************/
19
 
20
/* Define to prevent recursive inclusion -------------------------------------*/
21
#ifndef __91x_SCU_H
22
#define __91x_SCU_H
23
 
24
/* Includes ------------------------------------------------------------------*/
25
#include "91x_map.h"
26
 
27
/* Exported constants --------------------------------------------------------*/
28
 
29
/*MCLK_Source*/
30
#define SCU_MCLK_PLL      0x0
31
#define SCU_MCLK_RTC      0x1
32
#define SCU_MCLK_OSC      0x2
33
 
34
/*RCLK_Divisor*/
35
#define SCU_RCLK_Div1     0xFFFFFFE3
36
#define SCU_RCLK_Div2     0x4
37
#define SCU_RCLK_Div4     0x8
38
#define SCU_RCLK_Div8     0xC
39
#define SCU_RCLK_Div16    0x10
40
#define SCU_RCLK_Div1024  0x14
41
 
42
/*HCLK_Divisor*/
43
#define SCU_HCLK_Div1 0xFFFFFF9F
44
#define SCU_HCLK_Div2 0x20
45
#define SCU_HCLK_Div4 0x40
46
 
47
/*PCLK_Divisor*/
48
#define SCU_PCLK_Div1 0xFFFFFE7F
49
#define SCU_PCLK_Div2 0x80
50
#define SCU_PCLK_Div4 0x100
51
#define SCU_PCLK_Div8 0x180
52
 
53
/*FMICLK_Divisor*/
54
#define SCU_FMICLK_Div1 0xFFFEFFFF
55
#define SCU_FMICLK_Div2 0x10000
56
 
57
/*BRCLK_Divisor*/
58
#define SCU_BRCLK_Div1 0xFFFFFDFF
59
#define SCU_BRCLK_Div2 0x200
60
 
61
/*TIMCLK_Source*/
62
#define SCU_TIMCLK_EXT 0x1
63
#define SCU_TIMCLK_INT 0x0
64
 
65
/*TIMx*/
66
#define SCU_TIM01 0x0
67
#define SCU_TIM23 0x1
68
 
69
 
70
/*USBCLK_Source*/
71
#define SCU_USBCLK_MCLK  0xFFFFF3FF
72
#define SCU_USBCLK_MCLK2 0x400
73
#define SCU_USBCLK_EXT   0x800
74
 
75
/*SCU_EMIBCLK*/
76
#define SCU_EMIBCLK_Div1 0xFFF9FFFF
77
#define SCU_EMIBCLK_Div2 0x20000
78
 
79
/*SCU_EMIMODE*/
80
#define SCU_EMI_MUX   0xFFFFFFBF
81
#define SCU_EMI_DEMUX 0x40
82
 
83
/*SCU_EMIALE_LEN*/
84
#define SCU_EMIALE_LEN1 0xFFFFFEFF
85
#define SCU_EMIALE_LEN2 0x100
86
 
87
/*SCU_EMIALE_POL*/
88
#define SCU_EMIALE_POLLow  0xFFFFFF7F
89
#define SCU_EMIALE_POLHigh 0x80
90
 
91
/*UART_IrDA_Mode*/
92
#define SCU_UARTMode_IrDA 0x1
93
#define SCU_UARTMode_UART 0x0
94
 
95
/*APBPeriph*/
96
#define __TIM01 0x1
97
#define __TIM23 0x2
98
#define __MC    0x4
99
#define __UART0 0x8
100
#define __UART1 0x10
101
#define __UART2 0x20
102
#define __I2C0  0x40
103
#define __I2C1  0x80
104
#define __SSP0  0x100
105
#define __SSP1  0x200
106
#define __CAN   0x400
107
#define __ADC   0x800
108
#define __WDG   0x1000
109
#define __WIU   0x2000
110
#define __GPIO0 0x4000
111
#define __GPIO1 0x8000
112
#define __GPIO2 0x10000
113
#define __GPIO3 0x20000
114
#define __GPIO4 0x40000
115
#define __GPIO5 0x80000
116
#define __GPIO6 0x100000
117
#define __GPIO7 0x200000
118
#define __GPIO8 0x400000
119
#define __GPIO9 0x800000
120
#define __RTC   0x1000000
121
 
122
/*AHBPeriph*/
123
#define __FMI          0x1
124
#define __FPQBC        0x2
125
#define __SRAM         0x8
126
#define __SRAM_ARBITER 0x10
127
#define __VIC          0x20
128
#define __EMI          0x40
129
#define __EMI_MEM_CLK  0x80
130
#define __DMA          0x100
131
#define __USB          0x200
132
#define __USB48M       0x400
133
#define __ENET         0x800
134
#define __PFQBC_AHB    0x1000
135
 
136
/*SCU_IT*/
137
#define SCU_IT_LVD_RST    0x10
138
#define SCU_IT_SRAM_ERROR 0x8
139
#define SCU_IT_ACK_PFQBC  0x4
140
#define SCU_IT_LOCK_LOST  0x2
141
#define SCU_IT_LOCK       0x1
142
 
143
/*SCU_FLAG*/
144
#define SCU_FLAG_SRAM_ERROR 0x20
145
#define SCU_FLAG_ACK_PFQBC  0x10
146
#define SCU_FLAG_LVD_RESET  0x8
147
#define SCU_FLAG_WDG_RST    0x4
148
#define SCU_FLAG_LOCK_LOST  0x2
149
#define SCU_FLAG_LOCK       0x1
150
 
151
 
152
/* Module private variables --------------------------------------------------*/
153
/* Exported macro ------------------------------------------------------------*/
154
/* Private functions ---------------------------------------------------------*/
155
/* Exported functions ------------------------------------------------------- */
156
ErrorStatus SCU_MCLKSourceConfig(u32 MCLK_Source);
157
ErrorStatus SCU_PLLFactorsConfig(u8 PLLN, u8 PLLM, u8 PLLP);
158
ErrorStatus SCU_PLLCmd(FunctionalState NewState);
159
void SCU_RCLKDivisorConfig(u32 RCLK_Divisor);
160
void SCU_HCLKDivisorConfig(u32 HCLK_Divisor);
161
void SCU_PCLKDivisorConfig(u32 PCLK_Divisor);
162
void SCU_APBPeriphClockConfig(u32 APBPeriph, FunctionalState NewState);
163
void SCU_AHBPeriphClockConfig(u32 AHBPeriph, FunctionalState NewState);
164
void SCU_APBPeriphReset(u32 APBPeriph, FunctionalState NewState);
165
void SCU_AHBPeriphReset(u32 AHBPeriph, FunctionalState NewState);
166
void SCU_APBPeriphIdleConfig(u32 APBPeriph, FunctionalState NewState);
167
void SCU_AHBPeriphIdleConfig(u32 AHBPeriph, FunctionalState NewState);
168
void SCU_APBPeriphDebugConfig(u32 APBPeriph, FunctionalState NewState);
169
void SCU_AHBPeriphDebugConfig(u32 AHBPeriph, FunctionalState NewState);
170
void SCU_BRCLKDivisorConfig(u32 BRCLK_Divisor);
171
void SCU_TIMCLKSourceConfig(u8 TIMx, u32 TIMCLK_Source);
172
void SCU_TIMPresConfig(u8 TIMx, u16 Prescaler);
173
void SCU_USBCLKConfig(u32 USBCLK_Source);
174
void SCU_PHYCLKConfig(FunctionalState NewState);
175
void SCU_FMICLKDivisorConfig(u32 FMICLK_Divisor);
176
void SCU_EMIBCLKDivisorConfig(u32 SCU_EMIBCLK);
177
void SCU_EMIModeConfig(u32 SCU_EMIMODE);
178
void SCU_EMIALEConfig(u32 SCU_EMIALE_LEN, u32 SCU_EMIALE_POL);
179
void SCU_ITConfig(u32 SCU_IT, FunctionalState NewState);
180
FlagStatus SCU_GetFlagStatus(u32 SCU_Flag);
181
void SCU_ClearFlag(u32 SCU_Flag);
182
u32 SCU_GetPLLFreqValue(void);
183
u32 SCU_GetMCLKFreqValue(void);
184
u32 SCU_GetRCLKFreqValue(void);
185
u32 SCU_GetHCLKFreqValue(void);
186
u32 SCU_GetPCLKFreqValue(void);
187
void SCU_WakeUpLineConfig(u8 EXTint);
188
void SCU_SpecIntRunModeConfig(FunctionalState NewState);
189
void SCU_EnterIdleMode(void);
190
void SCU_EnterSleepMode(void);
191
void SCU_UARTIrDASelect(UART_TypeDef * UARTx, u8 UART_IrDA_Mode);
192
void SCU_PFQBCCmd(FunctionalState NewState);
193
 
194
#endif /*__91x_SCU_H*/
195
 
196
/******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.