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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [AVR32_UC3/] [DRIVERS/] [GPIO/] [gpio.c] - Blame information for rev 589

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1 589 jeremybenn
/*This file has been prepared for Doxygen automatic documentation generation.*/
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/*! \file *********************************************************************
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 *
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 * \brief GPIO driver for AVR32 UC3.
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 *
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 * This file defines a useful set of functions for the GPIO.
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 *
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 * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32
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 * - Supported devices:  All AVR32 devices with a GPIO module can be used.
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 * - AppNote:
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 *
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 * \author               Atmel Corporation: http://www.atmel.com \n
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 *                       Support and FAQ: http://support.atmel.no/
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 *
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 *****************************************************************************/
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/* Copyright (c) 2007, Atmel Corporation All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions are met:
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 *
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 * 1. Redistributions of source code must retain the above copyright notice,
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 * this list of conditions and the following disclaimer.
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 *
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 * 2. Redistributions in binary form must reproduce the above copyright notice,
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 * this list of conditions and the following disclaimer in the documentation
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 * and/or other materials provided with the distribution.
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 *
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 * 3. The name of ATMEL may not be used to endorse or promote products derived
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 * from this software without specific prior written permission.
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 *
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 * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
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 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
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 * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
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 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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#include "gpio.h"
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//! GPIO module instance.
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#define GPIO  AVR32_GPIO
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int gpio_enable_module(const gpio_map_t gpiomap, unsigned int size)
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{
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  int status = GPIO_SUCCESS;
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  unsigned int i;
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  for (i = 0; i < size; i++)
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  {
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    status |= gpio_enable_module_pin(gpiomap->pin, gpiomap->function);
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    gpiomap++;
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  }
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  return status;
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}
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int gpio_enable_module_pin(unsigned int pin, unsigned int function)
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{
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  volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
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  // Enable the correct function.
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  switch (function)
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  {
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  case 0: // A function.
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    gpio_port->pmr0c = 1 << (pin & 0x1F);
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    gpio_port->pmr1c = 1 << (pin & 0x1F);
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    break;
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  case 1: // B function.
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    gpio_port->pmr0s = 1 << (pin & 0x1F);
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    gpio_port->pmr1c = 1 << (pin & 0x1F);
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    break;
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  case 2: // C function.
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    gpio_port->pmr0c = 1 << (pin & 0x1F);
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    gpio_port->pmr1s = 1 << (pin & 0x1F);
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    break;
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  default:
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    return GPIO_INVALID_ARGUMENT;
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  }
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  // Disable GPIO control.
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  gpio_port->gperc = 1 << (pin & 0x1F);
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  return GPIO_SUCCESS;
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}
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void gpio_enable_gpio(const gpio_map_t gpiomap, unsigned int size)
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{
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  unsigned int i;
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  for (i = 0; i < size; i++)
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  {
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    gpio_enable_gpio_pin(gpiomap->pin);
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    gpiomap++;
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  }
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}
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void gpio_enable_gpio_pin(unsigned int pin)
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{
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  volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
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  gpio_port->oderc = 1 << (pin & 0x1F);
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  gpio_port->gpers = 1 << (pin & 0x1F);
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}
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void gpio_enable_pin_open_drain(unsigned int pin)
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{
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  volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
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  gpio_port->odmers = 1 << (pin & 0x1F);
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}
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void gpio_disable_pin_open_drain(unsigned int pin)
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{
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  volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
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  gpio_port->odmerc = 1 << (pin & 0x1F);
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}
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void gpio_enable_pin_pull_up(unsigned int pin)
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{
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  volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
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  gpio_port->puers = 1 << (pin & 0x1F);
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}
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void gpio_disable_pin_pull_up(unsigned int pin)
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{
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  volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
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  gpio_port->puerc = 1 << (pin & 0x1F);
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}
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int gpio_get_pin_value(unsigned int pin)
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{
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  volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
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  return (gpio_port->pvr >> (pin & 0x1F)) & 1;
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}
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int gpio_get_gpio_pin_output_value(unsigned int pin)
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{
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  volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
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  return (gpio_port->ovr >> (pin & 0x1F)) & 1;
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}
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void gpio_set_gpio_pin(unsigned int pin)
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{
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  volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
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  gpio_port->ovrs  = 1 << (pin & 0x1F); // Value to be driven on the I/O line: 1.
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  gpio_port->oders = 1 << (pin & 0x1F); // The GPIO output driver is enabled for that pin.
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  gpio_port->gpers = 1 << (pin & 0x1F); // The GPIO module controls that pin.
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}
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void gpio_clr_gpio_pin(unsigned int pin)
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{
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  volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
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  gpio_port->ovrc  = 1 << (pin & 0x1F); // Value to be driven on the I/O line: 0.
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  gpio_port->oders = 1 << (pin & 0x1F); // The GPIO output driver is enabled for that pin.
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  gpio_port->gpers = 1 << (pin & 0x1F); // The GPIO module controls that pin.
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}
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void gpio_tgl_gpio_pin(unsigned int pin)
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{
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  volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
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  gpio_port->ovrt  = 1 << (pin & 0x1F); // Toggle the I/O line.
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  gpio_port->oders = 1 << (pin & 0x1F); // The GPIO output driver is enabled for that pin.
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  gpio_port->gpers = 1 << (pin & 0x1F); // The GPIO module controls that pin.
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}
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void gpio_enable_pin_glitch_filter(unsigned int pin)
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{
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  volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
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  gpio_port->gfers = 1 << (pin & 0x1F);
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}
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void gpio_disable_pin_glitch_filter(unsigned int pin)
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{
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  volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
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  gpio_port->gferc = 1 << (pin & 0x1F);
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}
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int gpio_enable_pin_interrupt(unsigned int pin, unsigned int mode)
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{
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  volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
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  // Enable the glitch filter.
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  gpio_port->gfers = 1 << (pin & 0x1F);
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  // Configure the edge detector.
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  switch (mode)
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  {
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  case GPIO_PIN_CHANGE:
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    gpio_port->imr0c = 1 << (pin & 0x1F);
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    gpio_port->imr1c = 1 << (pin & 0x1F);
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    break;
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  case GPIO_RISING_EDGE:
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    gpio_port->imr0s = 1 << (pin & 0x1F);
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    gpio_port->imr1c = 1 << (pin & 0x1F);
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    break;
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  case GPIO_FALLING_EDGE:
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    gpio_port->imr0c = 1 << (pin & 0x1F);
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    gpio_port->imr1s = 1 << (pin & 0x1F);
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    break;
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  default:
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    return GPIO_INVALID_ARGUMENT;
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  }
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  // Enable interrupt.
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  gpio_port->iers = 1 << (pin & 0x1F);
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  return GPIO_SUCCESS;
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}
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void gpio_disable_pin_interrupt(unsigned int pin)
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{
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  volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
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  gpio_port->ierc = 1 << (pin & 0x1F);
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}
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int gpio_get_pin_interrupt_flag(unsigned int pin)
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{
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  volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
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  return (gpio_port->ifr >> (pin & 0x1F)) & 1;
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}
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void gpio_clear_pin_interrupt_flag(unsigned int pin)
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{
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  volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
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  gpio_port->ifrc = 1 << (pin & 0x1F);
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}

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