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/******************************************************************************
 * @file:    core_cm3.c
 * @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Source File
 * @version: V1.10
 * @date:    24. Feb. 2009
 *----------------------------------------------------------------------------
 *
 * Copyright (C) 2009 ARM Limited. All rights reserved.
 *
 * ARM Limited (ARM) is supplying this software for use with Cortex-Mx
 * processor based microcontrollers.  This file can be freely distributed
 * within development tools that are supporting such ARM based processors.
 *
 * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
 *
 ******************************************************************************/
 
 
 
#include <stdint.h>
 
 
/* define compiler specific symbols */
#if defined   ( __CC_ARM   )
  #define __ASM            __asm           /*!< asm keyword for armcc          */
  #define __INLINE         __inline        /*!< inline keyword for armcc        */
 
#elif defined ( __ICCARM__ )
  #define __ASM           __asm            /*!< asm keyword for iarcc           */
  #define __INLINE        inline           /*!< inline keyword for iarcc. Only avaiable in High optimization mode! */
  #define __nop           __no_operation   /*!< no operation intrinsic in iarcc */
 
#elif defined (  __GNUC__  )
  #define __ASM             asm            /*!< asm keyword for gcc            */
  #define __INLINE          inline         /*!< inline keyword for gcc         */
#endif
 
 
 
#if defined ( __CC_ARM   ) /*------------------RealView Compiler -----------------*/
 
/**
 * @brief  Return the Process Stack Pointer
 *
 * @param  none
 * @return uint32_t ProcessStackPointer
 *
 * Return the actual process stack pointer
 */
__ASM uint32_t __get_PSP(void)
{
  mrs r0, psp
  bx lr
}
 
/**
 * @brief  Set the Process Stack Pointer
 *
 * @param  uint32_t Process Stack Pointer
 * @return none
 *
 * Assign the value ProcessStackPointer to the MSP
 * (process stack pointer) Cortex processor register
 */
__ASM void __set_PSP(uint32_t topOfProcStack)
{
  msr psp, r0
  bx lr
}
 
/**
 * @brief  Return the Main Stack Pointer
 *
 * @param  none
 * @return uint32_t Main Stack Pointer
 *
 * Return the current value of the MSP (main stack pointer)
 * Cortex processor register
 */
__ASM uint32_t __get_MSP(void)
{
  mrs r0, msp
  bx lr
}
 
/**
 * @brief  Set the Main Stack Pointer
 *
 * @param  uint32_t Main Stack Pointer
 * @return none
 *
 * Assign the value mainStackPointer to the MSP
 * (main stack pointer) Cortex processor register
 */
__ASM void __set_MSP(uint32_t mainStackPointer)
{
  msr msp, r0
  bx lr
}
 
/**
 * @brief  Reverse byte order in unsigned short value
 *
 * @param  uint16_t value to reverse
 * @return uint32_t reversed value
 *
 * Reverse byte order in unsigned short value
 */
__ASM uint32_t __REV16(uint16_t value)
{
  rev16 r0, r0
  bx lr
}
 
/**
 * @brief  Reverse byte order in signed short value with sign extension to integer
 *
 * @param  int16_t value to reverse
 * @return int32_t reversed value
 *
 * Reverse byte order in signed short value with sign extension to integer
 */
__ASM int32_t __REVSH(int16_t value)
{
  revsh r0, r0
  bx lr
}
 
 
#if (__ARMCC_VERSION < 400000)
 
/**
 * @brief  Remove the exclusive lock created by ldrex
 *
 * @param  none
 * @return none
 *
 * Removes the exclusive lock which is created by ldrex.
 */
__ASM void __CLREX(void)
{
  clrex
}
 
/**
 * @brief  Return the Base Priority value
 *
 * @param  none
 * @return uint32_t BasePriority
 *
 * Return the content of the base priority register
 */
__ASM uint32_t  __get_BASEPRI(void)
{
  mrs r0, basepri
  bx lr
}
 
/**
 * @brief  Set the Base Priority value
 *
 * @param  uint32_t BasePriority
 * @return none
 *
 * Set the base priority register
 */
__ASM void __set_BASEPRI(uint32_t basePri)
{
  msr basepri, r0
  bx lr
}
 
/**
 * @brief  Return the Priority Mask value
 *
 * @param  none
 * @return uint32_t PriMask
 *
 * Return the state of the priority mask bit from the priority mask
 * register
 */
__ASM uint32_t __get_PRIMASK(void)
{
  mrs r0, primask
  bx lr
}
 
/**
 * @brief  Set the Priority Mask value
 *
 * @param  uint32_t PriMask
 * @return none
 *
 * Set the priority mask bit in the priority mask register
 */
__ASM void __set_PRIMASK(uint32_t priMask)
{
  msr primask, r0
  bx lr
}
 
/**
 * @brief  Return the Fault Mask value
 *
 * @param  none
 * @return uint32_t FaultMask
 *
 * Return the content of the fault mask register
 */
__ASM uint32_t  __get_FAULTMASK(void)
{
  mrs r0, faultmask
  bx lr
}
 
/**
 * @brief  Set the Fault Mask value
 *
 * @param  uint32_t faultMask value
 * @return none
 *
 * Set the fault mask register
 */
__ASM void __set_FAULTMASK(uint32_t faultMask)
{
  msr faultmask, r0
  bx lr
}
 
/**
 * @brief  Return the Control Register value
 *
 * @param  none
 * @return uint32_t Control value
 *
 * Return the content of the control register
 */
__ASM uint32_t  __get_CONTROL(void)
{
  mrs r0, control
  bx lr
}
 
/**
 * @brief  Set the Control Register value
 *
 * @param  uint32_t Control value
 * @return none
 *
 * Set the control register
 */
__ASM void __set_CONTROL(uint32_t control)
{
  msr control, r0
  bx lr
}
 
#endif /* __ARMCC_VERSION  */ 
 
 
#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
#pragma diag_suppress=Pe940
 
/**
 * @brief  Return the Process Stack Pointer
 *
 * @param  none
 * @return uint32_t ProcessStackPointer
 *
 * Return the actual process stack pointer
 */
uint32_t __get_PSP(void)
{
  __ASM("mrs r0, psp");
  __ASM("bx lr");
}
 
/**
 * @brief  Set the Process Stack Pointer
 *
 * @param  uint32_t Process Stack Pointer
 * @return none
 *
 * Assign the value ProcessStackPointer to the MSP
 * (process stack pointer) Cortex processor register
 */
void __set_PSP(uint32_t topOfProcStack)
{
  __ASM("msr psp, r0");
  __ASM("bx lr");
}
 
/**
 * @brief  Return the Main Stack Pointer
 *
 * @param  none
 * @return uint32_t Main Stack Pointer
 *
 * Return the current value of the MSP (main stack pointer)
 * Cortex processor register
 */
uint32_t __get_MSP(void)
{
  __ASM("mrs r0, msp");
  __ASM("bx lr");
}
 
/**
 * @brief  Set the Main Stack Pointer
 *
 * @param  uint32_t Main Stack Pointer
 * @return none
 *
 * Assign the value mainStackPointer to the MSP
 * (main stack pointer) Cortex processor register
 */
void __set_MSP(uint32_t topOfMainStack)
{
  __ASM("msr msp, r0");
  __ASM("bx lr");
}
 
/**
 * @brief  Reverse byte order in unsigned short value
 *
 * @param  uint16_t value to reverse
 * @return uint32_t reversed value
 *
 * Reverse byte order in unsigned short value
 */
uint32_t __REV16(uint16_t value)
{
  __ASM("rev16 r0, r0");
  __ASM("bx lr");
}
 
/**
 * @brief  Reverse bit order of value
 *
 * @param  uint32_t value to reverse
 * @return uint32_t reversed value
 *
 * Reverse bit order of value
 */
uint32_t __RBIT(uint32_t value)
{
  __ASM("rbit r0, r0");
  __ASM("bx lr");
}
 
/**
 * @brief  LDR Exclusive
 *
 * @param  uint8_t* address
 * @return uint8_t value of (*address)
 *
 * Exclusive LDR command
 */
uint8_t __LDREXB(uint8_t *addr)
{
  __ASM("ldrexb r0, [r0]");
  __ASM("bx lr");
}
 
/**
 * @brief  LDR Exclusive
 *
 * @param  uint16_t* address
 * @return uint16_t value of (*address)
 *
 * Exclusive LDR command
 */
uint16_t __LDREXH(uint16_t *addr)
{
  __ASM("ldrexh r0, [r0]");
  __ASM("bx lr");
}
 
/**
 * @brief  LDR Exclusive
 *
 * @param  uint32_t* address
 * @return uint32_t value of (*address)
 *
 * Exclusive LDR command
 */
uint32_t __LDREXW(uint32_t *addr)
{
  __ASM("ldrex r0, [r0]");
  __ASM("bx lr");
}
 
/**
 * @brief  STR Exclusive
 *
 * @param  uint8_t *address
 * @param  uint8_t value to store
 * @return uint32_t successful / failed
 *
 * Exclusive STR command
 */
uint32_t __STREXB(uint8_t value, uint8_t *addr)
{
  __ASM("strexb r0, r0, [r1]");
  __ASM("bx lr");
}
 
/**
 * @brief  STR Exclusive
 *
 * @param  uint16_t *address
 * @param  uint16_t value to store
 * @return uint32_t successful / failed
 *
 * Exclusive STR command
 */
uint32_t __STREXH(uint16_t value, uint16_t *addr)
{
  __ASM("strexh r0, r0, [r1]");
  __ASM("bx lr");
}
 
/**
 * @brief  STR Exclusive
 *
 * @param  uint32_t *address
 * @param  uint32_t value to store
 * @return uint32_t successful / failed
 *
 * Exclusive STR command
 */
uint32_t __STREXW(uint32_t value, uint32_t *addr)
{
  __ASM("strex r0, r0, [r1]");
  __ASM("bx lr");
}
 
#pragma diag_default=Pe940
 
 
#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
 
/**
 * @brief  Return the Process Stack Pointer
 *
 * @param  none
 * @return uint32_t ProcessStackPointer
 *
 * Return the actual process stack pointer
 */
uint32_t __get_PSP(void)
{
  uint32_t result=0;
 
  __ASM volatile ("MRS %0, psp" : "=r" (result) );
  return(result);
}
 
/**
 * @brief  Set the Process Stack Pointer
 *
 * @param  uint32_t Process Stack Pointer
 * @return none
 *
 * Assign the value ProcessStackPointer to the MSP
 * (process stack pointer) Cortex processor register
 */
void __set_PSP(uint32_t topOfProcStack)
{
  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) );
}
 
/**
 * @brief  Return the Main Stack Pointer
 *
 * @param  none
 * @return uint32_t Main Stack Pointer
 *
 * Return the current value of the MSP (main stack pointer)
 * Cortex processor register
 */
uint32_t __get_MSP(void)
{
  uint32_t result=0;
 
  __ASM volatile ("MRS %0, msp" : "=r" (result) );
  return(result);
}
 
/**
 * @brief  Set the Main Stack Pointer
 *
 * @param  uint32_t Main Stack Pointer
 * @return none
 *
 * Assign the value mainStackPointer to the MSP
 * (main stack pointer) Cortex processor register
 */
void __set_MSP(uint32_t topOfMainStack)
{
  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) );
}
 
/**
 * @brief  Return the Base Priority value
 *
 * @param  none
 * @return uint32_t BasePriority
 *
 * Return the content of the base priority register
 */
uint32_t __get_BASEPRI(void)
{
  uint32_t result=0;
 
  __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
  return(result);
}
 
/**
 * @brief  Set the Base Priority value
 *
 * @param  uint32_t BasePriority
 * @return none
 *
 * Set the base priority register
 */
void __set_BASEPRI(uint32_t value)
{
  __ASM volatile ("MSR basepri, %0" : : "r" (value) );
}
 
/**
 * @brief  Return the Priority Mask value
 *
 * @param  none
 * @return uint32_t PriMask
 *
 * Return the state of the priority mask bit from the priority mask
 * register
 */
uint32_t __get_PRIMASK(void)
{
  uint32_t result=0;
 
  __ASM volatile ("MRS %0, primask" : "=r" (result) );
  return(result);
}
 
/**
 * @brief  Set the Priority Mask value
 *
 * @param  uint32_t PriMask
 * @return none
 *
 * Set the priority mask bit in the priority mask register
 */
void __set_PRIMASK(uint32_t priMask)
{
  __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
}
 
/**
 * @brief  Return the Fault Mask value
 *
 * @param  none
 * @return uint32_t FaultMask
 *
 * Return the content of the fault mask register
 */
uint32_t __get_FAULTMASK(void)
{
  uint32_t result=0;
 
  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
  return(result);
}
 
/**
 * @brief  Set the Fault Mask value
 *
 * @param  uint32_t faultMask value
 * @return none
 *
 * Set the fault mask register
 */
void __set_FAULTMASK(uint32_t faultMask)
{
  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
}
 
/**
 * @brief  Reverse byte order in integer value
 *
 * @param  uint32_t value to reverse
 * @return uint32_t reversed value
 *
 * Reverse byte order in integer value
 */
uint32_t __REV(uint32_t value)
{
  uint32_t result=0;
 
  __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
  return(result);
}
 
/**
 * @brief  Reverse byte order in unsigned short value
 *
 * @param  uint16_t value to reverse
 * @return uint32_t reversed value
 *
 * Reverse byte order in unsigned short value
 */
uint32_t __REV16(uint16_t value)
{
  uint32_t result=0;
 
  __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
  return(result);
}
 
/**
 * @brief  Reverse byte order in signed short value with sign extension to integer
 *
 * @param  int32_t value to reverse
 * @return int32_t reversed value
 *
 * Reverse byte order in signed short value with sign extension to integer
 */
int32_t __REVSH(int16_t value)
{
  uint32_t result=0;
 
  __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
  return(result);
}
 
/**
 * @brief  Reverse bit order of value
 *
 * @param  uint32_t value to reverse
 * @return uint32_t reversed value
 *
 * Reverse bit order of value
 */
uint32_t __RBIT(uint32_t value)
{
  uint32_t result=0;
 
   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
   return(result);
}
 
/**
 * @brief  LDR Exclusive
 *
 * @param  uint8_t* address
 * @return uint8_t value of (*address)
 *
 * Exclusive LDR command
 */
uint8_t __LDREXB(uint8_t *addr)
{
    uint8_t result=0;
 
   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
   return(result);
}
 
/**
 * @brief  LDR Exclusive
 *
 * @param  uint16_t* address
 * @return uint16_t value of (*address)
 *
 * Exclusive LDR command
 */
uint16_t __LDREXH(uint16_t *addr)
{
    uint16_t result=0;
 
   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
   return(result);
}
 
/**
 * @brief  LDR Exclusive
 *
 * @param  uint32_t* address
 * @return uint32_t value of (*address)
 *
 * Exclusive LDR command
 */
uint32_t __LDREXW(uint32_t *addr)
{
    uint32_t result=0;
 
   __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
   return(result);
}
 
/**
 * @brief  STR Exclusive
 *
 * @param  uint8_t *address
 * @param  uint8_t value to store
 * @return uint32_t successful / failed
 *
 * Exclusive STR command
 */
uint32_t __STREXB(uint8_t value, uint8_t *addr)
{
   uint32_t result=0;
 
   __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
   return(result);
}
 
/**
 * @brief  STR Exclusive
 *
 * @param  uint16_t *address
 * @param  uint16_t value to store
 * @return uint32_t successful / failed
 *
 * Exclusive STR command
 */
uint32_t __STREXH(uint16_t value, uint16_t *addr)
{
   uint32_t result=0;
 
   __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
   return(result);
}
 
/**
 * @brief  STR Exclusive
 *
 * @param  uint32_t *address
 * @param  uint32_t value to store
 * @return uint32_t successful / failed
 *
 * Exclusive STR command
 */
uint32_t __STREXW(uint32_t value, uint32_t *addr)
{
   uint32_t result=0;
 
   __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
   return(result);
}
 
/**
 * @brief  Return the Control Register value
 *
 * @param  none
 * @return uint32_t Control value
 *
 * Return the content of the control register
 */
uint32_t __get_CONTROL(void)
{
  uint32_t result=0;
 
  __ASM volatile ("MRS %0, control" : "=r" (result) );
  return(result);
}
 
/**
 * @brief  Set the Control Register value
 *
 * @param  uint32_t Control value
 * @return none
 *
 * Set the control register
 */
void __set_CONTROL(uint32_t control)
{
  __ASM volatile ("MSR control, %0" : : "r" (control) );
}
 
#endif
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

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Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [CORTEX_AT91SAM3U256_IAR/] [AT91Lib/] [cmsis/] [core_cm3.c] - Blame information for rev 580

Line No.	Rev	Author	Line
1	580	jeremybenn	`/******************************************************************************`
2			`* @file: core_cm3.c`
3			`* @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Source File`
4			`* @version: V1.10`
5			`* @date: 24. Feb. 2009`
6			`*----------------------------------------------------------------------------`
7			`*`
8			`* Copyright (C) 2009 ARM Limited. All rights reserved.`
9			`*`
10			`* ARM Limited (ARM) is supplying this software for use with Cortex-Mx`
11			`* processor based microcontrollers. This file can be freely distributed`
12			`* within development tools that are supporting such ARM based processors.`
13			`*`
14			`* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED`
15			`* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF`
16			`* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.`
17			`* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR`
18			`* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.`
19			`*`
20			`******************************************************************************/`
21
22
23
24			`#include <stdint.h>`
25
26
27			`/* define compiler specific symbols */`
28			`#if defined ( __CC_ARM )`
29			`#define __ASM __asm /!< asm keyword for armcc /`
30			`#define __INLINE __inline /!< inline keyword for armcc /`
31
32			`#elif defined ( __ICCARM__ )`
33			`#define __ASM __asm /!< asm keyword for iarcc /`
34			`#define __INLINE inline /!< inline keyword for iarcc. Only avaiable in High optimization mode! /`
35			`#define __nop __no_operation /!< no operation intrinsic in iarcc /`
36
37			`#elif defined ( __GNUC__ )`
38			`#define __ASM asm /!< asm keyword for gcc /`
39			`#define __INLINE inline /!< inline keyword for gcc /`
40			`#endif`
41
42
43
44			`#if defined ( __CC_ARM ) /------------------RealView Compiler -----------------/`
45
46			`/**`
47			`* @brief Return the Process Stack Pointer`
48			`*`
49			`* @param none`
50			`* @return uint32_t ProcessStackPointer`
51			`*`
52			`* Return the actual process stack pointer`
53			`*/`
54			`__ASM uint32_t __get_PSP(void)`
55			`{`
56			`mrs r0, psp`
57			`bx lr`
58			`}`
59
60			`/**`
61			`* @brief Set the Process Stack Pointer`
62			`*`
63			`* @param uint32_t Process Stack Pointer`
64			`* @return none`
65			`*`
66			`* Assign the value ProcessStackPointer to the MSP`
67			`* (process stack pointer) Cortex processor register`
68			`*/`
69			`__ASM void __set_PSP(uint32_t topOfProcStack)`
70			`{`
71			`msr psp, r0`
72			`bx lr`
73			`}`
74
75			`/**`
76			`* @brief Return the Main Stack Pointer`
77			`*`
78			`* @param none`
79			`* @return uint32_t Main Stack Pointer`
80			`*`
81			`* Return the current value of the MSP (main stack pointer)`
82			`* Cortex processor register`
83			`*/`
84			`__ASM uint32_t __get_MSP(void)`
85			`{`
86			`mrs r0, msp`
87			`bx lr`
88			`}`
89
90			`/**`
91			`* @brief Set the Main Stack Pointer`
92			`*`
93			`* @param uint32_t Main Stack Pointer`
94			`* @return none`
95			`*`
96			`* Assign the value mainStackPointer to the MSP`
97			`* (main stack pointer) Cortex processor register`
98			`*/`
99			`__ASM void __set_MSP(uint32_t mainStackPointer)`
100			`{`
101			`msr msp, r0`
102			`bx lr`
103			`}`
104
105			`/**`
106			`* @brief Reverse byte order in unsigned short value`
107			`*`
108			`* @param uint16_t value to reverse`
109			`* @return uint32_t reversed value`
110			`*`
111			`* Reverse byte order in unsigned short value`
112			`*/`
113			`__ASM uint32_t __REV16(uint16_t value)`
114			`{`
115			`rev16 r0, r0`
116			`bx lr`
117			`}`
118
119			`/**`
120			`* @brief Reverse byte order in signed short value with sign extension to integer`
121			`*`
122			`* @param int16_t value to reverse`
123			`* @return int32_t reversed value`
124			`*`
125			`* Reverse byte order in signed short value with sign extension to integer`
126			`*/`
127			`__ASM int32_t __REVSH(int16_t value)`
128			`{`
129			`revsh r0, r0`
130			`bx lr`
131			`}`
132
133
134			`#if (__ARMCC_VERSION < 400000)`
135
136			`/**`
137			`* @brief Remove the exclusive lock created by ldrex`
138			`*`
139			`* @param none`
140			`* @return none`
141			`*`
142			`* Removes the exclusive lock which is created by ldrex.`
143			`*/`
144			`__ASM void __CLREX(void)`
145			`{`
146			`clrex`
147			`}`
148
149			`/**`
150			`* @brief Return the Base Priority value`
151			`*`
152			`* @param none`
153			`* @return uint32_t BasePriority`
154			`*`
155			`* Return the content of the base priority register`
156			`*/`
157			`__ASM uint32_t __get_BASEPRI(void)`
158			`{`
159			`mrs r0, basepri`
160			`bx lr`
161			`}`
162
163			`/**`
164			`* @brief Set the Base Priority value`
165			`*`
166			`* @param uint32_t BasePriority`
167			`* @return none`
168			`*`
169			`* Set the base priority register`
170			`*/`
171			`__ASM void __set_BASEPRI(uint32_t basePri)`
172			`{`
173			`msr basepri, r0`
174			`bx lr`
175			`}`
176
177			`/**`
178			`* @brief Return the Priority Mask value`
179			`*`
180			`* @param none`
181			`* @return uint32_t PriMask`
182			`*`
183			`* Return the state of the priority mask bit from the priority mask`
184			`* register`
185			`*/`
186			`__ASM uint32_t __get_PRIMASK(void)`
187			`{`
188			`mrs r0, primask`
189			`bx lr`
190			`}`
191
192			`/**`
193			`* @brief Set the Priority Mask value`
194			`*`
195			`* @param uint32_t PriMask`
196			`* @return none`
197			`*`
198			`* Set the priority mask bit in the priority mask register`
199			`*/`
200			`__ASM void __set_PRIMASK(uint32_t priMask)`
201			`{`
202			`msr primask, r0`
203			`bx lr`
204			`}`
205
206			`/**`
207			`* @brief Return the Fault Mask value`
208			`*`
209			`* @param none`
210			`* @return uint32_t FaultMask`
211			`*`
212			`* Return the content of the fault mask register`
213			`*/`
214			`__ASM uint32_t __get_FAULTMASK(void)`
215			`{`
216			`mrs r0, faultmask`
217			`bx lr`
218			`}`
219
220			`/**`
221			`* @brief Set the Fault Mask value`
222			`*`
223			`* @param uint32_t faultMask value`
224			`* @return none`
225			`*`
226			`* Set the fault mask register`
227			`*/`
228			`__ASM void __set_FAULTMASK(uint32_t faultMask)`
229			`{`
230			`msr faultmask, r0`
231			`bx lr`
232			`}`
233
234			`/**`
235			`* @brief Return the Control Register value`
236			`*`
237			`* @param none`
238			`* @return uint32_t Control value`
239			`*`
240			`* Return the content of the control register`
241			`*/`
242			`__ASM uint32_t __get_CONTROL(void)`
243			`{`
244			`mrs r0, control`
245			`bx lr`
246			`}`
247
248			`/**`
249			`* @brief Set the Control Register value`
250			`*`
251			`* @param uint32_t Control value`
252			`* @return none`
253			`*`
254			`* Set the control register`
255			`*/`
256			`__ASM void __set_CONTROL(uint32_t control)`
257			`{`
258			`msr control, r0`
259			`bx lr`
260			`}`
261
262			`#endif /* __ARMCC_VERSION */`
263
264
265			`#elif (defined (__ICCARM__)) /------------------ ICC Compiler -------------------/`
266			`#pragma diag_suppress=Pe940`
267
268			`/**`
269			`* @brief Return the Process Stack Pointer`
270			`*`
271			`* @param none`
272			`* @return uint32_t ProcessStackPointer`
273			`*`
274			`* Return the actual process stack pointer`
275			`*/`
276			`uint32_t __get_PSP(void)`
277			`{`
278			`__ASM("mrs r0, psp");`
279			`__ASM("bx lr");`
280			`}`
281
282			`/**`
283			`* @brief Set the Process Stack Pointer`
284			`*`
285			`* @param uint32_t Process Stack Pointer`
286			`* @return none`
287			`*`
288			`* Assign the value ProcessStackPointer to the MSP`
289			`* (process stack pointer) Cortex processor register`
290			`*/`
291			`void __set_PSP(uint32_t topOfProcStack)`
292			`{`
293			`__ASM("msr psp, r0");`
294			`__ASM("bx lr");`
295			`}`
296
297			`/**`
298			`* @brief Return the Main Stack Pointer`
299			`*`
300			`* @param none`
301			`* @return uint32_t Main Stack Pointer`
302			`*`
303			`* Return the current value of the MSP (main stack pointer)`
304			`* Cortex processor register`
305			`*/`
306			`uint32_t __get_MSP(void)`
307			`{`
308			`__ASM("mrs r0, msp");`
309			`__ASM("bx lr");`
310			`}`
311
312			`/**`
313			`* @brief Set the Main Stack Pointer`
314			`*`
315			`* @param uint32_t Main Stack Pointer`
316			`* @return none`
317			`*`
318			`* Assign the value mainStackPointer to the MSP`
319			`* (main stack pointer) Cortex processor register`
320			`*/`
321			`void __set_MSP(uint32_t topOfMainStack)`
322			`{`
323			`__ASM("msr msp, r0");`
324			`__ASM("bx lr");`
325			`}`
326
327			`/**`
328			`* @brief Reverse byte order in unsigned short value`
329			`*`
330			`* @param uint16_t value to reverse`
331			`* @return uint32_t reversed value`
332			`*`
333			`* Reverse byte order in unsigned short value`
334			`*/`
335			`uint32_t __REV16(uint16_t value)`
336			`{`
337			`__ASM("rev16 r0, r0");`
338			`__ASM("bx lr");`
339			`}`
340
341			`/**`
342			`* @brief Reverse bit order of value`
343			`*`
344			`* @param uint32_t value to reverse`
345			`* @return uint32_t reversed value`
346			`*`
347			`* Reverse bit order of value`
348			`*/`
349			`uint32_t __RBIT(uint32_t value)`
350			`{`
351			`__ASM("rbit r0, r0");`
352			`__ASM("bx lr");`
353			`}`
354
355			`/**`
356			`* @brief LDR Exclusive`
357			`*`
358			`* @param uint8_t* address`
359			`* @return uint8_t value of (*address)`
360			`*`
361			`* Exclusive LDR command`
362			`*/`
363			`uint8_t __LDREXB(uint8_t *addr)`
364			`{`
365			`__ASM("ldrexb r0, [r0]");`
366			`__ASM("bx lr");`
367			`}`
368
369			`/**`
370			`* @brief LDR Exclusive`
371			`*`
372			`* @param uint16_t* address`
373			`* @return uint16_t value of (*address)`
374			`*`
375			`* Exclusive LDR command`
376			`*/`
377			`uint16_t __LDREXH(uint16_t *addr)`
378			`{`
379			`__ASM("ldrexh r0, [r0]");`
380			`__ASM("bx lr");`
381			`}`
382
383			`/**`
384			`* @brief LDR Exclusive`
385			`*`
386			`* @param uint32_t* address`
387			`* @return uint32_t value of (*address)`
388			`*`
389			`* Exclusive LDR command`
390			`*/`
391			`uint32_t __LDREXW(uint32_t *addr)`
392			`{`
393			`__ASM("ldrex r0, [r0]");`
394			`__ASM("bx lr");`
395			`}`
396
397			`/**`
398			`* @brief STR Exclusive`
399			`*`
400			`* @param uint8_t *address`
401			`* @param uint8_t value to store`
402			`* @return uint32_t successful / failed`
403			`*`
404			`* Exclusive STR command`
405			`*/`
406			`uint32_t __STREXB(uint8_t value, uint8_t *addr)`
407			`{`
408			`__ASM("strexb r0, r0, [r1]");`
409			`__ASM("bx lr");`
410			`}`
411
412			`/**`
413			`* @brief STR Exclusive`
414			`*`
415			`* @param uint16_t *address`
416			`* @param uint16_t value to store`
417			`* @return uint32_t successful / failed`
418			`*`
419			`* Exclusive STR command`
420			`*/`
421			`uint32_t __STREXH(uint16_t value, uint16_t *addr)`
422			`{`
423			`__ASM("strexh r0, r0, [r1]");`
424			`__ASM("bx lr");`
425			`}`
426
427			`/**`
428			`* @brief STR Exclusive`
429			`*`
430			`* @param uint32_t *address`
431			`* @param uint32_t value to store`
432			`* @return uint32_t successful / failed`
433			`*`
434			`* Exclusive STR command`
435			`*/`
436			`uint32_t __STREXW(uint32_t value, uint32_t *addr)`
437			`{`
438			`__ASM("strex r0, r0, [r1]");`
439			`__ASM("bx lr");`
440			`}`
441
442			`#pragma diag_default=Pe940`
443
444
445			`#elif (defined (__GNUC__)) /------------------ GNU Compiler ---------------------/`
446
447			`/**`
448			`* @brief Return the Process Stack Pointer`
449			`*`
450			`* @param none`
451			`* @return uint32_t ProcessStackPointer`
452			`*`
453			`* Return the actual process stack pointer`
454			`*/`
455			`uint32_t __get_PSP(void)`
456			`{`
457			`uint32_t result=0;`
458
459			`__ASM volatile ("MRS %0, psp" : "=r" (result) );`
460			`return(result);`
461			`}`
462
463			`/**`
464			`* @brief Set the Process Stack Pointer`
465			`*`
466			`* @param uint32_t Process Stack Pointer`
467			`* @return none`
468			`*`
469			`* Assign the value ProcessStackPointer to the MSP`
470			`* (process stack pointer) Cortex processor register`
471			`*/`
472			`void __set_PSP(uint32_t topOfProcStack)`
473			`{`
474			`__ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) );`
475			`}`
476
477			`/**`
478			`* @brief Return the Main Stack Pointer`
479			`*`
480			`* @param none`
481			`* @return uint32_t Main Stack Pointer`
482			`*`
483			`* Return the current value of the MSP (main stack pointer)`
484			`* Cortex processor register`
485			`*/`
486			`uint32_t __get_MSP(void)`
487			`{`
488			`uint32_t result=0;`
489
490			`__ASM volatile ("MRS %0, msp" : "=r" (result) );`
491			`return(result);`
492			`}`
493
494			`/**`
495			`* @brief Set the Main Stack Pointer`
496			`*`
497			`* @param uint32_t Main Stack Pointer`
498			`* @return none`
499			`*`
500			`* Assign the value mainStackPointer to the MSP`
501			`* (main stack pointer) Cortex processor register`
502			`*/`
503			`void __set_MSP(uint32_t topOfMainStack)`
504			`{`
505			`__ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) );`
506			`}`
507
508			`/**`
509			`* @brief Return the Base Priority value`
510			`*`
511			`* @param none`
512			`* @return uint32_t BasePriority`
513			`*`
514			`* Return the content of the base priority register`
515			`*/`
516			`uint32_t __get_BASEPRI(void)`
517			`{`
518			`uint32_t result=0;`
519
520			`__ASM volatile ("MRS %0, basepri_max" : "=r" (result) );`
521			`return(result);`
522			`}`
523
524			`/**`
525			`* @brief Set the Base Priority value`
526			`*`
527			`* @param uint32_t BasePriority`
528			`* @return none`
529			`*`
530			`* Set the base priority register`
531			`*/`
532			`void __set_BASEPRI(uint32_t value)`
533			`{`
534			`__ASM volatile ("MSR basepri, %0" : : "r" (value) );`
535			`}`
536
537			`/**`
538			`* @brief Return the Priority Mask value`
539			`*`
540			`* @param none`
541			`* @return uint32_t PriMask`
542			`*`
543			`* Return the state of the priority mask bit from the priority mask`
544			`* register`
545			`*/`
546			`uint32_t __get_PRIMASK(void)`
547			`{`
548			`uint32_t result=0;`
549
550			`__ASM volatile ("MRS %0, primask" : "=r" (result) );`
551			`return(result);`
552			`}`
553
554			`/**`
555			`* @brief Set the Priority Mask value`
556			`*`
557			`* @param uint32_t PriMask`
558			`* @return none`
559			`*`
560			`* Set the priority mask bit in the priority mask register`
561			`*/`
562			`void __set_PRIMASK(uint32_t priMask)`
563			`{`
564			`__ASM volatile ("MSR primask, %0" : : "r" (priMask) );`
565			`}`
566
567			`/**`
568			`* @brief Return the Fault Mask value`
569			`*`
570			`* @param none`
571			`* @return uint32_t FaultMask`
572			`*`
573			`* Return the content of the fault mask register`
574			`*/`
575			`uint32_t __get_FAULTMASK(void)`
576			`{`
577			`uint32_t result=0;`
578
579			`__ASM volatile ("MRS %0, faultmask" : "=r" (result) );`
580			`return(result);`
581			`}`
582
583			`/**`
584			`* @brief Set the Fault Mask value`
585			`*`
586			`* @param uint32_t faultMask value`
587			`* @return none`
588			`*`
589			`* Set the fault mask register`
590			`*/`
591			`void __set_FAULTMASK(uint32_t faultMask)`
592			`{`
593			`__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );`
594			`}`
595
596			`/**`
597			`* @brief Reverse byte order in integer value`
598			`*`
599			`* @param uint32_t value to reverse`
600			`* @return uint32_t reversed value`
601			`*`
602			`* Reverse byte order in integer value`
603			`*/`
604			`uint32_t __REV(uint32_t value)`
605			`{`
606			`uint32_t result=0;`
607
608			`__ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );`
609			`return(result);`
610			`}`
611
612			`/**`
613			`* @brief Reverse byte order in unsigned short value`
614			`*`
615			`* @param uint16_t value to reverse`
616			`* @return uint32_t reversed value`
617			`*`
618			`* Reverse byte order in unsigned short value`
619			`*/`
620			`uint32_t __REV16(uint16_t value)`
621			`{`
622			`uint32_t result=0;`
623
624			`__ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );`
625			`return(result);`
626			`}`
627
628			`/**`
629			`* @brief Reverse byte order in signed short value with sign extension to integer`
630			`*`
631			`* @param int32_t value to reverse`
632			`* @return int32_t reversed value`
633			`*`
634			`* Reverse byte order in signed short value with sign extension to integer`
635			`*/`
636			`int32_t __REVSH(int16_t value)`
637			`{`
638			`uint32_t result=0;`
639
640			`__ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );`
641			`return(result);`
642			`}`
643
644			`/**`
645			`* @brief Reverse bit order of value`
646			`*`
647			`* @param uint32_t value to reverse`
648			`* @return uint32_t reversed value`
649			`*`
650			`* Reverse bit order of value`
651			`*/`
652			`uint32_t __RBIT(uint32_t value)`
653			`{`
654			`uint32_t result=0;`
655
656			`__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );`
657			`return(result);`
658			`}`
659
660			`/**`
661			`* @brief LDR Exclusive`
662			`*`
663			`* @param uint8_t* address`
664			`* @return uint8_t value of (*address)`
665			`*`
666			`* Exclusive LDR command`
667			`*/`
668			`uint8_t __LDREXB(uint8_t *addr)`
669			`{`
670			`uint8_t result=0;`
671
672			`__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );`
673			`return(result);`
674			`}`
675
676			`/**`
677			`* @brief LDR Exclusive`
678			`*`
679			`* @param uint16_t* address`
680			`* @return uint16_t value of (*address)`
681			`*`
682			`* Exclusive LDR command`
683			`*/`
684			`uint16_t __LDREXH(uint16_t *addr)`
685			`{`
686			`uint16_t result=0;`
687
688			`__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );`
689			`return(result);`
690			`}`
691
692			`/**`
693			`* @brief LDR Exclusive`
694			`*`
695			`* @param uint32_t* address`
696			`* @return uint32_t value of (*address)`
697			`*`
698			`* Exclusive LDR command`
699			`*/`
700			`uint32_t __LDREXW(uint32_t *addr)`
701			`{`
702			`uint32_t result=0;`
703
704			`__ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );`
705			`return(result);`
706			`}`
707
708			`/**`
709			`* @brief STR Exclusive`
710			`*`
711			`* @param uint8_t *address`
712			`* @param uint8_t value to store`
713			`* @return uint32_t successful / failed`
714			`*`
715			`* Exclusive STR command`
716			`*/`
717			`uint32_t __STREXB(uint8_t value, uint8_t *addr)`
718			`{`
719			`uint32_t result=0;`
720
721			`__ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );`
722			`return(result);`
723			`}`
724
725			`/**`
726			`* @brief STR Exclusive`
727			`*`
728			`* @param uint16_t *address`
729			`* @param uint16_t value to store`
730			`* @return uint32_t successful / failed`
731			`*`
732			`* Exclusive STR command`
733			`*/`
734			`uint32_t __STREXH(uint16_t value, uint16_t *addr)`
735			`{`
736			`uint32_t result=0;`
737
738			`__ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );`
739			`return(result);`
740			`}`
741
742			`/**`
743			`* @brief STR Exclusive`
744			`*`
745			`* @param uint32_t *address`
746			`* @param uint32_t value to store`
747			`* @return uint32_t successful / failed`
748			`*`
749			`* Exclusive STR command`
750			`*/`
751			`uint32_t __STREXW(uint32_t value, uint32_t *addr)`
752			`{`
753			`uint32_t result=0;`
754
755			`__ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );`
756			`return(result);`
757			`}`
758
759			`/**`
760			`* @brief Return the Control Register value`
761			`*`
762			`* @param none`
763			`* @return uint32_t Control value`
764			`*`
765			`* Return the content of the control register`
766			`*/`
767			`uint32_t __get_CONTROL(void)`
768			`{`
769			`uint32_t result=0;`
770
771			`__ASM volatile ("MRS %0, control" : "=r" (result) );`
772			`return(result);`
773			`}`
774
775			`/**`
776			`* @brief Set the Control Register value`
777			`*`
778			`* @param uint32_t Control value`
779			`* @return none`
780			`*`
781			`* Set the control register`
782			`*/`
783			`void __set_CONTROL(uint32_t control)`
784			`{`
785			`__ASM volatile ("MSR control, %0" : : "r" (control) );`
786			`}`
787
788			`#endif`
789
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792
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799
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