OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [CORTEX_AT91SAM3U256_IAR/] [AT91Lib/] [cmsis/] [core_cm3.h] - Blame information for rev 591

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 580 jeremybenn 
/******************************************************************************
2 
 * @file:    core_cm3.h
3 
 * @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Header File
4 
 * @version: V1.10
5 
 * @date:    24. Feb. 2009
6 
 *----------------------------------------------------------------------------
7 
 *
8 
 * Copyright (C) 2009 ARM Limited. All rights reserved.
9 
 *
10 
 * ARM Limited (ARM) is supplying this software for use with Cortex-Mx
11 
 * processor based microcontrollers.  This file can be freely distributed
12 
 * within development tools that are supporting such ARM based processors.
13 
 *
14 
 * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
15 
 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
16 
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
17 
 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
18 
 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
19 
 *
20 
 ******************************************************************************/
21 
 
22 
 
23 
 
24 
 
25 
#ifndef __CM3_CORE_H__
26 
#define __CM3_CORE_H__
27 
 
28 
 
29 
#define __CM3_CMSIS_VERSION_MAIN  (0x01)                                                       /*!< [31:16] CMSIS HAL main version */
30 
#define __CM3_CMSIS_VERSION_SUB   (0x10)                                                       /*!< [15:0]  CMSIS HAL sub version  */
31 
#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number       */
32 
 
33 
#define __CORTEX_M                (0x03)                                                       /*!< Cortex core                    */
34 
 
35 
/**
36 
 *  Lint configuration \n
37 
 *  ----------------------- \n
38 
 *
39 
 *  The following Lint messages will be suppressed and not shown: \n
40 
 *  \n
41 
 *    --- Error 10: --- \n
42 
 *    register uint32_t __regBasePri         __asm("basepri"); \n
43 
 *    Error 10: Expecting ';' \n
44 
 *     \n
45 
 *    --- Error 530: --- \n
46 
 *    return(__regBasePri); \n
47 
 *    Warning 530: Symbol '__regBasePri' (line 264) not initialized \n
48 
 *     \n
49 
 *    --- Error 550: --- \n
50 
 *      __regBasePri = (basePri & 0x1ff); \n
51 
 *    } \n
52 
 *    Warning 550: Symbol '__regBasePri' (line 271) not accessed \n
53 
 *     \n
54 
 *    --- Error 754: --- \n
55 
 *    uint32_t RESERVED0[24]; \n
56 
 *    Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced \n
57 
 *     \n
58 
 *    --- Error 750: --- \n
59 
 *    #define __CM3_CORE_H__ \n
60 
 *    Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced \n
61 
 *     \n
62 
 *    --- Error 528: --- \n
63 
 *    static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n
64 
 *    Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced \n
65 
 *     \n
66 
 *    --- Error 751: --- \n
67 
 *    } InterruptType_Type; \n
68 
 *    Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced \n
69 
 * \n
70 
 * \n
71 
 *    Note:  To re-enable a Message, insert a space before 'lint' * \n
72 
 *
73 
 */
74 
 
75 
/*lint -save */
76 
/*lint -e10  */
77 
/*lint -e530 */
78 
/*lint -e550 */
79 
/*lint -e754 */
80 
/*lint -e750 */
81 
/*lint -e528 */
82 
/*lint -e751 */
83 
 
84 
 
85 
#include <stdint.h>                           /* Include standard types */
86 
 
87 
#if defined (__ICCARM__)
88 
  #include <intrinsics.h>                     /* IAR Intrinsics   */
89 
#endif
90 
 
91 
 
92 
#ifndef __NVIC_PRIO_BITS
93 
  #define __NVIC_PRIO_BITS    4               /*!< standard definition for NVIC Priority Bits */
94 
#endif
95 
 
96 
 
97 
 
98 
 
99 
/**
100 
 * IO definitions
101 
 *
102 
 * define access restrictions to peripheral registers
103 
 */
104 
 
105 
#define     __I     volatile const            /*!< defines 'read only' permissions      */
106 
#define     __O     volatile                  /*!< defines 'write only' permissions     */
107 
#define     __IO    volatile                  /*!< defines 'read / write' permissions   */
108 
 
109 
 
110 
 
111 
/*******************************************************************************
112 
 *                 Register Abstraction
113 
 ******************************************************************************/
114 
 
115 
 
116 
/* System Reset */
117 
#define NVIC_VECTRESET              0         /*!< Vector Reset Bit             */
118 
#define NVIC_SYSRESETREQ            2         /*!< System Reset Request         */
119 
#define NVIC_AIRCR_VECTKEY    (0x5FA << 16)   /*!< AIRCR Key for write access   */
120 
#define NVIC_AIRCR_ENDIANESS        15        /*!< Endianess                    */
121 
 
122 
/* Core Debug */
123 
#define CoreDebug_DEMCR_TRCENA (1 << 24)      /*!< DEMCR TRCENA enable          */
124 
#define ITM_TCR_ITMENA              1         /*!< ITM enable                   */
125 
 
126 
 
127 
 
128 
 
129 
/* memory mapping struct for Nested Vectored Interrupt Controller (NVIC) */
130 
typedef struct
131 
{
132 
  __IO uint32_t ISER[8];                      /*!< Interrupt Set Enable Register            */
133 
       uint32_t RESERVED0[24];
134 
  __IO uint32_t ICER[8];                      /*!< Interrupt Clear Enable Register          */
135 
       uint32_t RSERVED1[24];
136 
  __IO uint32_t ISPR[8];                      /*!< Interrupt Set Pending Register           */
137 
       uint32_t RESERVED2[24];
138 
  __IO uint32_t ICPR[8];                      /*!< Interrupt Clear Pending Register         */
139 
       uint32_t RESERVED3[24];
140 
  __IO uint32_t IABR[8];                      /*!< Interrupt Active bit Register            */
141 
       uint32_t RESERVED4[56];
142 
  __IO uint8_t  IP[240];                      /*!< Interrupt Priority Register, 8Bit wide   */
143 
       uint32_t RESERVED5[644];
144 
  __O  uint32_t STIR;                         /*!< Software Trigger Interrupt Register      */
145 
}  NVIC_Type;
146 
 
147 
 
148 
/* memory mapping struct for System Control Block */
149 
typedef struct
150 
{
151 
  __I  uint32_t CPUID;                        /*!< CPU ID Base Register                                     */
152 
  __IO uint32_t ICSR;                         /*!< Interrupt Control State Register                         */
153 
  __IO uint32_t VTOR;                         /*!< Vector Table Offset Register                             */
154 
  __IO uint32_t AIRCR;                        /*!< Application Interrupt / Reset Control Register           */
155 
  __IO uint32_t SCR;                          /*!< System Control Register                                  */
156 
  __IO uint32_t CCR;                          /*!< Configuration Control Register                           */
157 
  __IO uint8_t  SHP[12];                      /*!< System Handlers Priority Registers (4-7, 8-11, 12-15)    */
158 
  __IO uint32_t SHCSR;                        /*!< System Handler Control and State Register                */
159 
  __IO uint32_t CFSR;                         /*!< Configurable Fault Status Register                       */
160 
  __IO uint32_t HFSR;                         /*!< Hard Fault Status Register                               */
161 
  __IO uint32_t DFSR;                         /*!< Debug Fault Status Register                              */
162 
  __IO uint32_t MMFAR;                        /*!< Mem Manage Address Register                              */
163 
  __IO uint32_t BFAR;                         /*!< Bus Fault Address Register                               */
164 
  __IO uint32_t AFSR;                         /*!< Auxiliary Fault Status Register                          */
165 
  __I  uint32_t PFR[2];                       /*!< Processor Feature Register                               */
166 
  __I  uint32_t DFR;                          /*!< Debug Feature Register                                   */
167 
  __I  uint32_t ADR;                          /*!< Auxiliary Feature Register                               */
168 
  __I  uint32_t MMFR[4];                      /*!< Memory Model Feature Register                            */
169 
  __I  uint32_t ISAR[5];                      /*!< ISA Feature Register                                     */
170 
} SCB_Type;
171 
 
172 
 
173 
/* memory mapping struct for SysTick */
174 
typedef struct
175 
{
176 
  __IO uint32_t CTRL;                         /*!< SysTick Control and Status Register */
177 
  __IO uint32_t LOAD;                         /*!< SysTick Reload Value Register       */
178 
  __IO uint32_t VAL;                          /*!< SysTick Current Value Register      */
179 
  __I  uint32_t CALIB;                        /*!< SysTick Calibration Register        */
180 
} SysTick_Type;
181 
 
182 
 
183 
/* memory mapping structur for ITM */
184 
typedef struct
185 
{
186 
  __O  union
187 
  {
188 
    __O  uint8_t    u8;                       /*!< ITM Stimulus Port 8-bit               */
189 
    __O  uint16_t   u16;                      /*!< ITM Stimulus Port 16-bit              */
190 
    __O  uint32_t   u32;                      /*!< ITM Stimulus Port 32-bit              */
191 
  }  PORT [32];                               /*!< ITM Stimulus Port Registers           */
192 
       uint32_t RESERVED0[864];
193 
  __IO uint32_t TER;                          /*!< ITM Trace Enable Register             */
194 
       uint32_t RESERVED1[15];
195 
  __IO uint32_t TPR;                          /*!< ITM Trace Privilege Register          */
196 
       uint32_t RESERVED2[15];
197 
  __IO uint32_t TCR;                          /*!< ITM Trace Control Register            */
198 
       uint32_t RESERVED3[29];
199 
  __IO uint32_t IWR;                          /*!< ITM Integration Write Register        */
200 
  __IO uint32_t IRR;                          /*!< ITM Integration Read Register         */
201 
  __IO uint32_t IMCR;                         /*!< ITM Integration Mode Control Register */
202 
       uint32_t RESERVED4[43];
203 
  __IO uint32_t LAR;                          /*!< ITM Lock Access Register              */
204 
  __IO uint32_t LSR;                          /*!< ITM Lock Status Register              */
205 
       uint32_t RESERVED5[6];
206 
  __I  uint32_t PID4;                         /*!< ITM Product ID Registers              */
207 
  __I  uint32_t PID5;
208 
  __I  uint32_t PID6;
209 
  __I  uint32_t PID7;
210 
  __I  uint32_t PID0;
211 
  __I  uint32_t PID1;
212 
  __I  uint32_t PID2;
213 
  __I  uint32_t PID3;
214 
  __I  uint32_t CID0;
215 
  __I  uint32_t CID1;
216 
  __I  uint32_t CID2;
217 
  __I  uint32_t CID3;
218 
} ITM_Type;
219 
 
220 
 
221 
/* memory mapped struct for Interrupt Type */
222 
typedef struct
223 
{
224 
       uint32_t RESERVED0;
225 
  __I  uint32_t ICTR;                         /*!< Interrupt Control Type Register  */
226 
#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
227 
  __IO uint32_t ACTLR;                        /*!< Auxiliary Control Register       */
228 
#else
229 
       uint32_t RESERVED1;
230 
#endif
231 
} InterruptType_Type;
232 
 
233 
 
234 
/* Memory Protection Unit */
235 
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
236 
typedef struct
237 
{
238 
  __I  uint32_t TYPE;                         /*!< MPU Type Register                               */
239 
  __IO uint32_t CTRL;                         /*!< MPU Control Register                            */
240 
  __IO uint32_t RNR;                          /*!< MPU Region RNRber Register                      */
241 
  __IO uint32_t RBAR;                         /*!< MPU Region Base Address Register                */
242 
  __IO uint32_t RASR;                         /*!< MPU Region Attribute and Size Register          */
243 
  __IO uint32_t RBAR_A1;                      /*!< MPU Alias 1 Region Base Address Register        */
244 
  __IO uint32_t RASR_A1;                      /*!< MPU Alias 1 Region Attribute and Size Register  */
245 
  __IO uint32_t RBAR_A2;                      /*!< MPU Alias 2 Region Base Address Register        */
246 
  __IO uint32_t RASR_A2;                      /*!< MPU Alias 2 Region Attribute and Size Register  */
247 
  __IO uint32_t RBAR_A3;                      /*!< MPU Alias 3 Region Base Address Register        */
248 
  __IO uint32_t RASR_A3;                      /*!< MPU Alias 3 Region Attribute and Size Register  */
249 
} MPU_Type;
250 
#endif
251 
 
252 
 
253 
/* Core Debug Register */
254 
typedef struct
255 
{
256 
  __IO uint32_t DHCSR;                        /*!< Debug Halting Control and Status Register       */
257 
  __O  uint32_t DCRSR;                        /*!< Debug Core Register Selector Register           */
258 
  __IO uint32_t DCRDR;                        /*!< Debug Core Register Data Register               */
259 
  __IO uint32_t DEMCR;                        /*!< Debug Exception and Monitor Control Register    */
260 
} CoreDebug_Type;
261 
 
262 
 
263 
/* Memory mapping of Cortex-M3 Hardware */
264 
#define SCS_BASE            (0xE000E000)                              /*!< System Control Space Base Address    */
265 
#define ITM_BASE            (0xE0000000)                              /*!< ITM Base Address                     */
266 
#define CoreDebug_BASE      (0xE000EDF0)                              /*!< Core Debug Base Address              */
267 
#define SysTick_BASE        (SCS_BASE +  0x0010)                      /*!< SysTick Base Address                 */
268 
#define NVIC_BASE           (SCS_BASE +  0x0100)                      /*!< NVIC Base Address                    */
269 
#define SCB_BASE            (SCS_BASE +  0x0D00)                      /*!< System Control Block Base Address    */
270 
 
271 
#define InterruptType       ((InterruptType_Type *) SCS_BASE)         /*!< Interrupt Type Register              */
272 
#define SCB                 ((SCB_Type *)           SCB_BASE)         /*!< SCB configuration struct             */
273 
#define SysTick             ((SysTick_Type *)       SysTick_BASE)     /*!< SysTick configuration struct         */
274 
#define NVIC                ((NVIC_Type *)          NVIC_BASE)        /*!< NVIC configuration struct            */
275 
#define ITM                 ((ITM_Type *)           ITM_BASE)         /*!< ITM configuration struct             */
276 
#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct      */
277 
 
278 
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
279 
  #define MPU_BASE          (SCS_BASE +  0x0D90)                      /*!< Memory Protection Unit               */
280 
  #define MPU               ((MPU_Type*)            MPU_BASE)         /*!< Memory Protection Unit               */
281 
#endif
282 
 
283 
 
284 
 
285 
/*******************************************************************************
286 
 *                Hardware Abstraction Layer
287 
 ******************************************************************************/
288 
 
289 
 
290 
#if defined ( __CC_ARM   )
291 
  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
292 
  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
293 
 
294 
#elif defined ( __ICCARM__ )
295 
  #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler           */
296 
  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
297 
  #define __NOP           __no_operation                              /*!< no operation intrinsic in IAR Compiler */
298 
 
299 
#elif defined   (  __GNUC__  )
300 
  #define __ASM            asm                                        /*!< asm keyword for GNU Compiler          */
301 
  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
302 
 
303 
#endif
304 
 
305 
 
306 
/* ###################  Compiler specific Intrinsics  ########################### */
307 
 
308 
#if defined ( __CC_ARM   ) /*------------------RealView Compiler -----------------*/
309 
/* ARM armcc specific functions */
310 
 
311 
#define __enable_fault_irq                __enable_fiq
312 
#define __disable_fault_irq               __disable_fiq
313 
 
314 
#define __NOP                             __nop
315 
#define __WFI                             __wfi
316 
#define __WFE                             __wfe
317 
#define __SEV                             __sev
318 
#define __ISB()                           __isb(0)
319 
#define __DSB()                           __dsb(0)
320 
#define __DMB()                           __dmb(0)
321 
#define __REV                             __rev
322 
#define __RBIT                            __rbit
323 
#define __LDREXB(ptr)                     ((unsigned char ) __ldrex(ptr))
324 
#define __LDREXH(ptr)                     ((unsigned short) __ldrex(ptr))
325 
#define __LDREXW(ptr)                     ((unsigned int  ) __ldrex(ptr))
326 
#define __STREXB(value, ptr)              __strex(value, ptr)
327 
#define __STREXH(value, ptr)              __strex(value, ptr)
328 
#define __STREXW(value, ptr)              __strex(value, ptr)
329 
 
330 
 
331 
  /* intrinsic unsigned long long __ldrexd(volatile void *ptr) */
332 
  /* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */
333 
  /* intrinsic void __enable_irq();     */
334 
  /* intrinsic void __disable_irq();    */
335 
 
336 
 
337 
/**
338 
 * @brief  Return the Process Stack Pointer
339 
 *
340 
 * @param  none
341 
 * @return uint32_t ProcessStackPointer
342 
 *
343 
 * Return the actual process stack pointer
344 
 */
345 
extern uint32_t __get_PSP(void);
346 
 
347 
/**
348 
 * @brief  Set the Process Stack Pointer
349 
 *
350 
 * @param  uint32_t Process Stack Pointer
351 
 * @return none
352 
 *
353 
 * Assign the value ProcessStackPointer to the MSP
354 
 * (process stack pointer) Cortex processor register
355 
 */
356 
extern void __set_PSP(uint32_t topOfProcStack);
357 
 
358 
/**
359 
 * @brief  Return the Main Stack Pointer
360 
 *
361 
 * @param  none
362 
 * @return uint32_t Main Stack Pointer
363 
 *
364 
 * Return the current value of the MSP (main stack pointer)
365 
 * Cortex processor register
366 
 */
367 
extern uint32_t __get_MSP(void);
368 
 
369 
/**
370 
 * @brief  Set the Main Stack Pointer
371 
 *
372 
 * @param  uint32_t Main Stack Pointer
373 
 * @return none
374 
 *
375 
 * Assign the value mainStackPointer to the MSP
376 
 * (main stack pointer) Cortex processor register
377 
 */
378 
extern void __set_MSP(uint32_t topOfMainStack);
379 
 
380 
/**
381 
 * @brief  Reverse byte order in unsigned short value
382 
 *
383 
 * @param  uint16_t value to reverse
384 
 * @return uint32_t reversed value
385 
 *
386 
 * Reverse byte order in unsigned short value
387 
 */
388 
extern uint32_t __REV16(uint16_t value);
389 
 
390 
/*
391 
 * @brief  Reverse byte order in signed short value with sign extension to integer
392 
 *
393 
 * @param  int16_t value to reverse
394 
 * @return int32_t reversed value
395 
 *
396 
 * Reverse byte order in signed short value with sign extension to integer
397 
 */
398 
extern int32_t __REVSH(int16_t value);
399 
 
400 
 
401 
#if (__ARMCC_VERSION < 400000)
402 
 
403 
/**
404 
 * @brief  Remove the exclusive lock created by ldrex
405 
 *
406 
 * @param  none
407 
 * @return none
408 
 *
409 
 * Removes the exclusive lock which is created by ldrex.
410 
 */
411 
extern void __CLREX(void);
412 
 
413 
/**
414 
 * @brief  Return the Base Priority value
415 
 *
416 
 * @param  none
417 
 * @return uint32_t BasePriority
418 
 *
419 
 * Return the content of the base priority register
420 
 */
421 
extern uint32_t __get_BASEPRI(void);
422 
 
423 
/**
424 
 * @brief  Set the Base Priority value
425 
 *
426 
 * @param  uint32_t BasePriority
427 
 * @return none
428 
 *
429 
 * Set the base priority register
430 
 */
431 
extern void __set_BASEPRI(uint32_t basePri);
432 
 
433 
/**
434 
 * @brief  Return the Priority Mask value
435 
 *
436 
 * @param  none
437 
 * @return uint32_t PriMask
438 
 *
439 
 * Return the state of the priority mask bit from the priority mask
440 
 * register
441 
 */
442 
extern uint32_t __get_PRIMASK(void);
443 
 
444 
/**
445 
 * @brief  Set the Priority Mask value
446 
 *
447 
 * @param  uint32_t PriMask
448 
 * @return none
449 
 *
450 
 * Set the priority mask bit in the priority mask register
451 
 */
452 
extern void __set_PRIMASK(uint32_t priMask);
453 
 
454 
/**
455 
 * @brief  Return the Fault Mask value
456 
 *
457 
 * @param  none
458 
 * @return uint32_t FaultMask
459 
 *
460 
 * Return the content of the fault mask register
461 
 */
462 
extern uint32_t __get_FAULTMASK(void);
463 
 
464 
/**
465 
 * @brief  Set the Fault Mask value
466 
 *
467 
 * @param  uint32_t faultMask value
468 
 * @return none
469 
 *
470 
 * Set the fault mask register
471 
 */
472 
extern void __set_FAULTMASK(uint32_t faultMask);
473 
 
474 
/**
475 
 * @brief  Return the Control Register value
476 
 *
477 
 * @param  none
478 
 * @return uint32_t Control value
479 
 *
480 
 * Return the content of the control register
481 
 */
482 
extern uint32_t __get_CONTROL(void);
483 
 
484 
/**
485 
 * @brief  Set the Control Register value
486 
 *
487 
 * @param  uint32_t Control value
488 
 * @return none
489 
 *
490 
 * Set the control register
491 
 */
492 
extern void __set_CONTROL(uint32_t control);
493 
 
494 
#else  /* (__ARMCC_VERSION >= 400000)  */
495 
 
496 
 
497 
/**
498 
 * @brief  Remove the exclusive lock created by ldrex
499 
 *
500 
 * @param  none
501 
 * @return none
502 
 *
503 
 * Removes the exclusive lock which is created by ldrex.
504 
 */
505 
#define __CLREX                           __clrex
506 
 
507 
/**
508 
 * @brief  Return the Base Priority value
509 
 *
510 
 * @param  none
511 
 * @return uint32_t BasePriority
512 
 *
513 
 * Return the content of the base priority register
514 
 */
515 
static __INLINE uint32_t  __get_BASEPRI(void)
516 
{
517 
  register uint32_t __regBasePri         __ASM("basepri");
518 
  return(__regBasePri);
519 
}
520 
 
521 
/**
522 
 * @brief  Set the Base Priority value
523 
 *
524 
 * @param  uint32_t BasePriority
525 
 * @return none
526 
 *
527 
 * Set the base priority register
528 
 */
529 
static __INLINE void __set_BASEPRI(uint32_t basePri)
530 
{
531 
  register uint32_t __regBasePri         __ASM("basepri");
532 
  __regBasePri = (basePri & 0x1ff);
533 
}
534 
 
535 
/**
536 
 * @brief  Return the Priority Mask value
537 
 *
538 
 * @param  none
539 
 * @return uint32_t PriMask
540 
 *
541 
 * Return the state of the priority mask bit from the priority mask
542 
 * register
543 
 */
544 
static __INLINE uint32_t __get_PRIMASK(void)
545 
{
546 
  register uint32_t __regPriMask         __ASM("primask");
547 
  return(__regPriMask);
548 
}
549 
 
550 
/**
551 
 * @brief  Set the Priority Mask value
552 
 *
553 
 * @param  uint32_t PriMask
554 
 * @return none
555 
 *
556 
 * Set the priority mask bit in the priority mask register
557 
 */
558 
static __INLINE void __set_PRIMASK(uint32_t priMask)
559 
{
560 
  register uint32_t __regPriMask         __ASM("primask");
561 
  __regPriMask = (priMask);
562 
}
563 
 
564 
/**
565 
 * @brief  Return the Fault Mask value
566 
 *
567 
 * @param  none
568 
 * @return uint32_t FaultMask
569 
 *
570 
 * Return the content of the fault mask register
571 
 */
572 
static __INLINE uint32_t __get_FAULTMASK(void)
573 
{
574 
  register uint32_t __regFaultMask       __ASM("faultmask");
575 
  return(__regFaultMask);
576 
}
577 
 
578 
/**
579 
 * @brief  Set the Fault Mask value
580 
 *
581 
 * @param  uint32_t faultMask value
582 
 * @return none
583 
 *
584 
 * Set the fault mask register
585 
 */
586 
static __INLINE void __set_FAULTMASK(uint32_t faultMask)
587 
{
588 
  register uint32_t __regFaultMask       __ASM("faultmask");
589 
  __regFaultMask = (faultMask & 1);
590 
}
591 
 
592 
/**
593 
 * @brief  Return the Control Register value
594 
 *
595 
 * @param  none
596 
 * @return uint32_t Control value
597 
 *
598 
 * Return the content of the control register
599 
 */
600 
static __INLINE uint32_t __get_CONTROL(void)
601 
{
602 
  register uint32_t __regControl         __ASM("control");
603 
  return(__regControl);
604 
}
605 
 
606 
/**
607 
 * @brief  Set the Control Register value
608 
 *
609 
 * @param  uint32_t Control value
610 
 * @return none
611 
 *
612 
 * Set the control register
613 
 */
614 
static __INLINE void __set_CONTROL(uint32_t control)
615 
{
616 
  register uint32_t __regControl         __ASM("control");
617 
  __regControl = control;
618 
}
619 
 
620 
#endif /* __ARMCC_VERSION  */
621 
 
622 
 
623 
 
624 
#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
625 
/* IAR iccarm specific functions */
626 
 
627 
#define __enable_irq                              __enable_interrupt        /*!< global Interrupt enable */
628 
#define __disable_irq                             __disable_interrupt       /*!< global Interrupt disable */
629 
 
630 
static __INLINE void __enable_fault_irq()         { __ASM ("cpsie f"); }
631 
static __INLINE void __disable_fault_irq()        { __ASM ("cpsid f"); }
632 
 
633 
static __INLINE  void __WFI()                     { __ASM ("wfi"); }
634 
static __INLINE  void __WFE()                     { __ASM ("wfe"); }
635 
static __INLINE  void __SEV()                     { __ASM ("sev"); }
636 
static __INLINE  void __CLREX()                   { __ASM ("clrex"); }
637 
 
638 
/**
639 
 * @brief  Return the Process Stack Pointer
640 
 *
641 
 * @param  none
642 
 * @return uint32_t ProcessStackPointer
643 
 *
644 
 * Return the actual process stack pointer
645 
 */
646 
extern uint32_t __get_PSP(void);
647 
 
648 
/**
649 
 * @brief  Set the Process Stack Pointer
650 
 *
651 
 * @param  uint32_t Process Stack Pointer
652 
 * @return none
653 
 *
654 
 * Assign the value ProcessStackPointer to the MSP
655 
 * (process stack pointer) Cortex processor register
656 
 */
657 
extern void __set_PSP(uint32_t topOfProcStack);
658 
 
659 
/**
660 
 * @brief  Return the Main Stack Pointer
661 
 *
662 
 * @param  none
663 
 * @return uint32_t Main Stack Pointer
664 
 *
665 
 * Return the current value of the MSP (main stack pointer)
666 
 * Cortex processor register
667 
 */
668 
extern uint32_t __get_MSP(void);
669 
 
670 
/**
671 
 * @brief  Set the Main Stack Pointer
672 
 *
673 
 * @param  uint32_t Main Stack Pointer
674 
 * @return none
675 
 *
676 
 * Assign the value mainStackPointer to the MSP
677 
 * (main stack pointer) Cortex processor register
678 
 */
679 
extern void __set_MSP(uint32_t topOfMainStack);
680 
 
681 
/**
682 
 * @brief  Reverse byte order in unsigned short value
683 
 *
684 
 * @param  uint16_t value to reverse
685 
 * @return uint32_t reversed value
686 
 *
687 
 * Reverse byte order in unsigned short value
688 
 */
689 
extern uint32_t __REV16(uint16_t value);
690 
 
691 
/**
692 
 * @brief  Reverse bit order of value
693 
 *
694 
 * @param  uint32_t value to reverse
695 
 * @return uint32_t reversed value
696 
 *
697 
 * Reverse bit order of value
698 
 */
699 
extern uint32_t __RBIT(uint32_t value);
700 
 
701 
/**
702 
 * @brief  LDR Exclusive
703 
 *
704 
 * @param  uint8_t* address
705 
 * @return uint8_t value of (*address)
706 
 *
707 
 * Exclusive LDR command
708 
 */
709 
extern uint8_t __LDREXB(uint8_t *addr);
710 
 
711 
/**
712 
 * @brief  LDR Exclusive
713 
 *
714 
 * @param  uint16_t* address
715 
 * @return uint16_t value of (*address)
716 
 *
717 
 * Exclusive LDR command
718 
 */
719 
extern uint16_t __LDREXH(uint16_t *addr);
720 
 
721 
/**
722 
 * @brief  LDR Exclusive
723 
 *
724 
 * @param  uint32_t* address
725 
 * @return uint32_t value of (*address)
726 
 *
727 
 * Exclusive LDR command
728 
 */
729 
extern uint32_t __LDREXW(uint32_t *addr);
730 
 
731 
/**
732 
 * @brief  STR Exclusive
733 
 *
734 
 * @param  uint8_t *address
735 
 * @param  uint8_t value to store
736 
 * @return uint32_t successful / failed
737 
 *
738 
 * Exclusive STR command
739 
 */
740 
extern uint32_t __STREXB(uint8_t value, uint8_t *addr);
741 
 
742 
/**
743 
 * @brief  STR Exclusive
744 
 *
745 
 * @param  uint16_t *address
746 
 * @param  uint16_t value to store
747 
 * @return uint32_t successful / failed
748 
 *
749 
 * Exclusive STR command
750 
 */
751 
extern uint32_t __STREXH(uint16_t value, uint16_t *addr);
752 
 
753 
/**
754 
 * @brief  STR Exclusive
755 
 *
756 
 * @param  uint32_t *address
757 
 * @param  uint32_t value to store
758 
 * @return uint32_t successful / failed
759 
 *
760 
 * Exclusive STR command
761 
 */
762 
extern uint32_t __STREXW(uint32_t value, uint32_t *addr);
763 
 
764 
 
765 
/* intrinsic void __set_PRIMASK();                                    */
766 
/* intrinsic void __get_PRIMASK();                                    */
767 
/* intrinsic void __set_FAULTMASK();                                  */
768 
/* intrinsic void __get_FAULTMASK();                                  */
769 
/* intrinsic uint32_t __REV(uint32_t value);                          */
770 
/* intrinsic uint32_t __REVSH(uint32_t value);                        */
771 
/* intrinsic unsigned long __STREX(unsigned long, unsigned long);     */
772 
/* intrinsic unsigned long __LDREX(unsigned long *);                  */
773 
 
774 
 
775 
 
776 
#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
777 
/* GNU gcc specific functions */
778 
 
779 
static __INLINE void __NOP()                      { __ASM volatile ("nop"); }
780 
static __INLINE void __enable_irq()               { __ASM volatile ("cpsie i"); }
781 
static __INLINE void __disable_irq()              { __ASM volatile ("cpsid i"); }
782 
 
783 
static __INLINE void __enable_fault_irq()         { __ASM volatile ("cpsie f"); }
784 
static __INLINE void __disable_fault_irq()        { __ASM volatile ("cpsid f"); }
785 
 
786 
static __INLINE void __WFI()                      { __ASM volatile ("wfi");   }
787 
static __INLINE void __WFE()                      { __ASM volatile ("wfe");   }
788 
static __INLINE void __SEV()                      { __ASM volatile ("sev");   }
789 
static __INLINE void __ISB(arg)                   { __ASM volatile ("isb");   }
790 
static __INLINE void __DSB(arg)                   { __ASM volatile ("dsb");   }
791 
static __INLINE void __DMB(arg)                   { __ASM volatile ("dmb");   }
792 
static __INLINE void __CLREX()                    { __ASM volatile ("clrex"); }
793 
 
794 
 
795 
/**
796 
 * @brief  Return the Process Stack Pointer
797 
 *
798 
 * @param  none
799 
 * @return uint32_t ProcessStackPointer
800 
 *
801 
 * Return the actual process stack pointer
802 
 */
803 
extern uint32_t __get_PSP(void);
804 
 
805 
/**
806 
 * @brief  Set the Process Stack Pointer
807 
 *
808 
 * @param  uint32_t Process Stack Pointer
809 
 * @return none
810 
 *
811 
 * Assign the value ProcessStackPointer to the MSP
812 
 * (process stack pointer) Cortex processor register
813 
 */
814 
extern void __set_PSP(uint32_t topOfProcStack);
815 
 
816 
/**
817 
 * @brief  Return the Main Stack Pointer
818 
 *
819 
 * @param  none
820 
 * @return uint32_t Main Stack Pointer
821 
 *
822 
 * Return the current value of the MSP (main stack pointer)
823 
 * Cortex processor register
824 
 */
825 
extern uint32_t __get_MSP(void);
826 
 
827 
/**
828 
 * @brief  Set the Main Stack Pointer
829 
 *
830 
 * @param  uint32_t Main Stack Pointer
831 
 * @return none
832 
 *
833 
 * Assign the value mainStackPointer to the MSP
834 
 * (main stack pointer) Cortex processor register
835 
 */
836 
extern void __set_MSP(uint32_t topOfMainStack);
837 
 
838 
/**
839 
 * @brief  Return the Base Priority value
840 
 *
841 
 * @param  none
842 
 * @return uint32_t BasePriority
843 
 *
844 
 * Return the content of the base priority register
845 
 */
846 
extern uint32_t __get_BASEPRI(void);
847 
 
848 
/**
849 
 * @brief  Set the Base Priority value
850 
 *
851 
 * @param  uint32_t BasePriority
852 
 * @return none
853 
 *
854 
 * Set the base priority register
855 
 */
856 
extern void __set_BASEPRI(uint32_t basePri);
857 
 
858 
/**
859 
 * @brief  Return the Priority Mask value
860 
 *
861 
 * @param  none
862 
 * @return uint32_t PriMask
863 
 *
864 
 * Return the state of the priority mask bit from the priority mask
865 
 * register
866 
 */
867 
extern uint32_t  __get_PRIMASK(void);
868 
 
869 
/**
870 
 * @brief  Set the Priority Mask value
871 
 *
872 
 * @param  uint32_t PriMask
873 
 * @return none
874 
 *
875 
 * Set the priority mask bit in the priority mask register
876 
 */
877 
extern void __set_PRIMASK(uint32_t priMask);
878 
 
879 
/**
880 
 * @brief  Return the Fault Mask value
881 
 *
882 
 * @param  none
883 
 * @return uint32_t FaultMask
884 
 *
885 
 * Return the content of the fault mask register
886 
 */
887 
extern uint32_t __get_FAULTMASK(void);
888 
 
889 
/**
890 
 * @brief  Set the Fault Mask value
891 
 *
892 
 * @param  uint32_t faultMask value
893 
 * @return none
894 
 *
895 
 * Set the fault mask register
896 
 */
897 
extern void __set_FAULTMASK(uint32_t faultMask);
898 
 
899 
/**
900 
 * @brief  Return the Control Register value
901 
*
902 
*  @param  none
903 
*  @return uint32_t Control value
904 
 *
905 
 * Return the content of the control register
906 
 */
907 
extern uint32_t __get_CONTROL(void);
908 
 
909 
/**
910 
 * @brief  Set the Control Register value
911 
 *
912 
 * @param  uint32_t Control value
913 
 * @return none
914 
 *
915 
 * Set the control register
916 
 */
917 
extern void __set_CONTROL(uint32_t control);
918 
 
919 
/**
920 
 * @brief  Reverse byte order in integer value
921 
 *
922 
 * @param  uint32_t value to reverse
923 
 * @return uint32_t reversed value
924 
 *
925 
 * Reverse byte order in integer value
926 
 */
927 
extern uint32_t __REV(uint32_t value);
928 
 
929 
/**
930 
 * @brief  Reverse byte order in unsigned short value
931 
 *
932 
 * @param  uint16_t value to reverse
933 
 * @return uint32_t reversed value
934 
 *
935 
 * Reverse byte order in unsigned short value
936 
 */
937 
extern uint32_t __REV16(uint16_t value);
938 
 
939 
/*
940 
 * Reverse byte order in signed short value with sign extension to integer
941 
 *
942 
 * @param  int16_t value to reverse
943 
 * @return int32_t reversed value
944 
 *
945 
 * @brief  Reverse byte order in signed short value with sign extension to integer
946 
 */
947 
extern int32_t __REVSH(int16_t value);
948 
 
949 
/**
950 
 * @brief  Reverse bit order of value
951 
 *
952 
 * @param  uint32_t value to reverse
953 
 * @return uint32_t reversed value
954 
 *
955 
 * Reverse bit order of value
956 
 */
957 
extern uint32_t __RBIT(uint32_t value);
958 
 
959 
/**
960 
 * @brief  LDR Exclusive
961 
 *
962 
 * @param  uint8_t* address
963 
 * @return uint8_t value of (*address)
964 
 *
965 
 * Exclusive LDR command
966 
 */
967 
extern uint8_t __LDREXB(uint8_t *addr);
968 
 
969 
/**
970 
 * @brief  LDR Exclusive
971 
 *
972 
 * @param  uint16_t* address
973 
 * @return uint16_t value of (*address)
974 
 *
975 
 * Exclusive LDR command
976 
 */
977 
extern uint16_t __LDREXH(uint16_t *addr);
978 
 
979 
/**
980 
 * @brief  LDR Exclusive
981 
 *
982 
 * @param  uint32_t* address
983 
 * @return uint32_t value of (*address)
984 
 *
985 
 * Exclusive LDR command
986 
 */
987 
extern uint32_t __LDREXW(uint32_t *addr);
988 
 
989 
/**
990 
 * @brief  STR Exclusive
991 
 *
992 
 * @param  uint8_t *address
993 
 * @param  uint8_t value to store
994 
 * @return uint32_t successful / failed
995 
 *
996 
 * Exclusive STR command
997 
 */
998 
extern uint32_t __STREXB(uint8_t value, uint8_t *addr);
999 
 
1000 
/**
1001 
 * @brief  STR Exclusive
1002 
 *
1003 
 * @param  uint16_t *address
1004 
 * @param  uint16_t value to store
1005 
 * @return uint32_t successful / failed
1006 
 *
1007 
 * Exclusive STR command
1008 
 */
1009 
extern uint32_t __STREXH(uint16_t value, uint16_t *addr);
1010 
 
1011 
/**
1012 
 * @brief  STR Exclusive
1013 
 *
1014 
 * @param  uint32_t *address
1015 
 * @param  uint32_t value to store
1016 
 * @return uint32_t successful / failed
1017 
 *
1018 
 * Exclusive STR command
1019 
 */
1020 
extern uint32_t __STREXW(uint32_t value, uint32_t *addr);
1021 
 
1022 
 
1023 
#endif
1024 
 
1025 
 
1026 
 
1027 
/* ##########################   NVIC functions  #################################### */
1028 
 
1029 
/**
1030 
 * @brief  Set the Priority Grouping in NVIC Interrupt Controller
1031 
 *
1032 
 * @param  uint32_t priority_grouping is priority grouping field
1033 
 * @return
1034 
 *
1035 
 * Set the priority grouping field using the required unlock sequence.
1036 
 * The parameter priority_grouping is assigned to the field
1037 
 * SCB->AIRCR [10:8] PRIGROUP field.
1038 
 */
1039 
static __INLINE void NVIC_SetPriorityGrouping(uint32_t priority_grouping)
1040 
{
1041 
  uint32_t reg_value=0;
1042 
 
1043 
  reg_value  = SCB->AIRCR;                                                                            /* read old register configuration    */
1044 
  reg_value &= ~((0xFFFFU << 16) | (0x0F << 8));                                                      /* clear bits to change               */
1045 
  reg_value  = ((reg_value | NVIC_AIRCR_VECTKEY | (priority_grouping << 8)));                         /* Insert write key and priorty group */
1046 
  SCB->AIRCR = reg_value;
1047 
}
1048 
 
1049 
/**
1050 
 * @brief  Enable Interrupt in NVIC Interrupt Controller
1051 
 *
1052 
 * @param  IRQn_Type IRQn specifies the interrupt number
1053 
 * @return none
1054 
 *
1055 
 * Enable a device specific interupt in the NVIC interrupt controller.
1056 
 * The interrupt number cannot be a negative value.
1057 
 */
1058 
static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
1059 
{
1060 
  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));                             /* enable interrupt */
1061 
}
1062 
 
1063 
/**
1064 
 * @brief  Disable the interrupt line for external interrupt specified
1065 
 *
1066 
 * @param  IRQn_Type IRQn is the positive number of the external interrupt
1067 
 * @return  none
1068 
 *
1069 
 * Disable a device specific interupt in the NVIC interrupt controller.
1070 
 * The interrupt number cannot be a negative value.
1071 
 */
1072 
static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
1073 
{
1074 
  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));                             /* disable interrupt */
1075 
}
1076 
 
1077 
/**
1078 
 * @brief  Read the interrupt pending bit for a device specific interrupt source
1079 
 *
1080 
 * @param  IRQn_Type IRQn is the number of the device specifc interrupt
1081 
 * @return IRQn_Type Number of pending interrupt or zero
1082 
 *
1083 
 * Read the pending register in NVIC and return the number of the
1084 
 * specified interrupt if its status is pending, otherwise it returns
1085 
 * zero. The interrupt number cannot be a negative value.
1086 
 */
1087 
static __INLINE IRQn_Type NVIC_GetPendingIRQ(IRQn_Type IRQn)
1088 
{
1089 
  return((IRQn_Type) (NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F))));         /* Return Interrupt bit or 'zero' */
1090 
}
1091 
 
1092 
/**
1093 
 * @brief  Set the pending bit for an external interrupt
1094 
 *
1095 
 * @param  IRQn_Type IRQn is the Number of the interrupt
1096 
 * @return  none
1097 
 *
1098 
 * Set the pending bit for the specified interrupt.
1099 
 * The interrupt number cannot be a negative value.
1100 
 */
1101 
static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
1102 
{
1103 
  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));                             /* set interrupt pending */
1104 
}
1105 
 
1106 
/**
1107 
 * @brief  Clear the pending bit for an external interrupt
1108 
 *
1109 
 * @param  IRQn_Type IRQn is the Number of the interrupt
1110 
 * @return  none
1111 
 *
1112 
 * Clear the pending bit for the specified interrupt.
1113 
 * The interrupt number cannot be a negative value.
1114 
 */
1115 
static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
1116 
{
1117 
  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));                             /* Clear pending interrupt */
1118 
}
1119 
 
1120 
/**
1121 
 * @brief  Read the active bit for an external interrupt
1122 
 *
1123 
 * @param  IRQn_Type IRQn is the Number of the interrupt
1124 
 * @return IRQn_Type Number of pending interrupt or zero
1125 
 *
1126 
 * Read the active register in NVIC and returns the number of the
1127 
 * specified interrupt if its status is active, otherwise it
1128 
 * returns zero. The interrupt number cannot be a negative value.
1129 
 */
1130 
static __INLINE IRQn_Type NVIC_GetActive(IRQn_Type IRQn)
1131 
{
1132 
  return((IRQn_Type)(NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F))));                        /* Return Interruptnumber or 'zero' */
1133 
}
1134 
 
1135 
/**
1136 
 * @brief  Set the priority for an interrupt
1137 
 *
1138 
 * @param  IRQn_Type IRQn is the Number of the interrupt
1139 
 * @param  priority is the priority for the interrupt
1140 
 * @return  none
1141 
 *
1142 
 * Set the priority for the specified interrupt. The interrupt
1143 
 * number can be positive to specify an external (device specific)
1144 
 * interrupt, or negative to specify an internal (core) interrupt. \n
1145 
 *
1146 
 * Note: The priority cannot be set for every core interrupt.
1147 
 */
1148 
static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, int32_t priority)
1149 
{
1150 
  if(IRQn < 0) {
1151 
    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); }  /* set Priority for Cortex-M3 System Interrupts */
1152 
  else {
1153 
    //NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }         /* set Priority for device specific Interrupts      */
1154 
    NVIC->IP[(uint32_t)(IRQn)] = (priority & 0xff);    }         /* set Priority for device specific Interrupts      */
1155 
}
1156 
 
1157 
/**
1158 
 * @brief  Read the priority for an interrupt
1159 
 *
1160 
 * @param  IRQn_Type IRQn is the Number of the interrupt
1161 
 * @return priority is the priority for the interrupt
1162 
 *
1163 
 * Read the priority for the specified interrupt. The interrupt
1164 
 * number can be positive to specify an external (device specific)
1165 
 * interrupt, or negative to specify an internal (core) interrupt.
1166 
 *
1167 
 * The returned priority value is automatically aligned to the implemented
1168 
 * priority bits of the microcontroller.
1169 
 *
1170 
 * Note: The priority cannot be set for every core interrupt.
1171 
 */
1172 
static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
1173 
{
1174 
 
1175 
  if(IRQn < 0) {
1176 
    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  }              /* get priority for Cortex-M3 system interrupts   */
1177 
  else {
1178 
    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  }              /* get priority for device specific interrupts    */
1179 
}
1180 
 
1181 
 
1182 
 
1183 
/* ##################################    SysTick function  ############################################ */
1184 
 
1185 
#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0)
1186 
 
1187 
/* SysTick constants */
1188 
#define SYSTICK_ENABLE              0                                          /* Config-Bit to start or stop the SysTick Timer                         */
1189 
#define SYSTICK_TICKINT             1                                          /* Config-Bit to enable or disable the SysTick interrupt                 */
1190 
#define SYSTICK_CLKSOURCE           2                                          /* Clocksource has the offset 2 in SysTick Control and Status Register   */
1191 
#define SYSTICK_MAXCOUNT       ((1<<24) -1)                                    /* SysTick MaxCount                                                      */
1192 
 
1193 
/**
1194 
 * @brief  Initialize and start the SysTick counter and its interrupt.
1195 
 *
1196 
 * @param  uint32_t ticks is the number of ticks between two interrupts
1197 
 * @return  none
1198 
 *
1199 
 * Initialise the system tick timer and its interrupt and start the
1200 
 * system tick timer / counter in free running mode to generate
1201 
 * periodical interrupts.
1202 
 */
1203 
static __INLINE uint32_t SysTick_Config(uint32_t ticks)
1204 
{
1205 
  if (ticks > SYSTICK_MAXCOUNT)  return (1);                                                /* Reload value impossible */
1206 
 
1207 
  SysTick->LOAD  =  (ticks & SYSTICK_MAXCOUNT) - 1;                                         /* set reload register */
1208 
  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);                               /* set Priority for Cortex-M0 System Interrupts */
1209 
  SysTick->VAL   =  (0x00);                                                                 /* Load the SysTick Counter Value */
1210 
  SysTick->CTRL = (1 << SYSTICK_CLKSOURCE) | (1<<SYSTICK_ENABLE) | (1<<SYSTICK_TICKINT);    /* Enable SysTick IRQ and SysTick Timer */
1211 
  return (0);                                                                               /* Function successful */
1212 
}
1213 
 
1214 
#endif
1215 
 
1216 
 
1217 
 
1218 
 
1219 
 
1220 
/* ##################################    Reset function  ############################################ */
1221 
 
1222 
/**
1223 
 * @brief  Initiate a system reset request.
1224 
 *
1225 
 * @param   none
1226 
 * @return  none
1227 
 *
1228 
 * Initialize a system reset request to reset the MCU
1229 
 */
1230 
static __INLINE void NVIC_SystemReset(void)
1231 
{
1232 
  SCB->AIRCR  = (NVIC_AIRCR_VECTKEY | (SCB->AIRCR & (0x700)) | (1<<NVIC_SYSRESETREQ));      /* Keep priority group unchanged */
1233 
}
1234 
 
1235 
 
1236 
/* ##################################    Debug Output  function  ############################################ */
1237 
 
1238 
 
1239 
/**
1240 
 * @brief  Outputs a character via the ITM channel 0
1241 
 *
1242 
 * @param   uint32_t character to output
1243 
 * @return  uint32_t input character
1244 
 *
1245 
 * The function outputs a character via the ITM channel 0.
1246 
 * The function returns when no debugger is connected that has booked the output.
1247 
 * It is blocking when a debugger is connected, but the previous character send is not transmitted.
1248 
 */
1249 
static __INLINE uint32_t ITM_SendChar (uint32_t ch)
1250 
{
1251 
  if(ch == '\n') ITM_SendChar('\r');
1252 
 
1253 
  if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA)  &&
1254 
      (ITM->TCR & ITM_TCR_ITMENA)                  &&
1255 
      (ITM->TER & (1UL << 0))  )
1256 
  {
1257 
    while (ITM->PORT[0].u32 == 0);
1258 
    ITM->PORT[0].u8 = (uint8_t) ch;
1259 
  }
1260 
  return (ch);
1261 
}
1262 
 
1263 
#endif
1264 
 
1265 
/*lint -restore */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.