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jeremybenn |
/* ----------------------------------------------------------------------------
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* ATMEL Microcontroller Software Support
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* ----------------------------------------------------------------------------
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* Copyright (c) 2008, Atmel Corporation
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*
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* - Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the disclaimer below.
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*
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* Atmel's name may not be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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* ----------------------------------------------------------------------------
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*/
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MODULE ?cp15
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;; Forward declaration of sections.
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SECTION IRQ_STACK:DATA:NOROOT(2)
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SECTION CSTACK:DATA:NOROOT(3)
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//------------------------------------------------------------------------------
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// Headers
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//------------------------------------------------------------------------------
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#define __ASSEMBLY__
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#include "board.h"
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#ifdef CP15_PRESENT
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//------------------------------------------------------------------------------
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/// Functions to access CP15 coprocessor register
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//------------------------------------------------------------------------------
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PUBLIC _readControlRegister
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PUBLIC _writeControlRegister
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PUBLIC _waitForInterrupt
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PUBLIC _writeTTB
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PUBLIC _writeDomain
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PUBLIC _writeITLBLockdown
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PUBLIC _prefetchICacheLine
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//------------------------------------------------------------------------------
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/// Control Register c1
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/// Register c1 is the Control Register for the ARM926EJ-S processor.
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/// This register specifies the configuration used to enable and disable the
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/// caches and MMU. It is recommended that you access this register using a
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/// read-modify-write sequence.
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//------------------------------------------------------------------------------
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// CP15 Read Control Register
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_readControlRegister:
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mov r0, #0
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mrc p15, 0, r0, c1, c0, 0
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bx lr
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// CP15 Write Control Register
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_writeControlRegister:
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mcr p15, 0, r0, c1, c0, 0
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bx lr
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//------------------------------------------------------------------------------
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/// CP15 Wait For Interrupt operation
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/// The purpose of the Wait For Interrupt operation is to put the processor in
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/// to a low power state.
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/// This puts the processor into a low-power state and stops it executing more
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/// instructions until an interrupt, or debug request occurs, regardless of
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/// whether the interrupts are disabled by the masks in the CPSR.
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/// When an interrupt does occur, the MCR instruction completes and the IRQ or
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/// FIQ handler is entered as normal. The return link in r14_irq or r14_fiq
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/// contains the address of the MCR instruction plus 8, so that the normal
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/// instruction used for interrupt return (SUBS PC,R14,#4) returns to the
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/// instruction following the MCR.
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/// Wait For Interrupt : MCR p15, 0, <Rd>, c7, c0, 4
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//------------------------------------------------------------------------------
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_waitForInterrupt:
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mov r0, #0
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mcr p15, 0, r0, c7, c0, 4
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bx lr
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//------------------------------------------------------------------------------
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/// CP15 Translation Table Base Register c2
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/// Register c2 is the Translation Table Base Register (TTBR), for the base
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/// address of the first-level translation table.
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/// Reading from c2 returns the pointer to the currently active first-level
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/// translation table in bits [31:14] and an Unpredictable value in bits [13:0].
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/// Writing to register c2 updates the pointer to the first-level translation
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/// table from the value in bits [31:14] of the written value. Bits [13:0]
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/// Should Be Zero.
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/// You can use the following instructions to access the TTBR:
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/// Read TTBR : MRC p15, 0, <Rd>, c2, c0, 0
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/// Write TTBR : MCR p15, 0, <Rd>, c2, c0, 0
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//------------------------------------------------------------------------------
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_writeTTB:
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MCR p15, 0, r0, c2, c0, 0
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bx lr
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//------------------------------------------------------------------------------
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/// Domain Access Control Register c3
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/// Read domain access permissions : MRC p15, 0, <Rd>, c3, c0, 0
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/// Write domain access permissions : MCR p15, 0, <Rd>, c3, c0, 0
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//------------------------------------------------------------------------------
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_writeDomain:
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MCR p15, 0, r0, c3, c0, 0
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bx lr
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//------------------------------------------------------------------------------
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/// TLB Lockdown Register c10
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/// The TLB Lockdown Register controls where hardware page table walks place the
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/// TLB entry, in the set associative region or the lockdown region of the TLB,
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/// and if in the lockdown region, which entry is written. The lockdown region
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/// of the TLB contains eight entries. See TLB structure for a description of
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/// the structure of the TLB.
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/// Read data TLB lockdown victim : MRC p15,0,<Rd>,c10,c0,0
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/// Write data TLB lockdown victim : MCR p15,0,<Rd>,c10,c0,0
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//------------------------------------------------------------------------------
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_writeITLBLockdown:
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MCR p15, 0, r0, c10, c0, 0
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bx lr
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//------------------------------------------------------------------------------
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/// Prefetch ICache line
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/// Performs an ICache lookup of the specified modified virtual address.
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/// If the cache misses, and the region is cacheable, a linefill is performed.
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/// Prefetch ICache line (MVA): MCR p15, 0, <Rd>, c7, c13, 1
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//------------------------------------------------------------------------------
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_prefetchICacheLine:
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MCR p15, 0, r0, c7, c13, 1
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bx lr
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#endif
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END
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