OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [CORTEX_AT91SAM3U256_IAR/] [AT91Lib/] [peripherals/] [dma/] [dma.h] - Blame information for rev 763

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 580 jeremybenn
/* ----------------------------------------------------------------------------
2
 *         ATMEL Microcontroller Software Support  -  ROUSSET  -
3
 * ----------------------------------------------------------------------------
4
 * Copyright (c) 2006, Atmel Corporation
5
 
6
 * All rights reserved.
7
 *
8
 * Redistribution and use in source and binary forms, with or without
9
 * modification, are permitted provided that the following conditions are met:
10
 *
11
 * - Redistributions of source code must retain the above copyright notice,
12
 * this list of conditions and the disclaiimer below.
13
 *
14
 * - Redistributions in binary form must reproduce the above copyright notice,
15
 * this list of conditions and the disclaimer below in the documentation and/or
16
 * other materials provided with the distribution.
17
 *
18
 * Atmel's name may not be used to endorse or promote products derived from
19
 * this software without specific prior written permission.
20
 *
21
 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
22
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
23
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
24
 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
25
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
27
 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
28
 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
29
 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30
 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31
 * ----------------------------------------------------------------------------
32
 */
33
 
34
//------------------------------------------------------------------------------
35
/// \dir
36
/// !Purpose
37
/// 
38
/// Interface for configuration the %DMA controller(DMAC).
39
///
40
/// !Usage
41
///
42
/// -# Enable or disable the a DMAC controller with 
43
///    DMA_Enable() and or DMA_Disable().
44
/// -# Enable or disable %Dma interrupt using DMA_EnableIt()
45
///    or DMA_DisableIt().
46
/// -# Get %Dma interrupt status by DMA_GetStatus().
47
/// -# Enable or disable specified %Dma channel with 
48
///    DMA_EnableChannel() or DMA_DisableChannel().
49
/// -# Get %Dma channel status by DMA_GetChannelStatus().
50
/// -# Configure source and/or destination start address with
51
///    DMA_SetSourceAddr() and/or DMA_SetDestAddr().
52
/// -# Set %Dma descriptor address using DMA_SetDescriptorAddr().
53
/// -# Set source transfer buffer size with DMA_SetSourceBufferSize().
54
/// -# Configure source and/or destination transfer mode with
55
///    DMA_SetSourceBufferMode() and/or DMA_SetDestBufferMode().
56
/// -# Configure source and/or destination Picture-In-Picutre 
57
///    mode with DMA_SPIPconfiguration() and/or DMA_DPIPconfiguration().
58
//------------------------------------------------------------------------------
59
 
60
#ifndef DMA_H
61
#define DMA_H
62
 
63
#include <board.h>
64
 
65
//------------------------------------------------------------------------------
66
//         Definitions
67
//------------------------------------------------------------------------------
68
#define DMA_CHANNEL_0            0
69
#define DMA_CHANNEL_1            1
70
#define DMA_CHANNEL_2            2
71
#define DMA_CHANNEL_3            3
72
#define DMA_CHANNEL_4            4
73
#define DMA_CHANNEL_5            5
74
#define DMA_CHANNEL_6            6
75
#define DMA_CHANNEL_7            7
76
 
77
#if defined(CHIP_DMA_CHANNEL_NUM)
78
#define DMA_CHANNEL_NUM      CHIP_DMA_CHANNEL_NUM
79
#endif
80
 
81
#define DMA_TRANSFER_SINGLE      0
82
#define DMA_TRANSFER_LLI         1  
83
#define DMA_TRANSFER_RELOAD      2
84
#define DMA_TRANSFER_CONTIGUOUS  3
85
 
86
 
87
#define DMA_ENA                  (1 << 0)
88
#define DMA_DIS                  (1 << 0)
89
#define DMA_SUSP                 (1 << 8)
90
#define DMA_KEEPON               (1 << 24)
91
 
92
#define DMA_BTC                  (1 << 0)
93
#define DMA_CBTC                 (1 << 8)
94
#define DMA_ERR                  (1 << 16)
95
 
96
#if defined(at91sam9m10) || defined(at91sam9m11) || defined(at91sam3u4)
97
    #define AT91C_SRC_DSCR AT91C_HDMA_SRC_DSCR
98
    #define AT91C_DST_DSCR AT91C_HDMA_DST_DSCR
99
    #define AT91C_SRC_INCR AT91C_HDMA_SRC_ADDRESS_MODE
100
    #define AT91C_DST_INCR AT91C_HDMA_DST_ADDRESS_MODE
101
    #define AT91C_SRC_PER  AT91C_HDMA_SRC_PER
102
    #define AT91C_DST_PER  AT91C_HDMA_DST_PER
103
    #define AT91C_SRC_REP  AT91C_HDMA_SRC_REP
104
    #define AT91C_DST_REP  AT91C_HDMA_DST_REP
105
    #define AT91C_SRC_PIP  AT91C_HDMA_SRC_PIP
106
    #define AT91C_DST_PIP  AT91C_HDMA_DST_PIP
107
 
108
    #define AT91C_BTC             (0xFF <<  0) 
109
    #define AT91C_CBTC            (0xFF <<  8) 
110
    #define AT91C_ERR             (0xFF << 16) 
111
#endif    
112
 
113
//------------------------------------------------------------------------------
114
//         Exported functions
115
//------------------------------------------------------------------------------
116
 
117
extern void DMA_Config(unsigned int flag);
118
 
119
extern void DMA_Enable(void);
120
 
121
extern void DMA_Disable(void);
122
 
123
extern void DMA_EnableChannel(unsigned int channel);
124
 
125
extern void DMA_DisableChannel(unsigned int channel);
126
 
127
extern void DMA_KeeponChannel(unsigned int channel);
128
 
129
extern void DMA_ClearAutoMode(unsigned int channel);
130
 
131
extern unsigned int DMA_GetChannelStatus(void);
132
 
133
extern unsigned int DMA_GetStatus(void);
134
 
135
extern unsigned int DMA_GetInterruptMask(void);
136
 
137
extern unsigned int DMA_GetMaskedStatus(void);
138
 
139
extern void DMA_EnableIt (unsigned int flag);
140
 
141
extern void DMA_DisableIt (unsigned int flag);
142
 
143
extern void DMA_SetSourceAddr(unsigned char channel, unsigned int address);
144
 
145
extern void DMA_SetDestinationAddr(unsigned char channel, unsigned int address);
146
 
147
extern void DMA_SetDescriptorAddr(unsigned char channel, unsigned int address);
148
 
149
extern void DMA_SetSourceBufferSize(unsigned char channel,
150
                             unsigned int size,
151
                             unsigned char sourceWidth,
152
                             unsigned char desDMAdth,
153
                             unsigned char done);
154
 
155
extern void DMA_SetSourceBufferMode(unsigned char channel,
156
                             unsigned char transferMode,
157
                             unsigned char addressingType);
158
 
159
extern void DMA_SetDestBufferMode(unsigned char channel,
160
                             unsigned char transferMode,
161
                             unsigned char addressingType);
162
 
163
extern void DMA_SetConfiguration(unsigned char channel, unsigned int value);
164
 
165
extern void DMA_SPIPconfiguration(unsigned char channel,
166
                     unsigned int pipHole, unsigned int pipBoundary);
167
 
168
extern void DMA_DPIPconfiguration(unsigned char channel,
169
                     unsigned int pipHole, unsigned int pipBoundary);
170
 
171
#endif //#ifndef DMA_H

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.