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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [CORTEX_AT91SAM3U256_IAR/] [AT91Lib/] [peripherals/] [rstc/] [rstc.c] - Blame information for rev 580

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1 580 jeremybenn 
/* ----------------------------------------------------------------------------
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 *         ATMEL Microcontroller Software Support
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 * ----------------------------------------------------------------------------
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 * Copyright (c) 2008, Atmel Corporation
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 *
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 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions are met:
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 *
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 * - Redistributions of source code must retain the above copyright notice,
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 * this list of conditions and the disclaimer below.
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 *
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 * Atmel's name may not be used to endorse or promote products derived from
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 * this software without specific prior written permission.
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 *
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 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 * ----------------------------------------------------------------------------
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 */
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//-----------------------------------------------------------------------------
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//         Headers
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//-----------------------------------------------------------------------------
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#include <board.h>
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//-----------------------------------------------------------------------------
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//         Defines
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//-----------------------------------------------------------------------------
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/// Keywords to write to the reset registers
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#define RSTC_KEY_PASSWORD       (0xA5 << 24)
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//-----------------------------------------------------------------------------
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//         Exported functions
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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/// Configure the mode of the RSTC peripheral.
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/// The configuration is computed by the lib (AT91C_RSTC_*).
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/// \param rmr Desired mode configuration.
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//-----------------------------------------------------------------------------
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void RSTC_ConfigureMode(unsigned int rmr)
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{
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    rmr &= ~AT91C_RSTC_KEY;
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    AT91C_BASE_RSTC->RSTC_RMR = rmr | RSTC_KEY_PASSWORD;
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}
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//-----------------------------------------------------------------------------
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/// Enable/Disable the detection of a low level on the pin NRST as User Reset
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/// \param enable 1 to enable & 0 to disable.
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//-----------------------------------------------------------------------------
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void RSTC_SetUserResetEnable(unsigned char enable)
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{
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    unsigned int rmr = AT91C_BASE_RSTC->RSTC_RMR & (~AT91C_RSTC_KEY);
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    if (enable) {
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        rmr |=  AT91C_RSTC_URSTEN;
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    }
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    else {
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        rmr &= ~AT91C_RSTC_URSTEN;
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    }
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    AT91C_BASE_RSTC->RSTC_RMR = rmr | RSTC_KEY_PASSWORD;
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}
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//-----------------------------------------------------------------------------
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/// Enable/Disable the interrupt of a User Reset (USRTS bit in RSTC_RST).
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/// \param enable 1 to enable & 0 to disable.
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//-----------------------------------------------------------------------------
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void RSTC_SetUserResetInterruptEnable(unsigned char enable)
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{
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    unsigned int rmr = AT91C_BASE_RSTC->RSTC_RMR & (~AT91C_RSTC_KEY);
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    if (enable) {
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        rmr |=  AT91C_RSTC_URSTIEN;
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    }
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    else {
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        rmr &= ~AT91C_RSTC_URSTIEN;
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    }
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    AT91C_BASE_RSTC->RSTC_RMR = rmr | RSTC_KEY_PASSWORD;
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}
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//-----------------------------------------------------------------------------
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/// Setup the external reset length. The length is asserted during a time of
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/// pow(2, powl+1) Slow Clock(32KHz). The duration is between 60us and 2s.
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/// \param powl   Power length defined.
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//-----------------------------------------------------------------------------
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void RSTC_SetExtResetLength(unsigned char powl)
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{
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    unsigned int rmr = AT91C_BASE_RSTC->RSTC_RMR;
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    rmr &= ~(AT91C_RSTC_KEY | AT91C_RSTC_ERSTL);
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    rmr |=  (powl << 8) & AT91C_RSTC_ERSTL;
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    AT91C_BASE_RSTC->RSTC_RMR = rmr | RSTC_KEY_PASSWORD;
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}
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//-----------------------------------------------------------------------------
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/// Resets the processor.
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//-----------------------------------------------------------------------------
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void RSTC_ProcessorReset(void)
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{
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    AT91C_BASE_RSTC->RSTC_RCR = AT91C_RSTC_PROCRST | RSTC_KEY_PASSWORD;
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}
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//-----------------------------------------------------------------------------
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/// Resets the peripherals.
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//-----------------------------------------------------------------------------
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void RSTC_PeripheralReset(void)
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{
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    AT91C_BASE_RSTC->RSTC_RCR = AT91C_RSTC_PERRST | RSTC_KEY_PASSWORD;
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}
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//-----------------------------------------------------------------------------
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/// Asserts the NRST pin for external resets.
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//-----------------------------------------------------------------------------
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void RSTC_ExtReset(void)
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{
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    AT91C_BASE_RSTC->RSTC_RCR = AT91C_RSTC_EXTRST | RSTC_KEY_PASSWORD;
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}
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//-----------------------------------------------------------------------------
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/// Return NRST pin level ( 1 or 0 ).
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//-----------------------------------------------------------------------------
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unsigned char RSTC_GetNrstLevel(void)
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{
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    if (AT91C_BASE_RSTC->RSTC_RSR & AT91C_RSTC_NRSTL) {
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        return 1;
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    }
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    return 0;
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}
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//-----------------------------------------------------------------------------
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/// Returns 1 if at least one high-to-low transition of NRST (User Reset) has
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/// been detected since the last read of RSTC_RSR.
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//-----------------------------------------------------------------------------
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unsigned char RSTC_IsUserResetDetected(void)
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{
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    if (AT91C_BASE_RSTC->RSTC_RSR & AT91C_RSTC_URSTS) {
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        return 1;
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    }
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    return 0;
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}
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//-----------------------------------------------------------------------------
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/// Return 1 if a software reset command is being performed by the reset
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/// controller. The reset controller is busy.
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//-----------------------------------------------------------------------------
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unsigned char RSTC_IsBusy(void)
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{
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    if (AT91C_BASE_RSTC->RSTC_RSR & AT91C_RSTC_SRCMP) {
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        return 1;
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    }
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    return 0;
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}
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//-----------------------------------------------------------------------------
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/// Get the status
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//-----------------------------------------------------------------------------
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unsigned char RSTC_GetStatus(void)
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{
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    return (AT91C_BASE_RSTC->RSTC_RSR);
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}

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