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//  ----------------------------------------------------------------------------

//          ATMEL Microcontroller Software Support  -  ROUSSET  -

//  ----------------------------------------------------------------------------

//  Copyright (c) 2008, Atmel Corporation

// 

//  All rights reserved.

// 

//  Redistribution and use in source and binary forms, with or without

//  modification, are permitted provided that the following conditions are met:

// 

//  - Redistributions of source code must retain the above copyright notice,

//  this list of conditions and the disclaimer below.

// 

//  Atmel's name may not be used to endorse or promote products derived from

//  this software without specific prior written permission. 

//  

//  DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR

//  IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF

//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE

//  DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,

//  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT

//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,

//  OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF

//  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING

//  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,

//  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

//  ----------------------------------------------------------------------------

// File Name           : AT91SAM3U4.h

// Object              : AT91SAM3U4 definitions

// Generated           : AT91 SW Application Group  03/09/2009 (11:49:34)

// 

// CVS Reference       : /AT91SAM3U4.pl/1.32/Mon Feb  9 14:20:58 2009//

// CVS Reference       : /SYS_SAM3U4.pl/1.4/Fri Oct 17 13:27:57 2008//

// CVS Reference       : /HMATRIX2_SAM3U4.pl/1.3/Mon Mar  2 10:12:07 2009//

// CVS Reference       : /PMC_SAM3U4.pl/1.7/Fri Oct 17 13:27:54 2008//

// CVS Reference       : /EBI_SAM9260.pl/1.1/Fri Sep 30 12:12:14 2005//

// CVS Reference       : /EFC2_SAM3U4.pl/1.3/Mon Mar  2 10:12:06 2009//

// CVS Reference       : /HSDRAMC1_6100A.pl/1.2/Mon Aug  9 10:52:25 2004//

// CVS Reference       : /HSMC4_xxxx.pl/1.9/Fri Oct 17 13:27:56 2008//

// CVS Reference       : /HECC_6143A.pl/1.1/Wed Feb  9 17:16:57 2005//

// CVS Reference       : /CORTEX_M3_NVIC.pl/1.7/Tue Jan 27 16:16:24 2009//

// CVS Reference       : /CORTEX_M3_MPU.pl/1.3/Fri Oct 17 13:27:48 2008//

// CVS Reference       : /CORTEX_M3.pl/1.1/Mon Sep 15 15:22:06 2008//

// CVS Reference       : /PDC_6074C.pl/1.2/Thu Feb  3 09:02:11 2005//

// CVS Reference       : /DBGU_SAM3U4.pl/1.2/Fri Oct 17 13:27:49 2008//

// CVS Reference       : /PIO3_xxxx.pl/1.6/Mon Mar  9 10:43:37 2009//

// CVS Reference       : /RSTC_6098A.pl/1.4/Fri Oct 17 13:27:55 2008//

// CVS Reference       : /SHDWC_6122A.pl/1.3/Wed Oct  6 14:16:58 2004//

// CVS Reference       : /SUPC_SAM3U4.pl/1.2/Thu Jun  5 15:27:27 2008//

// CVS Reference       : /RTTC_6081A.pl/1.2/Thu Nov  4 13:57:22 2004//

// CVS Reference       : /PITC_6079A.pl/1.2/Thu Nov  4 13:56:22 2004//

// CVS Reference       : /WDTC_6080A.pl/1.3/Thu Nov  4 13:58:52 2004//

// CVS Reference       : /TC_6082A.pl/1.8/Fri Oct 17 13:27:58 2008//

// CVS Reference       : /MCI_6101F.pl/1.3/Fri Jan 23 09:15:32 2009//

// CVS Reference       : /TWI_6061B.pl/1.3/Fri Oct 17 13:27:59 2008//

// CVS Reference       : /US_6089J.pl/1.3/Fri Oct 17 13:27:59 2008//

// CVS Reference       : /SSC_6078B.pl/1.3/Fri Oct 17 13:27:57 2008//

// CVS Reference       : /SPI2.pl/1.4/Mon Mar  9 08:56:28 2009//

// CVS Reference       : /PWM_6343B_V400.pl/1.3/Fri Oct 17 13:27:54 2008//

// CVS Reference       : /HDMA_SAM3U4.pl/1.3/Fri Oct 17 13:27:51 2008//

// CVS Reference       : /UDPHS_SAM9_7ept6dma4iso.pl/1.4/Tue Jun 24 13:05:14 2008//

// CVS Reference       : /ADC_SAM3UE.pl/1.4/Fri Feb 20 12:19:18 2009//

// CVS Reference       : /RTC_1245D.pl/1.3/Fri Sep 17 14:01:31 2004//

//  ----------------------------------------------------------------------------

#ifndef AT91SAM3U4_H

#define AT91SAM3U4_H

#ifndef __ASSEMBLY__

typedef volatile unsigned int AT91_REG;// Hardware register definition

#define AT91_CAST(a) (a)

#else

#define AT91_CAST(a)

#endif

// *****************************************************************************

//              SOFTWARE API DEFINITION  FOR System Peripherals

// *****************************************************************************

#ifndef __ASSEMBLY__

typedef struct _AT91S_SYS {

        AT91_REG         HSMC4_CFG;     // Configuration Register

        AT91_REG         HSMC4_CTRL;    // Control Register

        AT91_REG         HSMC4_SR;      // Status Register

        AT91_REG         HSMC4_IER;     // Interrupt Enable Register

        AT91_REG         HSMC4_IDR;     // Interrupt Disable Register

        AT91_REG         HSMC4_IMR;     // Interrupt Mask Register

        AT91_REG         HSMC4_ADDR;    // Address Cycle Zero Register

        AT91_REG         HSMC4_BANK;    // Bank Register

        AT91_REG         HSMC4_ECCCR;   // ECC reset register

        AT91_REG         HSMC4_ECCCMD;  // ECC Page size register

        AT91_REG         HSMC4_ECCSR1;  // ECC Status register 1

        AT91_REG         HSMC4_ECCPR0;  // ECC Parity register 0

        AT91_REG         HSMC4_ECCPR1;  // ECC Parity register 1

        AT91_REG         HSMC4_ECCSR2;  // ECC Status register 2

        AT91_REG         HSMC4_ECCPR2;  // ECC Parity register 2

        AT91_REG         HSMC4_ECCPR3;  // ECC Parity register 3

        AT91_REG         HSMC4_ECCPR4;  // ECC Parity register 4

        AT91_REG         HSMC4_ECCPR5;  // ECC Parity register 5

        AT91_REG         HSMC4_ECCPR6;  // ECC Parity register 6

        AT91_REG         HSMC4_ECCPR7;  // ECC Parity register 7

        AT91_REG         HSMC4_ECCPR8;  // ECC Parity register 8

        AT91_REG         HSMC4_ECCPR9;  // ECC Parity register 9

        AT91_REG         HSMC4_ECCPR10;         // ECC Parity register 10

        AT91_REG         HSMC4_ECCPR11;         // ECC Parity register 11

        AT91_REG         HSMC4_ECCPR12;         // ECC Parity register 12

        AT91_REG         HSMC4_ECCPR13;         // ECC Parity register 13

        AT91_REG         HSMC4_ECCPR14;         // ECC Parity register 14

        AT91_REG         HSMC4_Eccpr15;         // ECC Parity register 15

        AT91_REG         Reserved0[40];         // 

        AT91_REG         HSMC4_OCMS;    // OCMS MODE register

        AT91_REG         HSMC4_KEY1;    // KEY1 Register

        AT91_REG         HSMC4_KEY2;    // KEY2 Register

        AT91_REG         Reserved1[50];         // 

        AT91_REG         HSMC4_WPCR;    // Write Protection Control register

        AT91_REG         HSMC4_WPSR;    // Write Protection Status Register

        AT91_REG         HSMC4_ADDRSIZE;        // Write Protection Status Register

        AT91_REG         HSMC4_IPNAME1;         // Write Protection Status Register

        AT91_REG         HSMC4_IPNAME2;         // Write Protection Status Register

        AT91_REG         HSMC4_FEATURES;        // Write Protection Status Register

        AT91_REG         HSMC4_VER;     // HSMC4 Version Register

        AT91_REG         HMATRIX_MCFG0;         //  Master Configuration Register 0 : ARM I and D

        AT91_REG         HMATRIX_MCFG1;         //  Master Configuration Register 1 : ARM S

        AT91_REG         HMATRIX_MCFG2;         //  Master Configuration Register 2

        AT91_REG         HMATRIX_MCFG3;         //  Master Configuration Register 3

        AT91_REG         HMATRIX_MCFG4;         //  Master Configuration Register 4

        AT91_REG         HMATRIX_MCFG5;         //  Master Configuration Register 5

        AT91_REG         HMATRIX_MCFG6;         //  Master Configuration Register 6

        AT91_REG         HMATRIX_MCFG7;         //  Master Configuration Register 7

        AT91_REG         Reserved2[8];  // 

        AT91_REG         HMATRIX_SCFG0;         //  Slave Configuration Register 0

        AT91_REG         HMATRIX_SCFG1;         //  Slave Configuration Register 1

        AT91_REG         HMATRIX_SCFG2;         //  Slave Configuration Register 2

        AT91_REG         HMATRIX_SCFG3;         //  Slave Configuration Register 3

        AT91_REG         HMATRIX_SCFG4;         //  Slave Configuration Register 4

        AT91_REG         HMATRIX_SCFG5;         //  Slave Configuration Register 5

        AT91_REG         HMATRIX_SCFG6;         //  Slave Configuration Register 6

        AT91_REG         HMATRIX_SCFG7;         //  Slave Configuration Register 5

        AT91_REG         HMATRIX_SCFG8;         //  Slave Configuration Register 8

        AT91_REG         Reserved3[43];         // 

        AT91_REG         HMATRIX_SFR0 ;         //  Special Function Register 0

        AT91_REG         HMATRIX_SFR1 ;         //  Special Function Register 1

        AT91_REG         HMATRIX_SFR2 ;         //  Special Function Register 2

        AT91_REG         HMATRIX_SFR3 ;         //  Special Function Register 3

        AT91_REG         HMATRIX_SFR4 ;         //  Special Function Register 4

        AT91_REG         HMATRIX_SFR5 ;         //  Special Function Register 5

        AT91_REG         HMATRIX_SFR6 ;         //  Special Function Register 6

        AT91_REG         HMATRIX_SFR7 ;         //  Special Function Register 7

        AT91_REG         HMATRIX_SFR8 ;         //  Special Function Register 8

        AT91_REG         HMATRIX_SFR9 ;         //  Special Function Register 9

        AT91_REG         HMATRIX_SFR10;         //  Special Function Register 10

        AT91_REG         HMATRIX_SFR11;         //  Special Function Register 11

        AT91_REG         HMATRIX_SFR12;         //  Special Function Register 12

        AT91_REG         HMATRIX_SFR13;         //  Special Function Register 13

        AT91_REG         HMATRIX_SFR14;         //  Special Function Register 14

        AT91_REG         HMATRIX_SFR15;         //  Special Function Register 15

        AT91_REG         Reserved4[39];         // 

        AT91_REG         HMATRIX_ADDRSIZE;      // HMATRIX2 ADDRSIZE REGISTER 

        AT91_REG         HMATRIX_IPNAME1;       // HMATRIX2 IPNAME1 REGISTER 

        AT91_REG         HMATRIX_IPNAME2;       // HMATRIX2 IPNAME2 REGISTER 

        AT91_REG         HMATRIX_FEATURES;      // HMATRIX2 FEATURES REGISTER 

        AT91_REG         HMATRIX_VER;   // HMATRIX2 VERSION REGISTER 

        AT91_REG         PMC_SCER;      // System Clock Enable Register

        AT91_REG         PMC_SCDR;      // System Clock Disable Register

        AT91_REG         PMC_SCSR;      // System Clock Status Register

        AT91_REG         Reserved5[1];  // 

        AT91_REG         PMC_PCER;      // Peripheral Clock Enable Register

        AT91_REG         PMC_PCDR;      // Peripheral Clock Disable Register

        AT91_REG         PMC_PCSR;      // Peripheral Clock Status Register

        AT91_REG         PMC_UCKR;      // UTMI Clock Configuration Register

        AT91_REG         PMC_MOR;       // Main Oscillator Register

        AT91_REG         PMC_MCFR;      // Main Clock  Frequency Register

        AT91_REG         PMC_PLLAR;     // PLL Register

        AT91_REG         Reserved6[1];  // 

        AT91_REG         PMC_MCKR;      // Master Clock Register

        AT91_REG         Reserved7[3];  // 

        AT91_REG         PMC_PCKR[8];   // Programmable Clock Register

        AT91_REG         PMC_IER;       // Interrupt Enable Register

        AT91_REG         PMC_IDR;       // Interrupt Disable Register

        AT91_REG         PMC_SR;        // Status Register

        AT91_REG         PMC_IMR;       // Interrupt Mask Register

        AT91_REG         PMC_FSMR;      // Fast Startup Mode Register

        AT91_REG         PMC_FSPR;      // Fast Startup Polarity Register

        AT91_REG         PMC_FOCR;      // Fault Output Clear Register

        AT91_REG         Reserved8[28];         // 

        AT91_REG         PMC_ADDRSIZE;  // PMC ADDRSIZE REGISTER 

        AT91_REG         PMC_IPNAME1;   // PMC IPNAME1 REGISTER 

        AT91_REG         PMC_IPNAME2;   // PMC IPNAME2 REGISTER 

        AT91_REG         PMC_FEATURES;  // PMC FEATURES REGISTER 

        AT91_REG         PMC_VER;       // APMC VERSION REGISTER

        AT91_REG         Reserved9[64];         // 

        AT91_REG         DBGU_CR;       // Control Register

        AT91_REG         DBGU_MR;       // Mode Register

        AT91_REG         DBGU_IER;      // Interrupt Enable Register

        AT91_REG         DBGU_IDR;      // Interrupt Disable Register

        AT91_REG         DBGU_IMR;      // Interrupt Mask Register

        AT91_REG         DBGU_CSR;      // Channel Status Register

        AT91_REG         DBGU_RHR;      // Receiver Holding Register

        AT91_REG         DBGU_THR;      // Transmitter Holding Register

        AT91_REG         DBGU_BRGR;     // Baud Rate Generator Register

        AT91_REG         Reserved10[9];         // 

        AT91_REG         DBGU_FNTR;     // Force NTRST Register

        AT91_REG         Reserved11[40];        // 

        AT91_REG         DBGU_ADDRSIZE;         // DBGU ADDRSIZE REGISTER 

        AT91_REG         DBGU_IPNAME1;  // DBGU IPNAME1 REGISTER 

        AT91_REG         DBGU_IPNAME2;  // DBGU IPNAME2 REGISTER 

        AT91_REG         DBGU_FEATURES;         // DBGU FEATURES REGISTER 

        AT91_REG         DBGU_VER;      // DBGU VERSION REGISTER 

        AT91_REG         DBGU_RPR;      // Receive Pointer Register

        AT91_REG         DBGU_RCR;      // Receive Counter Register

        AT91_REG         DBGU_TPR;      // Transmit Pointer Register

        AT91_REG         DBGU_TCR;      // Transmit Counter Register

        AT91_REG         DBGU_RNPR;     // Receive Next Pointer Register

        AT91_REG         DBGU_RNCR;     // Receive Next Counter Register

        AT91_REG         DBGU_TNPR;     // Transmit Next Pointer Register

        AT91_REG         DBGU_TNCR;     // Transmit Next Counter Register

        AT91_REG         DBGU_PTCR;     // PDC Transfer Control Register

        AT91_REG         DBGU_PTSR;     // PDC Transfer Status Register

        AT91_REG         Reserved12[6];         // 

        AT91_REG         DBGU_CIDR;     // Chip ID Register

        AT91_REG         DBGU_EXID;     // Chip ID Extension Register

        AT91_REG         Reserved13[46];        // 

        AT91_REG         EFC0_FMR;      // EFC Flash Mode Register

        AT91_REG         EFC0_FCR;      // EFC Flash Command Register

        AT91_REG         EFC0_FSR;      // EFC Flash Status Register

        AT91_REG         EFC0_FRR;      // EFC Flash Result Register

        AT91_REG         Reserved14[1];         // 

        AT91_REG         EFC0_FVR;      // EFC Flash Version Register

        AT91_REG         Reserved15[122];       // 

        AT91_REG         EFC1_FMR;      // EFC Flash Mode Register

        AT91_REG         EFC1_FCR;      // EFC Flash Command Register

        AT91_REG         EFC1_FSR;      // EFC Flash Status Register

        AT91_REG         EFC1_FRR;      // EFC Flash Result Register

        AT91_REG         Reserved16[1];         // 

        AT91_REG         EFC1_FVR;      // EFC Flash Version Register

        AT91_REG         Reserved17[122];       // 

        AT91_REG         PIOA_PER;      // PIO Enable Register

        AT91_REG         PIOA_PDR;      // PIO Disable Register

        AT91_REG         PIOA_PSR;      // PIO Status Register

        AT91_REG         Reserved18[1];         // 

        AT91_REG         PIOA_OER;      // Output Enable Register

        AT91_REG         PIOA_ODR;      // Output Disable Registerr

        AT91_REG         PIOA_OSR;      // Output Status Register

        AT91_REG         Reserved19[1];         // 

        AT91_REG         PIOA_IFER;     // Input Filter Enable Register

        AT91_REG         PIOA_IFDR;     // Input Filter Disable Register

        AT91_REG         PIOA_IFSR;     // Input Filter Status Register

        AT91_REG         Reserved20[1];         // 

        AT91_REG         PIOA_SODR;     // Set Output Data Register

        AT91_REG         PIOA_CODR;     // Clear Output Data Register

        AT91_REG         PIOA_ODSR;     // Output Data Status Register

        AT91_REG         PIOA_PDSR;     // Pin Data Status Register

        AT91_REG         PIOA_IER;      // Interrupt Enable Register

        AT91_REG         PIOA_IDR;      // Interrupt Disable Register

        AT91_REG         PIOA_IMR;      // Interrupt Mask Register

        AT91_REG         PIOA_ISR;      // Interrupt Status Register

        AT91_REG         PIOA_MDER;     // Multi-driver Enable Register

        AT91_REG         PIOA_MDDR;     // Multi-driver Disable Register

        AT91_REG         PIOA_MDSR;     // Multi-driver Status Register

        AT91_REG         Reserved21[1];         // 

        AT91_REG         PIOA_PPUDR;    // Pull-up Disable Register

        AT91_REG         PIOA_PPUER;    // Pull-up Enable Register

        AT91_REG         PIOA_PPUSR;    // Pull-up Status Register

        AT91_REG         Reserved22[1];         // 

        AT91_REG         PIOA_ABSR;     // Peripheral AB Select Register

        AT91_REG         Reserved23[3];         // 

        AT91_REG         PIOA_SCIFSR;   // System Clock Glitch Input Filter Select Register

        AT91_REG         PIOA_DIFSR;    // Debouncing Input Filter Select Register

        AT91_REG         PIOA_IFDGSR;   // Glitch or Debouncing Input Filter Clock Selection Status Register

        AT91_REG         PIOA_SCDR;     // Slow Clock Divider Debouncing Register

        AT91_REG         Reserved24[4];         // 

        AT91_REG         PIOA_OWER;     // Output Write Enable Register

        AT91_REG         PIOA_OWDR;     // Output Write Disable Register

        AT91_REG         PIOA_OWSR;     // Output Write Status Register

        AT91_REG         Reserved25[1];         // 

        AT91_REG         PIOA_AIMER;    // Additional Interrupt Modes Enable Register

        AT91_REG         PIOA_AIMDR;    // Additional Interrupt Modes Disables Register

        AT91_REG         PIOA_AIMMR;    // Additional Interrupt Modes Mask Register

        AT91_REG         Reserved26[1];         // 

        AT91_REG         PIOA_ESR;      // Edge Select Register

        AT91_REG         PIOA_LSR;      // Level Select Register

        AT91_REG         PIOA_ELSR;     // Edge/Level Status Register

        AT91_REG         Reserved27[1];         // 

        AT91_REG         PIOA_FELLSR;   // Falling Edge/Low Level Select Register

        AT91_REG         PIOA_REHLSR;   // Rising Edge/ High Level Select Register

        AT91_REG         PIOA_FRLHSR;   // Fall/Rise - Low/High Status Register

        AT91_REG         Reserved28[1];         // 

        AT91_REG         PIOA_LOCKSR;   // Lock Status Register

        AT91_REG         Reserved29[6];         // 

        AT91_REG         PIOA_VER;      // PIO VERSION REGISTER 

        AT91_REG         Reserved30[8];         // 

        AT91_REG         PIOA_KER;      // Keypad Controller Enable Register

        AT91_REG         PIOA_KRCR;     // Keypad Controller Row Column Register

        AT91_REG         PIOA_KDR;      // Keypad Controller Debouncing Register

        AT91_REG         Reserved31[1];         // 

        AT91_REG         PIOA_KIER;     // Keypad Controller Interrupt Enable Register

        AT91_REG         PIOA_KIDR;     // Keypad Controller Interrupt Disable Register

        AT91_REG         PIOA_KIMR;     // Keypad Controller Interrupt Mask Register

        AT91_REG         PIOA_KSR;      // Keypad Controller Status Register

        AT91_REG         PIOA_KKPR;     // Keypad Controller Key Press Register

        AT91_REG         PIOA_KKRR;     // Keypad Controller Key Release Register

        AT91_REG         Reserved32[46];        // 

        AT91_REG         PIOB_PER;      // PIO Enable Register

        AT91_REG         PIOB_PDR;      // PIO Disable Register

        AT91_REG         PIOB_PSR;      // PIO Status Register

        AT91_REG         Reserved33[1];         // 

        AT91_REG         PIOB_OER;      // Output Enable Register

        AT91_REG         PIOB_ODR;      // Output Disable Registerr

        AT91_REG         PIOB_OSR;      // Output Status Register

        AT91_REG         Reserved34[1];         // 

        AT91_REG         PIOB_IFER;     // Input Filter Enable Register

        AT91_REG         PIOB_IFDR;     // Input Filter Disable Register

        AT91_REG         PIOB_IFSR;     // Input Filter Status Register

        AT91_REG         Reserved35[1];         // 

        AT91_REG         PIOB_SODR;     // Set Output Data Register

        AT91_REG         PIOB_CODR;     // Clear Output Data Register

        AT91_REG         PIOB_ODSR;     // Output Data Status Register

        AT91_REG         PIOB_PDSR;     // Pin Data Status Register

        AT91_REG         PIOB_IER;      // Interrupt Enable Register

        AT91_REG         PIOB_IDR;      // Interrupt Disable Register

        AT91_REG         PIOB_IMR;      // Interrupt Mask Register

        AT91_REG         PIOB_ISR;      // Interrupt Status Register

        AT91_REG         PIOB_MDER;     // Multi-driver Enable Register

        AT91_REG         PIOB_MDDR;     // Multi-driver Disable Register

        AT91_REG         PIOB_MDSR;     // Multi-driver Status Register

        AT91_REG         Reserved36[1];         // 

        AT91_REG         PIOB_PPUDR;    // Pull-up Disable Register

        AT91_REG         PIOB_PPUER;    // Pull-up Enable Register

        AT91_REG         PIOB_PPUSR;    // Pull-up Status Register

        AT91_REG         Reserved37[1];         // 

        AT91_REG         PIOB_ABSR;     // Peripheral AB Select Register

        AT91_REG         Reserved38[3];         // 

        AT91_REG         PIOB_SCIFSR;   // System Clock Glitch Input Filter Select Register

        AT91_REG         PIOB_DIFSR;    // Debouncing Input Filter Select Register

        AT91_REG         PIOB_IFDGSR;   // Glitch or Debouncing Input Filter Clock Selection Status Register

        AT91_REG         PIOB_SCDR;     // Slow Clock Divider Debouncing Register

        AT91_REG         Reserved39[4];         // 

        AT91_REG         PIOB_OWER;     // Output Write Enable Register

        AT91_REG         PIOB_OWDR;     // Output Write Disable Register

        AT91_REG         PIOB_OWSR;     // Output Write Status Register

        AT91_REG         Reserved40[1];         // 

        AT91_REG         PIOB_AIMER;    // Additional Interrupt Modes Enable Register

        AT91_REG         PIOB_AIMDR;    // Additional Interrupt Modes Disables Register

        AT91_REG         PIOB_AIMMR;    // Additional Interrupt Modes Mask Register

        AT91_REG         Reserved41[1];         // 

        AT91_REG         PIOB_ESR;      // Edge Select Register

        AT91_REG         PIOB_LSR;      // Level Select Register

        AT91_REG         PIOB_ELSR;     // Edge/Level Status Register

        AT91_REG         Reserved42[1];         // 

        AT91_REG         PIOB_FELLSR;   // Falling Edge/Low Level Select Register

        AT91_REG         PIOB_REHLSR;   // Rising Edge/ High Level Select Register

        AT91_REG         PIOB_FRLHSR;   // Fall/Rise - Low/High Status Register

        AT91_REG         Reserved43[1];         // 

        AT91_REG         PIOB_LOCKSR;   // Lock Status Register

        AT91_REG         Reserved44[6];         // 

        AT91_REG         PIOB_VER;      // PIO VERSION REGISTER 

        AT91_REG         Reserved45[8];         // 

        AT91_REG         PIOB_KER;      // Keypad Controller Enable Register

        AT91_REG         PIOB_KRCR;     // Keypad Controller Row Column Register

        AT91_REG         PIOB_KDR;      // Keypad Controller Debouncing Register

        AT91_REG         Reserved46[1];         // 

        AT91_REG         PIOB_KIER;     // Keypad Controller Interrupt Enable Register

        AT91_REG         PIOB_KIDR;     // Keypad Controller Interrupt Disable Register

        AT91_REG         PIOB_KIMR;     // Keypad Controller Interrupt Mask Register

        AT91_REG         PIOB_KSR;      // Keypad Controller Status Register

        AT91_REG         PIOB_KKPR;     // Keypad Controller Key Press Register

        AT91_REG         PIOB_KKRR;     // Keypad Controller Key Release Register

        AT91_REG         Reserved47[46];        // 

        AT91_REG         PIOC_PER;      // PIO Enable Register

        AT91_REG         PIOC_PDR;      // PIO Disable Register

        AT91_REG         PIOC_PSR;      // PIO Status Register

        AT91_REG         Reserved48[1];         // 

        AT91_REG         PIOC_OER;      // Output Enable Register

        AT91_REG         PIOC_ODR;      // Output Disable Registerr

        AT91_REG         PIOC_OSR;      // Output Status Register

        AT91_REG         Reserved49[1];         // 

        AT91_REG         PIOC_IFER;     // Input Filter Enable Register

        AT91_REG         PIOC_IFDR;     // Input Filter Disable Register

        AT91_REG         PIOC_IFSR;     // Input Filter Status Register

        AT91_REG         Reserved50[1];         // 

        AT91_REG         PIOC_SODR;     // Set Output Data Register

        AT91_REG         PIOC_CODR;     // Clear Output Data Register

        AT91_REG         PIOC_ODSR;     // Output Data Status Register

        AT91_REG         PIOC_PDSR;     // Pin Data Status Register

        AT91_REG         PIOC_IER;      // Interrupt Enable Register

        AT91_REG         PIOC_IDR;      // Interrupt Disable Register

        AT91_REG         PIOC_IMR;      // Interrupt Mask Register

        AT91_REG         PIOC_ISR;      // Interrupt Status Register

        AT91_REG         PIOC_MDER;     // Multi-driver Enable Register

        AT91_REG         PIOC_MDDR;     // Multi-driver Disable Register

        AT91_REG         PIOC_MDSR;     // Multi-driver Status Register

        AT91_REG         Reserved51[1];         // 

        AT91_REG         PIOC_PPUDR;    // Pull-up Disable Register

        AT91_REG         PIOC_PPUER;    // Pull-up Enable Register

        AT91_REG         PIOC_PPUSR;    // Pull-up Status Register

        AT91_REG         Reserved52[1];         // 

        AT91_REG         PIOC_ABSR;     // Peripheral AB Select Register

        AT91_REG         Reserved53[3];         // 

        AT91_REG         PIOC_SCIFSR;   // System Clock Glitch Input Filter Select Register

        AT91_REG         PIOC_DIFSR;    // Debouncing Input Filter Select Register

        AT91_REG         PIOC_IFDGSR;   // Glitch or Debouncing Input Filter Clock Selection Status Register

        AT91_REG         PIOC_SCDR;     // Slow Clock Divider Debouncing Register

        AT91_REG         Reserved54[4];         // 

        AT91_REG         PIOC_OWER;     // Output Write Enable Register

        AT91_REG         PIOC_OWDR;     // Output Write Disable Register

        AT91_REG         PIOC_OWSR;     // Output Write Status Register

        AT91_REG         Reserved55[1];         // 

        AT91_REG         PIOC_AIMER;    // Additional Interrupt Modes Enable Register

        AT91_REG         PIOC_AIMDR;    // Additional Interrupt Modes Disables Register

        AT91_REG         PIOC_AIMMR;    // Additional Interrupt Modes Mask Register

        AT91_REG         Reserved56[1];         // 

        AT91_REG         PIOC_ESR;      // Edge Select Register

        AT91_REG         PIOC_LSR;      // Level Select Register

        AT91_REG         PIOC_ELSR;     // Edge/Level Status Register

        AT91_REG         Reserved57[1];         // 

        AT91_REG         PIOC_FELLSR;   // Falling Edge/Low Level Select Register

        AT91_REG         PIOC_REHLSR;   // Rising Edge/ High Level Select Register

        AT91_REG         PIOC_FRLHSR;   // Fall/Rise - Low/High Status Register

        AT91_REG         Reserved58[1];         // 

        AT91_REG         PIOC_LOCKSR;   // Lock Status Register

        AT91_REG         Reserved59[6];         // 

        AT91_REG         PIOC_VER;      // PIO VERSION REGISTER 

        AT91_REG         Reserved60[8];         // 

        AT91_REG         PIOC_KER;      // Keypad Controller Enable Register

        AT91_REG         PIOC_KRCR;     // Keypad Controller Row Column Register

        AT91_REG         PIOC_KDR;      // Keypad Controller Debouncing Register

        AT91_REG         Reserved61[1];         // 

        AT91_REG         PIOC_KIER;     // Keypad Controller Interrupt Enable Register

        AT91_REG         PIOC_KIDR;     // Keypad Controller Interrupt Disable Register

        AT91_REG         PIOC_KIMR;     // Keypad Controller Interrupt Mask Register

        AT91_REG         PIOC_KSR;      // Keypad Controller Status Register

        AT91_REG         PIOC_KKPR;     // Keypad Controller Key Press Register

        AT91_REG         PIOC_KKRR;     // Keypad Controller Key Release Register

        AT91_REG         Reserved62[46];        // 

        AT91_REG         RSTC_RCR;      // Reset Control Register

        AT91_REG         RSTC_RSR;      // Reset Status Register

        AT91_REG         RSTC_RMR;      // Reset Mode Register

        AT91_REG         Reserved63[1];         // 

        AT91_REG         SUPC_CR;       // Control Register

        AT91_REG         SUPC_BOMR;     // Brown Out Mode Register

        AT91_REG         SUPC_MR;       // Mode Register

        AT91_REG         SUPC_WUMR;     // Wake Up Mode Register

        AT91_REG         SUPC_WUIR;     // Wake Up Inputs Register

        AT91_REG         SUPC_SR;       // Status Register

        AT91_REG         SUPC_FWUTR;    // Flash Wake-up Timer Register

        AT91_REG         Reserved64[1];         // 

        AT91_REG         RTTC_RTMR;     // Real-time Mode Register

        AT91_REG         RTTC_RTAR;     // Real-time Alarm Register

        AT91_REG         RTTC_RTVR;     // Real-time Value Register

        AT91_REG         RTTC_RTSR;     // Real-time Status Register

        AT91_REG         Reserved65[4];         // 

        AT91_REG         WDTC_WDCR;     // Watchdog Control Register

        AT91_REG         WDTC_WDMR;     // Watchdog Mode Register

        AT91_REG         WDTC_WDSR;     // Watchdog Status Register

        AT91_REG         Reserved66[1];         // 

        AT91_REG         RTC_CR;        // Control Register

        AT91_REG         RTC_MR;        // Mode Register

        AT91_REG         RTC_TIMR;      // Time Register

        AT91_REG         RTC_CALR;      // Calendar Register

        AT91_REG         RTC_TIMALR;    // Time Alarm Register

        AT91_REG         RTC_CALALR;    // Calendar Alarm Register

        AT91_REG         RTC_SR;        // Status Register

        AT91_REG         RTC_SCCR;      // Status Clear Command Register

        AT91_REG         RTC_IER;       // Interrupt Enable Register

        AT91_REG         RTC_IDR;       // Interrupt Disable Register

        AT91_REG         RTC_IMR;       // Interrupt Mask Register

        AT91_REG         RTC_VER;       // Valid Entry Register

        AT91_REG         SYS_GPBR[8];   // General Purpose Register

        AT91_REG         Reserved67[19];        // 

        AT91_REG         RSTC_VER;      // Version Register

} AT91S_SYS, *AT91PS_SYS;

#else

#define GPBR            (AT91_CAST(AT91_REG *)  0x00001290) // (GPBR) General Purpose Register

#endif

// -------- GPBR : (SYS Offset: 0x1290) GPBR General Purpose Register -------- 

#define AT91C_GPBR_GPRV       (0x0 <<  0) // (SYS) General Purpose Register Value

// *****************************************************************************

//              SOFTWARE API DEFINITION  FOR HSMC4 Chip Select interface

// *****************************************************************************

#ifndef __ASSEMBLY__

typedef struct _AT91S_HSMC4_CS {

        AT91_REG         HSMC4_SETUP;   // Setup Register

        AT91_REG         HSMC4_PULSE;   // Pulse Register

        AT91_REG         HSMC4_CYCLE;   // Cycle Register

        AT91_REG         HSMC4_TIMINGS;         // Timmings Register

        AT91_REG         HSMC4_MODE;    // Mode Register

} AT91S_HSMC4_CS, *AT91PS_HSMC4_CS;

#else

#define HSMC4_SETUP     (AT91_CAST(AT91_REG *)  0x00000000) // (HSMC4_SETUP) Setup Register

#define HSMC4_PULSE     (AT91_CAST(AT91_REG *)  0x00000004) // (HSMC4_PULSE) Pulse Register

#define HSMC4_CYCLE     (AT91_CAST(AT91_REG *)  0x00000008) // (HSMC4_CYCLE) Cycle Register

#define HSMC4_TIMINGS   (AT91_CAST(AT91_REG *)  0x0000000C) // (HSMC4_TIMINGS) Timmings Register

#define HSMC4_MODE      (AT91_CAST(AT91_REG *)  0x00000010) // (HSMC4_MODE) Mode Register

#endif

// -------- HSMC4_SETUP : (HSMC4_CS Offset: 0x0) HSMC4 SETUP -------- 

#define AT91C_HSMC4_NWE_SETUP (0x3F <<  0) // (HSMC4_CS) NWE Setup length

#define AT91C_HSMC4_NCS_WR_SETUP (0x3F <<  8) // (HSMC4_CS) NCS Setup length in Write access

#define AT91C_HSMC4_NRD_SETUP (0x3F << 16) // (HSMC4_CS) NRD Setup length

#define AT91C_HSMC4_NCS_RD_SETUP (0x3F << 24) // (HSMC4_CS) NCS Setup legnth in Read access

// -------- HSMC4_PULSE : (HSMC4_CS Offset: 0x4) HSMC4 PULSE -------- 

#define AT91C_HSMC4_NWE_PULSE (0x3F <<  0) // (HSMC4_CS) NWE Pulse Length

#define AT91C_HSMC4_NCS_WR_PULSE (0x3F <<  8) // (HSMC4_CS) NCS Pulse length in WRITE access

#define AT91C_HSMC4_NRD_PULSE (0x3F << 16) // (HSMC4_CS) NRD Pulse length

#define AT91C_HSMC4_NCS_RD_PULSE (0x3F << 24) // (HSMC4_CS) NCS Pulse length in READ access

// -------- HSMC4_CYCLE : (HSMC4_CS Offset: 0x8) HSMC4 CYCLE -------- 

#define AT91C_HSMC4_NWE_CYCLE (0x1FF <<  0) // (HSMC4_CS) Total Write Cycle Length

#define AT91C_HSMC4_NRD_CYCLE (0x1FF << 16) // (HSMC4_CS) Total Read Cycle Length

// -------- HSMC4_TIMINGS : (HSMC4_CS Offset: 0xc) HSMC4 TIMINGS -------- 

#define AT91C_HSMC4_TCLR      (0xF <<  0) // (HSMC4_CS) CLE to REN low delay

#define AT91C_HSMC4_TADL      (0xF <<  4) // (HSMC4_CS) ALE to data start

#define AT91C_HSMC4_TAR       (0xF <<  8) // (HSMC4_CS) ALE to REN low delay

#define AT91C_HSMC4_OCMSEN    (0x1 << 12) // (HSMC4_CS) Off Chip Memory Scrambling Enable

#define AT91C_HSMC4_TRR       (0xF << 16) // (HSMC4_CS) Ready to REN low delay

#define AT91C_HSMC4_TWB       (0xF << 24) // (HSMC4_CS) WEN high to REN to busy

#define AT91C_HSMC4_RBNSEL    (0x7 << 28) // (HSMC4_CS) Ready/Busy Line Selection

#define AT91C_HSMC4_NFSEL     (0x1 << 31) // (HSMC4_CS) Nand Flash Selection

// -------- HSMC4_MODE : (HSMC4_CS Offset: 0x10) HSMC4 MODE -------- 

#define AT91C_HSMC4_READ_MODE (0x1 <<  0) // (HSMC4_CS) Read Mode

#define AT91C_HSMC4_WRITE_MODE (0x1 <<  1) // (HSMC4_CS) Write Mode

#define AT91C_HSMC4_EXNW_MODE (0x3 <<  4) // (HSMC4_CS) NWAIT Mode

#define         AT91C_HSMC4_EXNW_MODE_NWAIT_DISABLE        (0x0 <<  4) // (HSMC4_CS) External NWAIT disabled.

#define         AT91C_HSMC4_EXNW_MODE_NWAIT_ENABLE_FROZEN  (0x2 <<  4) // (HSMC4_CS) External NWAIT enabled in frozen mode.

#define         AT91C_HSMC4_EXNW_MODE_NWAIT_ENABLE_READY   (0x3 <<  4) // (HSMC4_CS) External NWAIT enabled in ready mode.

#define AT91C_HSMC4_BAT       (0x1 <<  8) // (HSMC4_CS) Byte Access Type

#define         AT91C_HSMC4_BAT_BYTE_SELECT          (0x0 <<  8) // (HSMC4_CS) Write controled by ncs, nbs0, nbs1, nbs2, nbs3. Read controled by ncs, nrd, nbs0, nbs1, nbs2, nbs3.

#define         AT91C_HSMC4_BAT_BYTE_WRITE           (0x1 <<  8) // (HSMC4_CS) Write controled by ncs, nwe0, nwe1, nwe2, nwe3. Read controled by ncs and nrd.

#define AT91C_HSMC4_DBW       (0x3 << 12) // (HSMC4_CS) Data Bus Width

#define         AT91C_HSMC4_DBW_WIDTH_EIGTH_BITS     (0x0 << 12) // (HSMC4_CS) 8 bits.

#define         AT91C_HSMC4_DBW_WIDTH_SIXTEEN_BITS   (0x1 << 12) // (HSMC4_CS) 16 bits.

#define         AT91C_HSMC4_DBW_WIDTH_THIRTY_TWO_BITS (0x2 << 12) // (HSMC4_CS) 32 bits.

#define AT91C_HSMC4_TDF_CYCLES (0xF << 16) // (HSMC4_CS) Data Float Time.

#define AT91C_HSMC4_TDF_MODE  (0x1 << 20) // (HSMC4_CS) TDF Enabled.

#define AT91C_HSMC4_PMEN      (0x1 << 24) // (HSMC4_CS) Page Mode Enabled.

#define AT91C_HSMC4_PS        (0x3 << 28) // (HSMC4_CS) Page Size

#define         AT91C_HSMC4_PS_SIZE_FOUR_BYTES      (0x0 << 28) // (HSMC4_CS) 4 bytes.

#define         AT91C_HSMC4_PS_SIZE_EIGHT_BYTES     (0x1 << 28) // (HSMC4_CS) 8 bytes.

#define         AT91C_HSMC4_PS_SIZE_SIXTEEN_BYTES   (0x2 << 28) // (HSMC4_CS) 16 bytes.

#define         AT91C_HSMC4_PS_SIZE_THIRTY_TWO_BYTES (0x3 << 28) // (HSMC4_CS) 32 bytes.

// *****************************************************************************

//              SOFTWARE API DEFINITION  FOR AHB Static Memory Controller 4 Interface

// *****************************************************************************

#ifndef __ASSEMBLY__

typedef struct _AT91S_HSMC4 {

        AT91_REG         HSMC4_CFG;     // Configuration Register

        AT91_REG         HSMC4_CTRL;    // Control Register

        AT91_REG         HSMC4_SR;      // Status Register

        AT91_REG         HSMC4_IER;     // Interrupt Enable Register

        AT91_REG         HSMC4_IDR;     // Interrupt Disable Register

        AT91_REG         HSMC4_IMR;     // Interrupt Mask Register

        AT91_REG         HSMC4_ADDR;    // Address Cycle Zero Register

        AT91_REG         HSMC4_BANK;    // Bank Register

        AT91_REG         HSMC4_ECCCR;   // ECC reset register

        AT91_REG         HSMC4_ECCCMD;  // ECC Page size register

        AT91_REG         HSMC4_ECCSR1;  // ECC Status register 1

        AT91_REG         HSMC4_ECCPR0;  // ECC Parity register 0

        AT91_REG         HSMC4_ECCPR1;  // ECC Parity register 1

        AT91_REG         HSMC4_ECCSR2;  // ECC Status register 2

        AT91_REG         HSMC4_ECCPR2;  // ECC Parity register 2

        AT91_REG         HSMC4_ECCPR3;  // ECC Parity register 3

        AT91_REG         HSMC4_ECCPR4;  // ECC Parity register 4

        AT91_REG         HSMC4_ECCPR5;  // ECC Parity register 5

        AT91_REG         HSMC4_ECCPR6;  // ECC Parity register 6

        AT91_REG         HSMC4_ECCPR7;  // ECC Parity register 7

        AT91_REG         HSMC4_ECCPR8;  // ECC Parity register 8

        AT91_REG         HSMC4_ECCPR9;  // ECC Parity register 9

        AT91_REG         HSMC4_ECCPR10;         // ECC Parity register 10

        AT91_REG         HSMC4_ECCPR11;         // ECC Parity register 11

        AT91_REG         HSMC4_ECCPR12;         // ECC Parity register 12

        AT91_REG         HSMC4_ECCPR13;         // ECC Parity register 13

        AT91_REG         HSMC4_ECCPR14;         // ECC Parity register 14

        AT91_REG         HSMC4_Eccpr15;         // ECC Parity register 15

        AT91_REG         Reserved0[40];         // 

        AT91_REG         HSMC4_OCMS;    // OCMS MODE register

        AT91_REG         HSMC4_KEY1;    // KEY1 Register

        AT91_REG         HSMC4_KEY2;    // KEY2 Register

        AT91_REG         Reserved1[50];         // 

        AT91_REG         HSMC4_WPCR;    // Write Protection Control register

        AT91_REG         HSMC4_WPSR;    // Write Protection Status Register

        AT91_REG         HSMC4_ADDRSIZE;        // Write Protection Status Register

        AT91_REG         HSMC4_IPNAME1;         // Write Protection Status Register

        AT91_REG         HSMC4_IPNAME2;         // Write Protection Status Register

        AT91_REG         HSMC4_FEATURES;        // Write Protection Status Register

        AT91_REG         HSMC4_VER;     // HSMC4 Version Register

        AT91_REG         HSMC4_DUMMY;   // This rtegister was created only ti have AHB constants

} AT91S_HSMC4, *AT91PS_HSMC4;

#else

#define HSMC4_CFG       (AT91_CAST(AT91_REG *)  0x00000000) // (HSMC4_CFG) Configuration Register

#define HSMC4_CTRL      (AT91_CAST(AT91_REG *)  0x00000004) // (HSMC4_CTRL) Control Register

#define HSMC4_SR        (AT91_CAST(AT91_REG *)  0x00000008) // (HSMC4_SR) Status Register

#define HSMC4_IER       (AT91_CAST(AT91_REG *)  0x0000000C) // (HSMC4_IER) Interrupt Enable Register

#define HSMC4_IDR       (AT91_CAST(AT91_REG *)  0x00000010) // (HSMC4_IDR) Interrupt Disable Register

#define HSMC4_IMR       (AT91_CAST(AT91_REG *)  0x00000014) // (HSMC4_IMR) Interrupt Mask Register

#define HSMC4_ADDR      (AT91_CAST(AT91_REG *)  0x00000018) // (HSMC4_ADDR) Address Cycle Zero Register

#define HSMC4_BANK      (AT91_CAST(AT91_REG *)  0x0000001C) // (HSMC4_BANK) Bank Register

#define HSMC4_ECCCR     (AT91_CAST(AT91_REG *)  0x00000020) // (HSMC4_ECCCR) ECC reset register

#define HSMC4_ECCCMD    (AT91_CAST(AT91_REG *)  0x00000024) // (HSMC4_ECCCMD) ECC Page size register

#define HSMC4_ECCSR1    (AT91_CAST(AT91_REG *)  0x00000028) // (HSMC4_ECCSR1) ECC Status register 1

#define HSMC4_ECCPR0    (AT91_CAST(AT91_REG *)  0x0000002C) // (HSMC4_ECCPR0) ECC Parity register 0

#define HSMC4_ECCPR1    (AT91_CAST(AT91_REG *)  0x00000030) // (HSMC4_ECCPR1) ECC Parity register 1

#define HSMC4_ECCSR2    (AT91_CAST(AT91_REG *)  0x00000034) // (HSMC4_ECCSR2) ECC Status register 2

#define HSMC4_ECCPR2    (AT91_CAST(AT91_REG *)  0x00000038) // (HSMC4_ECCPR2) ECC Parity register 2

#define HSMC4_ECCPR3    (AT91_CAST(AT91_REG *)  0x0000003C) // (HSMC4_ECCPR3) ECC Parity register 3

#define HSMC4_ECCPR4    (AT91_CAST(AT91_REG *)  0x00000040) // (HSMC4_ECCPR4) ECC Parity register 4

#define HSMC4_ECCPR5    (AT91_CAST(AT91_REG *)  0x00000044) // (HSMC4_ECCPR5) ECC Parity register 5

#define HSMC4_ECCPR6    (AT91_CAST(AT91_REG *)  0x00000048) // (HSMC4_ECCPR6) ECC Parity register 6

#define HSMC4_ECCPR7    (AT91_CAST(AT91_REG *)  0x0000004C) // (HSMC4_ECCPR7) ECC Parity register 7

#define HSMC4_ECCPR8    (AT91_CAST(AT91_REG *)  0x00000050) // (HSMC4_ECCPR8) ECC Parity register 8

#define HSMC4_ECCPR9    (AT91_CAST(AT91_REG *)  0x00000054) // (HSMC4_ECCPR9) ECC Parity register 9

#define HSMC4_ECCPR10   (AT91_CAST(AT91_REG *)  0x00000058) // (HSMC4_ECCPR10) ECC Parity register 10

#define HSMC4_ECCPR11   (AT91_CAST(AT91_REG *)  0x0000005C) // (HSMC4_ECCPR11) ECC Parity register 11

#define HSMC4_ECCPR12   (AT91_CAST(AT91_REG *)  0x00000060) // (HSMC4_ECCPR12) ECC Parity register 12

#define HSMC4_ECCPR13   (AT91_CAST(AT91_REG *)  0x00000064) // (HSMC4_ECCPR13) ECC Parity register 13

#define HSMC4_ECCPR14   (AT91_CAST(AT91_REG *)  0x00000068) // (HSMC4_ECCPR14) ECC Parity register 14

#define Hsmc4_Eccpr15   (AT91_CAST(AT91_REG *)  0x0000006C) // (Hsmc4_Eccpr15) ECC Parity register 15

#define HSMC4_OCMS      (AT91_CAST(AT91_REG *)  0x00000110) // (HSMC4_OCMS) OCMS MODE register

#define HSMC4_KEY1      (AT91_CAST(AT91_REG *)  0x00000114) // (HSMC4_KEY1) KEY1 Register

#define HSMC4_KEY2      (AT91_CAST(AT91_REG *)  0x00000118) // (HSMC4_KEY2) KEY2 Register

#define HSMC4_WPCR      (AT91_CAST(AT91_REG *)  0x000001E4) // (HSMC4_WPCR) Write Protection Control register

#define HSMC4_WPSR      (AT91_CAST(AT91_REG *)  0x000001E8) // (HSMC4_WPSR) Write Protection Status Register

#define HSMC4_ADDRSIZE  (AT91_CAST(AT91_REG *)  0x000001EC) // (HSMC4_ADDRSIZE) Write Protection Status Register

#define HSMC4_IPNAME1   (AT91_CAST(AT91_REG *)  0x000001F0) // (HSMC4_IPNAME1) Write Protection Status Register

#define HSMC4_IPNAME2   (AT91_CAST(AT91_REG *)  0x000001F4) // (HSMC4_IPNAME2) Write Protection Status Register

#define HSMC4_FEATURES  (AT91_CAST(AT91_REG *)  0x000001F8) // (HSMC4_FEATURES) Write Protection Status Register

#define HSMC4_VER       (AT91_CAST(AT91_REG *)  0x000001FC) // (HSMC4_VER) HSMC4 Version Register

#define HSMC4_DUMMY     (AT91_CAST(AT91_REG *)  0x00000200) // (HSMC4_DUMMY) This rtegister was created only ti have AHB constants

#endif

// -------- HSMC4_CFG : (HSMC4 Offset: 0x0) Configuration Register -------- 

#define AT91C_HSMC4_PAGESIZE  (0x3 <<  0) // (HSMC4) PAGESIZE field description

#define         AT91C_HSMC4_PAGESIZE_528_Bytes            (0x0) // (HSMC4) 512 bytes plus 16 bytes page size

#define         AT91C_HSMC4_PAGESIZE_1056_Bytes           (0x1) // (HSMC4) 1024 bytes plus 32 bytes page size

#define         AT91C_HSMC4_PAGESIZE_2112_Bytes           (0x2) // (HSMC4) 2048 bytes plus 64 bytes page size

#define         AT91C_HSMC4_PAGESIZE_4224_Bytes           (0x3) // (HSMC4) 4096 bytes plus 128 bytes page size

#define AT91C_HSMC4_WSPARE    (0x1 <<  8) // (HSMC4) Spare area access in Write Mode

#define AT91C_HSMC4_RSPARE    (0x1 <<  9) // (HSMC4) Spare area access in Read Mode

#define AT91C_HSMC4_EDGECTRL  (0x1 << 12) // (HSMC4) Rising/Falling Edge Detection Control

#define AT91C_HSMC4_RBEDGE    (0x1 << 13) // (HSMC4) Ready/Busy Signal edge Detection

#define AT91C_HSMC4_DTOCYC    (0xF << 16) // (HSMC4) Data Timeout Cycle Number

#define AT91C_HSMC4_DTOMUL    (0x7 << 20) // (HSMC4) Data Timeout Multiplier

#define         AT91C_HSMC4_DTOMUL_1                    (0x0 << 20) // (HSMC4) DTOCYC x 1

#define         AT91C_HSMC4_DTOMUL_16                   (0x1 << 20) // (HSMC4) DTOCYC x 16

#define         AT91C_HSMC4_DTOMUL_128                  (0x2 << 20) // (HSMC4) DTOCYC x 128

#define         AT91C_HSMC4_DTOMUL_256                  (0x3 << 20) // (HSMC4) DTOCYC x 256

#define         AT91C_HSMC4_DTOMUL_1024                 (0x4 << 20) // (HSMC4) DTOCYC x 1024

#define         AT91C_HSMC4_DTOMUL_4096                 (0x5 << 20) // (HSMC4) DTOCYC x 4096

#define         AT91C_HSMC4_DTOMUL_65536                (0x6 << 20) // (HSMC4) DTOCYC x 65536

#define         AT91C_HSMC4_DTOMUL_1048576              (0x7 << 20) // (HSMC4) DTOCYC x 1048576

// -------- HSMC4_CTRL : (HSMC4 Offset: 0x4) Control Register -------- 

#define AT91C_HSMC4_NFCEN     (0x1 <<  0) // (HSMC4) Nand Flash Controller Host Enable

#define AT91C_HSMC4_NFCDIS    (0x1 <<  1) // (HSMC4) Nand Flash Controller Host Disable

#define AT91C_HSMC4_HOSTEN    (0x1 <<  8) // (HSMC4) If set to one, the Host controller is activated and perform a data transfer phase.

#define AT91C_HSMC4_HOSTWR    (0x1 << 11) // (HSMC4) If this field is set to one, the host transfers data from the internal SRAM to the Memory Device.

#define AT91C_HSMC4_HOSTCSID  (0x7 << 12) // (HSMC4) Host Controller Chip select Id

#define         AT91C_HSMC4_HOSTCSID_0                    (0x0 << 12) // (HSMC4) CS0

#define         AT91C_HSMC4_HOSTCSID_1                    (0x1 << 12) // (HSMC4) CS1

#define         AT91C_HSMC4_HOSTCSID_2                    (0x2 << 12) // (HSMC4) CS2

#define         AT91C_HSMC4_HOSTCSID_3                    (0x3 << 12) // (HSMC4) CS3

#define         AT91C_HSMC4_HOSTCSID_4                    (0x4 << 12) // (HSMC4) CS4

#define         AT91C_HSMC4_HOSTCSID_5                    (0x5 << 12) // (HSMC4) CS5

#define         AT91C_HSMC4_HOSTCSID_6                    (0x6 << 12) // (HSMC4) CS6

#define         AT91C_HSMC4_HOSTCSID_7                    (0x7 << 12) // (HSMC4) CS7

#define AT91C_HSMC4_VALID     (0x1 << 15) // (HSMC4) When set to 1, a write operation modifies both HOSTCSID and HOSTWR fields.

// -------- HSMC4_SR : (HSMC4 Offset: 0x8) HSMC4 Status Register -------- 

#define AT91C_HSMC4_NFCSTS    (0x1 <<  0) // (HSMC4) Nand Flash Controller status

#define AT91C_HSMC4_RBRISE    (0x1 <<  4) // (HSMC4) Selected Ready Busy Rising Edge Detected flag

#define AT91C_HSMC4_RBFALL    (0x1 <<  5) // (HSMC4) Selected Ready Busy Falling Edge Detected flag

#define AT91C_HSMC4_HOSTBUSY  (0x1 <<  8) // (HSMC4) Host Busy

#define AT91C_HSMC4_HOSTW     (0x1 << 11) // (HSMC4) Host Write/Read Operation

#define AT91C_HSMC4_HOSTCS    (0x7 << 12) // (HSMC4) Host Controller Chip select Id

#define         AT91C_HSMC4_HOSTCS_0                    (0x0 << 12) // (HSMC4) CS0

#define         AT91C_HSMC4_HOSTCS_1                    (0x1 << 12) // (HSMC4) CS1

#define         AT91C_HSMC4_HOSTCS_2                    (0x2 << 12) // (HSMC4) CS2

#define         AT91C_HSMC4_HOSTCS_3                    (0x3 << 12) // (HSMC4) CS3

#define         AT91C_HSMC4_HOSTCS_4                    (0x4 << 12) // (HSMC4) CS4

#define         AT91C_HSMC4_HOSTCS_5                    (0x5 << 12) // (HSMC4) CS5

#define         AT91C_HSMC4_HOSTCS_6                    (0x6 << 12) // (HSMC4) CS6

#define         AT91C_HSMC4_HOSTCS_7                    (0x7 << 12) // (HSMC4) CS7

#define AT91C_HSMC4_XFRDONE   (0x1 << 16) // (HSMC4) Host Data Transfer Terminated

#define AT91C_HSMC4_CMDDONE   (0x1 << 17) // (HSMC4) Command Done

#define AT91C_HSMC4_ECCRDY    (0x1 << 18) // (HSMC4) ECC ready

#define AT91C_HSMC4_DTOE      (0x1 << 20) // (HSMC4) Data timeout Error

#define AT91C_HSMC4_UNDEF     (0x1 << 21) // (HSMC4) Undefined Area Error

#define AT91C_HSMC4_AWB       (0x1 << 22) // (HSMC4) Accessing While Busy Error

#define AT91C_HSMC4_HASE      (0x1 << 23) // (HSMC4) Host Controller Access Size Error

#define AT91C_HSMC4_RBEDGE0   (0x1 << 24) // (HSMC4) Ready Busy line 0 Edge detected

#define AT91C_HSMC4_RBEDGE1   (0x1 << 25) // (HSMC4) Ready Busy line 1 Edge detected

#define AT91C_HSMC4_RBEDGE2   (0x1 << 26) // (HSMC4) Ready Busy line 2 Edge detected

#define AT91C_HSMC4_RBEDGE3   (0x1 << 27) // (HSMC4) Ready Busy line 3 Edge detected

#define AT91C_HSMC4_RBEDGE4   (0x1 << 28) // (HSMC4) Ready Busy line 4 Edge detected

#define AT91C_HSMC4_RBEDGE5   (0x1 << 29) // (HSMC4) Ready Busy line 5 Edge detected

#define AT91C_HSMC4_RBEDGE6   (0x1 << 30) // (HSMC4) Ready Busy line 6 Edge detected

#define AT91C_HSMC4_RBEDGE7   (0x1 << 31) // (HSMC4) Ready Busy line 7 Edge detected

// -------- HSMC4_IER : (HSMC4 Offset: 0xc) HSMC4 Interrupt Enable Register -------- 

// -------- HSMC4_IDR : (HSMC4 Offset: 0x10) HSMC4 Interrupt Disable Register -------- 

// -------- HSMC4_IMR : (HSMC4 Offset: 0x14) HSMC4 Interrupt Mask Register -------- 

// -------- HSMC4_ADDR : (HSMC4 Offset: 0x18) Address Cycle Zero Register -------- 

#define AT91C_HSMC4_ADDRCYCLE0 (0xFF <<  0) // (HSMC4) Nand Flash Array Address cycle 0

// -------- HSMC4_BANK : (HSMC4 Offset: 0x1c) Bank Register -------- 

#define AT91C_BANK            (0x7 <<  0) // (HSMC4) Bank identifier

#define         AT91C_BANK_0                    (0x0) // (HSMC4) BANK0

#define         AT91C_BANK_1                    (0x1) // (HSMC4) BANK1

#define         AT91C_BANK_2                    (0x2) // (HSMC4) BANK2

#define         AT91C_BANK_3                    (0x3) // (HSMC4) BANK3

#define         AT91C_BANK_4                    (0x4) // (HSMC4) BANK4

#define         AT91C_BANK_5                    (0x5) // (HSMC4) BANK5

#define         AT91C_BANK_6                    (0x6) // (HSMC4) BANK6

#define         AT91C_BANK_7                    (0x7) // (HSMC4) BANK7

// -------- HSMC4_ECCCR : (HSMC4 Offset: 0x20) ECC Control Register -------- 

#define AT91C_HSMC4_ECCRESET  (0x1 <<  0) // (HSMC4) Reset ECC

// -------- HSMC4_ECCCMD : (HSMC4 Offset: 0x24) ECC mode register -------- 

#define AT91C_ECC_PAGE_SIZE   (0x3 <<  0) // (HSMC4) Nand Flash page size

#define AT91C_ECC_TYPCORRECT  (0x3 <<  4) // (HSMC4) Nand Flash page size

#define         AT91C_ECC_TYPCORRECT_ONE_PER_PAGE         (0x0 <<  4) // (HSMC4) 

#define         AT91C_ECC_TYPCORRECT_ONE_EVERY_256_BYTES  (0x1 <<  4) // (HSMC4) 

#define         AT91C_ECC_TYPCORRECT_ONE_EVERY_512_BYTES  (0x2 <<  4) // (HSMC4) 

// -------- HSMC4_ECCSR1 : (HSMC4 Offset: 0x28) ECC Status Register 1 -------- 

#define AT91C_HSMC4_ECC_RECERR0 (0x1 <<  0) // (HSMC4) Recoverable Error

#define AT91C_HSMC4_ECC_ECCERR0 (0x1 <<  1) // (HSMC4) ECC Error

#define AT91C_HSMC4_ECC_MULERR0 (0x1 <<  2) // (HSMC4) Multiple Error

#define AT91C_HSMC4_ECC_RECERR1 (0x1 <<  4) // (HSMC4) Recoverable Error

#define AT91C_HSMC4_ECC_ECCERR1 (0x1 <<  5) // (HSMC4) ECC Error

#define AT91C_HSMC4_ECC_MULERR1 (0x1 <<  6) // (HSMC4) Multiple Error

#define AT91C_HSMC4_ECC_RECERR2 (0x1 <<  8) // (HSMC4) Recoverable Error

#define AT91C_HSMC4_ECC_ECCERR2 (0x1 <<  9) // (HSMC4) ECC Error

#define AT91C_HSMC4_ECC_MULERR2 (0x1 << 10) // (HSMC4) Multiple Error

#define AT91C_HSMC4_ECC_RECERR3 (0x1 << 12) // (HSMC4) Recoverable Error

#define AT91C_HSMC4_ECC_ECCERR3 (0x1 << 13) // (HSMC4) ECC Error

#define AT91C_HSMC4_ECC_MULERR3 (0x1 << 14) // (HSMC4) Multiple Error

#define AT91C_HSMC4_ECC_RECERR4 (0x1 << 16) // (HSMC4) Recoverable Error

#define AT91C_HSMC4_ECC_ECCERR4 (0x1 << 17) // (HSMC4) ECC Error

#define AT91C_HSMC4_ECC_MULERR4 (0x1 << 18) // (HSMC4) Multiple Error

#define AT91C_HSMC4_ECC_RECERR5 (0x1 << 20) // (HSMC4) Recoverable Error

#define AT91C_HSMC4_ECC_ECCERR5 (0x1 << 21) // (HSMC4) ECC Error

#define AT91C_HSMC4_ECC_MULERR5 (0x1 << 22) // (HSMC4) Multiple Error

#define AT91C_HSMC4_ECC_RECERR6 (0x1 << 24) // (HSMC4) Recoverable Error

#define AT91C_HSMC4_ECC_ECCERR6 (0x1 << 25) // (HSMC4) ECC Error