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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [CORTEX_AT91SAM3U256_IAR/] [system/] [board_memories.c] - Blame information for rev 580

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Line No. Rev Author Line
1 580 jeremybenn
/* ----------------------------------------------------------------------------
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 *         ATMEL Microcontroller Software Support
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 * ----------------------------------------------------------------------------
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 * Copyright (c) 2009, Atmel Corporation
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 *
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 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions are met:
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 *
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 * - Redistributions of source code must retain the above copyright notice,
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 * this list of conditions and the disclaimer below.
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 *
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 * Atmel's name may not be used to endorse or promote products derived from
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 * this software without specific prior written permission.
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 *
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 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 * ----------------------------------------------------------------------------
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 */
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/*
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    Title: Memories implementation
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*/
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//------------------------------------------------------------------------------
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//         Headers
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//------------------------------------------------------------------------------
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#include <board.h>
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//------------------------------------------------------------------------------
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//         Exported functions
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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/// Dummy function to initialize and configure the SDRAM
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//------------------------------------------------------------------------------
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void BOARD_ConfigureSdram(unsigned char busWidth)
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{
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}
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//------------------------------------------------------------------------------
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/// Configures the EBI for NandFlash access. Pins must be configured after or
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/// before calling this function.
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//------------------------------------------------------------------------------
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void BOARD_ConfigureNandFlash(unsigned char busWidth)
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{
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    AT91PS_HSMC4 pHSMC4 = AT91C_BASE_HSMC4;
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    AT91PS_HSMC4_CS pSMC = AT91C_BASE_HSMC4_CS1;
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    // Open EBI clock
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    AT91C_BASE_PMC->PMC_PCER = (1<< AT91C_ID_HSMC4);
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#ifdef CHIP_NAND_CTRL    
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    // Enable the Nand Flash Controller
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    pHSMC4 ->HSMC4_CTRL = AT91C_HSMC4_NFCEN;
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#endif
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    pSMC->HSMC4_SETUP = 0
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                    | ((0 <<  0) & AT91C_HSMC4_NWE_SETUP)
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                    | ((1 <<  8) & AT91C_HSMC4_NCS_WR_SETUP)
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                    | ((0 << 16) & AT91C_HSMC4_NRD_SETUP)
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                    | ((1 << 24) & AT91C_HSMC4_NCS_RD_SETUP);
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    pSMC->HSMC4_PULSE = 0
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                    | ((2 <<  0) & AT91C_HSMC4_NWE_PULSE)
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                    | ((3 <<  8) & AT91C_HSMC4_NCS_WR_PULSE)
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                    | ((3 << 16) & AT91C_HSMC4_NRD_PULSE)
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                    | ((4 << 24) & AT91C_HSMC4_NCS_RD_PULSE);
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    pSMC->HSMC4_CYCLE = 0
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                  | ((4 <<  0) & AT91C_HSMC4_NWE_CYCLE)
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                  | ((7 << 16) & AT91C_HSMC4_NRD_CYCLE);
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    pSMC->HSMC4_TIMINGS = 0
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                    | ((1 <<  0) & AT91C_HSMC4_TCLR) // CLE to REN
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                    | ((2 <<  4) & AT91C_HSMC4_TADL) // ALE to Data
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                    | ((1 <<  8) & AT91C_HSMC4_TAR)  // ALE to REN
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                    | ((1 << 16) & AT91C_HSMC4_TRR)  // Ready to REN
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                    | ((2 << 24) & AT91C_HSMC4_TWB)  // WEN to REN
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                    | (7<<28)
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                    |(AT91C_HSMC4_NFSEL)              // Nand Flash Timing
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                    ;
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    if (busWidth == 8) {
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        pSMC->HSMC4_MODE = AT91C_HSMC4_DBW_WIDTH_EIGTH_BITS | AT91C_HSMC4_READ_MODE | AT91C_HSMC4_WRITE_MODE;
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    }
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    else if (busWidth == 16) {
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        pSMC->HSMC4_MODE = AT91C_HSMC4_DBW_WIDTH_SIXTEEN_BITS | AT91C_HSMC4_READ_MODE | AT91C_HSMC4_WRITE_MODE;
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    }
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}
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