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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [CORTEX_EFMG890F128_IAR/] [bsp/] [dvk_ebi.c] - Blame information for rev 615

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Line No. Rev Author Line
1 595 jeremybenn 
/**************************************************************************//**
2 
 * @file
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 * @brief EBI implementation of Board Control interface
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 *        This implementation works for devices w/o LCD display on the
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 *        MCU module, specifically the EFM32_G2xx_DK development board
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 * @author Energy Micro AS
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 * @version 1.0.1
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 ******************************************************************************
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 * @section License
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 * <b>(C) Copyright 2009 Energy Micro AS, http://www.energymicro.com</b>
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 ******************************************************************************
12 
 *
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 * This source code is the property of Energy Micro AS. The source and compiled
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 * code may only be used on Energy Micro "EFM32" microcontrollers.
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 *
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 * This copyright notice may not be removed from the source code nor changed.
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 *
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 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
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 * obligation to support this Software. Energy Micro AS is providing the
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 * Software "AS IS", with no express or implied warranties of any kind,
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 * including, but not limited to, any implied warranties of merchantability
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 * or fitness for any particular purpose or warranties against infringement
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 * of any proprietary rights of a third party.
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 *
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 * Energy Micro AS will not be liable for any consequential, incidental, or
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 * special damages, or any other relief, or for any claim by any third party,
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 * arising from your use of this Software.
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 *
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 *****************************************************************************/
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#include "efm32.h"
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#include "dvk.h"
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#include "dvk_bcregisters.h"
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/**************************************************************************//**
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 * @brief Configure EBI (external bus interface) for Board Control register
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 * access
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 *****************************************************************************/
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void DVK_EBI_configure(void)
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{
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  GPIO_TypeDef *gpio = GPIO;
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  EBI_TypeDef  *ebi  = EBI;
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  CMU_TypeDef  *cmu  = CMU;
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  /* Run time check if we have EBI on-chip capability on this device */
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  switch ((DEVINFO->PART & _DEVINFO_PART_DEVICE_NUMBER_MASK) >>
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          _DEVINFO_PART_DEVICE_NUMBER_SHIFT)
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  {
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  /* Only device types EFM32G 280/290/880 and 890 have EBI capability */
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  case 280:
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  case 290:
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  case 880:
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  case 890:
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    break;
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  default:
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    /* This device do not have EBI capability - use SPI to interface DVK */
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    /* With high probability your project has been configured for an */
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    /* incorrect part number. */
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    while (1) ;
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  }
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  /* Enable clocks */
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  cmu->HFCORECLKEN0 |= CMU_HFCORECLKEN0_EBI;
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  cmu->HFPERCLKEN0  |= CMU_HFPERCLKEN0_GPIO;
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  /* Configure bus connect PC bit 12 active low */
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  gpio->P[2].MODEH |=
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    GPIO_P_MODEH_MODE12_PUSHPULL;
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  gpio->P[2].DOUT &= ~(1UL << 12);
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  /* Configure GPIO pins as push pull */
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  /* EBI AD9..15 */
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  gpio->P[0].MODEL |=
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    (GPIO_P_MODEL_MODE0_PUSHPULL |
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     GPIO_P_MODEL_MODE1_PUSHPULL |
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     GPIO_P_MODEL_MODE2_PUSHPULL |
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     GPIO_P_MODEL_MODE3_PUSHPULL |
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     GPIO_P_MODEL_MODE4_PUSHPULL |
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     GPIO_P_MODEL_MODE5_PUSHPULL |
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     GPIO_P_MODEL_MODE6_PUSHPULL);
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  /* EBI AD8 */
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  gpio->P[0].MODEH |=
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    GPIO_P_MODEH_MODE15_PUSHPULL;
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  /* EBI CS0-CS3 */
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  gpio->P[3].MODEH |=
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    (GPIO_P_MODEH_MODE9_PUSHPULL |
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     GPIO_P_MODEH_MODE10_PUSHPULL |
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     GPIO_P_MODEH_MODE11_PUSHPULL |
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     GPIO_P_MODEH_MODE12_PUSHPULL);
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  /* EBI AD0..7 */
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  gpio->P[4].MODEH |=
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    (GPIO_P_MODEH_MODE8_PUSHPULL |
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     GPIO_P_MODEH_MODE9_PUSHPULL |
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     GPIO_P_MODEH_MODE10_PUSHPULL |
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     GPIO_P_MODEH_MODE11_PUSHPULL |
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     GPIO_P_MODEH_MODE12_PUSHPULL |
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     GPIO_P_MODEH_MODE13_PUSHPULL |
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     GPIO_P_MODEH_MODE14_PUSHPULL |
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     GPIO_P_MODEH_MODE15_PUSHPULL);
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  /* EBI ARDY/ALEN/Wen/Ren */
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  gpio->P[5].MODEL |=
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    (GPIO_P_MODEL_MODE2_PUSHPULL |
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     GPIO_P_MODEL_MODE3_PUSHPULL |
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     GPIO_P_MODEL_MODE4_PUSHPULL |
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     GPIO_P_MODEL_MODE5_PUSHPULL);
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  /* Configure EBI controller */
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  /* 16 bit address, 16 bit data mode */
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  /* Enable bank 0 address map 0x80000000, FPGA Flash */
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  /* Enable bank 1 address map 0x84000000, FPGA SRAM */
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  /* Enable bank 2 address map 0x88000000, FPGA TFT Display (SSD2119) */
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  /* Enable bank 3 address map 0x8c000000, FPGA Board Control Registers */
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  ebi->CTRL =
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    EBI_CTRL_MODE_D16A16ALE |
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    EBI_CTRL_BANK0EN |
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    EBI_CTRL_BANK1EN |
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    EBI_CTRL_BANK2EN |
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    EBI_CTRL_BANK3EN;
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  /* Setup and hold time */
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  ebi->ADDRTIMING = 3 << _EBI_ADDRTIMING_ADDRHOLD_SHIFT | 3 << _EBI_ADDRTIMING_ADDRSET_SHIFT;
123 
 
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  /* Default values for all write timing registers, read timing conservative */
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  ebi->RDTIMING = 7 << _EBI_RDTIMING_RDSTRB_SHIFT | 3 << _EBI_RDTIMING_RDHOLD_SHIFT | 3 << _EBI_RDTIMING_RDSETUP_SHIFT;
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  ebi->WRTIMING = 7 << _EBI_WRTIMING_WRSTRB_SHIFT | 3 << _EBI_WRTIMING_WRHOLD_SHIFT | 3 << _EBI_WRTIMING_WRSETUP_SHIFT;
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  ebi->POLARITY = _EBI_POLARITY_RESETVALUE;
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  /* Toggle on all chip selects for all banks */
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  ebi->ROUTE =
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    EBI_ROUTE_CS0PEN |
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    EBI_ROUTE_CS1PEN |
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    EBI_ROUTE_CS2PEN |
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    EBI_ROUTE_CS3PEN |
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    EBI_ROUTE_ALEPEN |
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    EBI_ROUTE_EBIPEN;
137 
}
138 
 
139 
 
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/**************************************************************************//**
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 * @brief Initialize EBI
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 * access
143 
 *****************************************************************************/
144 
void DVK_EBI_init(void)
145 
{
146 
  uint16_t ebiMagic;
147 
  int      ctr;
148 
  volatile int i;
149 
 
150 
  /* Configure EBI */
151 
  DVK_EBI_configure();
152 
  /* Verify that EBI access is working, if not kit is in SPI mode and needs to
153 
   * be configured for EBI access */
154 
  ebiMagic = DVK_EBI_readRegister(BC_MAGIC);
155 
  if (ebiMagic != BC_MAGIC_VALUE)
156 
  {
157 
    /* Disable EBI */
158 
    DVK_EBI_disable();
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    /* Enable SPI interface */
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    DVK_SPI_init();
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    /* Set EBI mode - after this SPI access will no longer be available */
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    DVK_SPI_writeRegister(BC_CFG, BC_CFG_EBI);
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    /* Disable SPI */
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    DVK_SPI_disable();
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    /* Now setup EBI again */
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    DVK_EBI_configure();
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    /* Wait until ready */
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    ctr = 0;
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    do {
170 
      /* Check if FPGA responds */
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      ebiMagic = DVK_EBI_readRegister(BC_MAGIC);
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      ctr++;
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      DVK_EBI_writeRegister(BC_LED, ctr);
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    } while (ebiMagic != BC_MAGIC_VALUE);
175 
  }
176 
}
177 
 
178 
/**************************************************************************//**
179 
 * @brief Disable EBI interface, free all GPIO pins
180 
 *****************************************************************************/
181 
void DVK_EBI_disable(void)
182 
{
183 
  GPIO_TypeDef *gpio = GPIO;
184 
  EBI_TypeDef  *ebi  = EBI;
185 
  CMU_TypeDef  *cmu  = CMU;
186 
 
187 
  /* Toggle off all chip selects for all banks */
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  ebi->ROUTE = _EBI_ROUTE_RESETVALUE;
189 
 
190 
  /* Disable EBI controller */
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  ebi->CTRL = _EBI_CTRL_RESETVALUE;
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193 
  /* Disable EBI clock */
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  cmu->HFCORECLKEN0 &= ~(CMU_HFCORECLKEN0_EBI);
195 
 
196 
  /* Disable EBI _BC_BUS_CONNECT */
197 
  gpio->P[2].MODEH &= ~(_GPIO_P_MODEH_MODE12_MASK);
198 
 
199 
  /* Configure GPIO pins as disabled */
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  gpio->P[0].MODEL &= ~(
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    _GPIO_P_MODEL_MODE0_MASK |
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    _GPIO_P_MODEL_MODE1_MASK |
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    _GPIO_P_MODEL_MODE2_MASK |
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    _GPIO_P_MODEL_MODE3_MASK |
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    _GPIO_P_MODEL_MODE4_MASK |
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    _GPIO_P_MODEL_MODE5_MASK |
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    _GPIO_P_MODEL_MODE6_MASK);
208 
  gpio->P[0].MODEH &= ~(_GPIO_P_MODEH_MODE15_MASK);
209 
  gpio->P[3].MODEH &= ~(
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    _GPIO_P_MODEH_MODE9_MASK|
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    _GPIO_P_MODEH_MODE10_MASK|
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    _GPIO_P_MODEH_MODE11_MASK|
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    _GPIO_P_MODEH_MODE12_MASK
214 
    );
215 
  gpio->P[4].MODEH &= ~(
216 
    _GPIO_P_MODEH_MODE8_MASK |
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    _GPIO_P_MODEH_MODE9_MASK |
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    _GPIO_P_MODEH_MODE10_MASK |
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    _GPIO_P_MODEH_MODE11_MASK |
220 
    _GPIO_P_MODEH_MODE12_MASK |
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    _GPIO_P_MODEH_MODE13_MASK |
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    _GPIO_P_MODEH_MODE14_MASK |
223 
    _GPIO_P_MODEH_MODE15_MASK);
224 
  gpio->P[5].MODEL &= ~(
225 
    _GPIO_P_MODEL_MODE2_MASK |
226 
    _GPIO_P_MODEL_MODE3_MASK |
227 
    _GPIO_P_MODEL_MODE4_MASK |
228 
    _GPIO_P_MODEL_MODE5_MASK);
229 
}
230 
 
231 
/**************************************************************************//**
232 
 * @brief Write data into 16-bit board control register
233 
 * @param addr Address to board control register
234 
 * @param data Data to write into register
235 
 *****************************************************************************/
236 
void DVK_EBI_writeRegister(volatile uint16_t *addr, uint16_t data)
237 
{
238 
  *addr = data;
239 
}
240 
 
241 
/**************************************************************************//**
242 
 * @brief Write data into 16-bit board control register
243 
 * @param addr Register to read from
244 
 *****************************************************************************/
245 
uint16_t DVK_EBI_readRegister(volatile uint16_t *addr)
246 
{
247 
  return *addr;
248 
}

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