OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [CORTEX_LM3S102_GCC/] [init/] [startup.c] - Blame information for rev 581

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 581 jeremybenn
//*****************************************************************************
2
//
3
// startup.c - Boot code for Stellaris.
4
//
5
// Copyright (c) 2005,2006 Luminary Micro, Inc.  All rights reserved.
6
//
7
// Software License Agreement
8
//
9
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
10
// exclusively on LMI's Stellaris Family of microcontroller products.
11
//
12
// The software is owned by LMI and/or its suppliers, and is protected under
13
// applicable copyright laws.  All rights are reserved.  Any use in violation
14
// of the foregoing restrictions may subject the user to criminal sanctions
15
// under applicable laws, as well as to civil liability for the breach of the
16
// terms and conditions of this license.
17
//
18
// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
19
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
20
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
21
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
22
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
23
//
24
//*****************************************************************************
25
 
26
//*****************************************************************************
27
//
28
// Forward declaration of the default fault handlers.
29
//
30
//*****************************************************************************
31
void ResetISR(void);
32
static void NmiSR(void);
33
void FaultISR(void);
34
extern void xPortPendSVHandler(void);
35
extern void xPortSysTickHandler(void);
36
extern void vUART_ISR( void );
37
extern void vPortSVCHandler( void );
38
 
39
//*****************************************************************************
40
//
41
// The entry point for the application.
42
//
43
//*****************************************************************************
44
extern void entry(void);
45
 
46
//*****************************************************************************
47
//
48
// Reserve space for the system stack.
49
//
50
//*****************************************************************************
51
#ifndef STACK_SIZE
52
#define STACK_SIZE                              51
53
#endif
54
static unsigned long pulMainStack[STACK_SIZE];
55
 
56
//*****************************************************************************
57
//
58
// The minimal vector table for a Cortex M3.  Note that the proper constructs
59
// must be placed on this to ensure that it ends up at physical address
60
// 0x0000.0000.
61
//
62
//*****************************************************************************
63
__attribute__ ((section("vectors")))
64
void (* const g_pfnVectors[])(void) =
65
{
66
    (void (*)(void))((unsigned long)pulMainStack + sizeof(pulMainStack)),
67
    ResetISR,
68
    NmiSR,
69
    FaultISR,                                                           //FAULT
70
    0,                                      // The MPU fault handler
71
    0,                                      // The bus fault handler
72
    0,                                      // The usage fault handler
73
    0,                                      // Reserved
74
    0,                                      // Reserved
75
    0,                                      // Reserved
76
    0,                                      // Reserved
77
    vPortSVCHandler,                                            // SVCall handler
78
    0,                                      // Debug monitor handler
79
    0,                                      // Reserved
80
    xPortPendSVHandler,                     // The PendSV handler
81
    xPortSysTickHandler,                    // The SysTick handler
82
    0,                      // GPIO Port A
83
    0,                      // GPIO Port B
84
    0,                      // GPIO Port C
85
    0,                      // GPIO Port D
86
    0,                      // GPIO Port E
87
    vUART_ISR                      // UART0 Rx and Tx
88
};
89
 
90
//*****************************************************************************
91
//
92
// The following are constructs created by the linker, indicating where the
93
// the "data" and "bss" segments reside in memory.  The initializers for the
94
// for the "data" segment resides immediately following the "text" segment.
95
//
96
//*****************************************************************************
97
extern unsigned long _etext;
98
extern unsigned long _data;
99
extern unsigned long _edata;
100
extern unsigned long _bss;
101
extern unsigned long _ebss;
102
 
103
//*****************************************************************************
104
//
105
// This is the code that gets called when the processor first starts execution
106
// following a reset event.  Only the absolutely necessary set is performed,
107
// after which the application supplied entry() routine is called.  Any fancy
108
// actions (such as making decisions based on the reset cause register, and
109
// resetting the bits in that register) are left solely in the hands of the
110
// application.
111
//
112
//*****************************************************************************
113
void
114
ResetISR(void)
115
{
116
    unsigned long *pulSrc, *pulDest;
117
 
118
    //
119
    // Copy the data segment initializers from flash to SRAM.
120
    //
121
    pulSrc = &_etext;
122
    for(pulDest = &_data; pulDest < &_edata; )
123
    {
124
        *pulDest++ = *pulSrc++;
125
    }
126
 
127
    //
128
    // Zero fill the bss segment.
129
    //
130
    for(pulDest = &_bss; pulDest < &_ebss; )
131
    {
132
        *pulDest++ = 0;
133
    }
134
 
135
    //
136
    // Call the application's entry point.
137
    //
138
    Main();
139
}
140
 
141
//*****************************************************************************
142
//
143
// This is the code that gets called when the processor receives a NMI.  This
144
// simply enters an infinite loop, preserving the system state for examination
145
// by a debugger.
146
//
147
//*****************************************************************************
148
static void
149
NmiSR(void)
150
{
151
    //
152
    // Enter an infinite loop.
153
    //
154
    while(1)
155
    {
156
    }
157
}
158
 
159
//*****************************************************************************
160
//
161
// This is the code that gets called when the processor receives a fault
162
// interrupt.  This simply enters an infinite loop, preserving the system state
163
// for examination by a debugger.
164
//
165
//*****************************************************************************
166
void
167
FaultISR(void)
168
{
169
    //
170
    // Enter an infinite loop.
171
    //
172
    while(1)
173
    {
174
    }
175
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.